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41. 发明申请

WO0219334A3 FLASH MEMORY ARCHITECTURE WITH SEPARATE STORAGE OF OVERHEAD AND USER DATA 审中-公开
标题翻译：具有独立存储和用户数据的闪存存储器架构
公开(公告)号：WO0219334A3
公开(公告)日：2003-03-27
申请号：PCT/US0126453
申请日：2001-08-24
申请人： LEXAR MEDIA INC
发明人： ESTAKHRI PETRO , NEMAZIE SIAMACK
IPC分类号： G11C16/02 , G06F3/06 , G06F12/00 , G06F12/02 , G11C16/10
CPC分类号： G06F3/0605 , G06F3/0616 , G06F3/0631 , G06F3/064 , G06F3/0647 , G06F3/0679 , G06F12/0246 , G06F12/1009 , G06F2212/1036 , G06F2212/214 , G06F2212/657 , G06F2212/7201 , G06F2212/7204 , G06F2212/7211 , G11C16/102
摘要： A flash memory system segregates overhead data from user data so that overhead data may be address, programmed and erased independently from user data. The non-volatile memory medium of a flash memory system is mapped into a plurality of separate and separately addressable memory blocks that are independently programmable and independently erasable, including Dedicated Overhead Blocks and Dedicated Data Blocks. The Dedicated Overhead Blocks are mapped according to a plurality of distinguishably addressable segments. User Data defined by a VLBA is stored in a Dedicated Data Block within the flash memory. Successively generated sets of Overhead Data, such as a cross reference to the physical address of the user data, flags, and Error Correction Data generated in conjunction with incoming User Data, are stored in respective segments in the Dedicated Overhead Blocks. When a Dedicated overhead Block is designated for erasure, any current overhead segments are consolidated and moved to a new Dedicated Overhead Block., and the full or obsolete block is erased.
摘要翻译：闪存系统将开销数据与用户数据隔离开，使得开销数据可以独立于用户数据进行地址，编程和擦除。闪速存储器系统的非易失性存储介质被映射到独立且可单独地寻址的存储器块，其独立地可编程并且可独立地可擦除，包括专用开销块和专用数据块。专用开销块根据多个可区分地寻址的段映射。由VLBA定义的用户数据存储在闪存中的专用数据块中。随后生成的开销数据集，如与用户数据的结合物理地址的交叉引用，标志和与输入用户数据一起生成的纠错数据，存储在专用开销块中的相应段中。当专用开销块被指定用于擦除时，任何当前开销段被合并并移动到新的专用开销块，并且完全或过时的块被擦除。

42. 发明申请

WO02019334A2 FLASH MEMORY ARCHITECTURE WITH SEPARATE STORAGE OF OVERHEAD AND USER DATA 审中-公开
标题翻译：具有独立存储和用户数据的闪存存储器架构
公开(公告)号：WO02019334A2
公开(公告)日：2002-03-07
申请号：PCT/US2001/026453
申请日：2001-08-24
IPC分类号： G11C16/02 , G06F3/06 , G06F12/00 , G06F12/02 , G11C16/10 , G11C7/00
CPC分类号： G06F3/0605 , G06F3/0616 , G06F3/0631 , G06F3/064 , G06F3/0647 , G06F3/0679 , G06F12/0246 , G06F12/1009 , G06F2212/1036 , G06F2212/214 , G06F2212/657 , G06F2212/7201 , G06F2212/7204 , G06F2212/7211 , G11C16/102
摘要： A flash memory system segregates overhead data from user data so that overhead data may be address, programmed and erased independently from user data. The non-volatile memory medium of a flash memory system is mapped into a plurality of separate and separately addressable memory blocks that are independently programmable and independently erasable, including Dedicated Overhead Blocks and Dedicated Data Blocks. The Dedicated Overhead Blocks are mapped according to a plurality of distinguishably addressable segments. User Data defined by a VLBA is stored in a Dedicated Data Block within the flash memory. Successively generated sets of Overhead Data, such as a cross reference to the physical address of the user data, flags, and Error Correction Data generated in conjunction with incoming User Data, are stored in respective segments in the Dedicated Overhead Blocks. When a Dedicated overhead Block is designated for erasure, any current overhead segments are consolidated and moved to a new Dedicated Overhead Block., and the full or obsolete block is erased.
摘要翻译：闪存系统将开销数据与用户数据隔离开，使得开销数据可以独立于用户数据进行地址，编程和擦除。闪速存储器系统的非易失性存储介质被映射到独立且可单独地寻址的存储器块，其独立地可编程并且可独立地可擦除，包括专用开销块和专用数据块。专用开销块根据多个可区分地寻址的段映射。由VLBA定义的用户数据存储在闪存中的专用数据块中。随后生成的开销数据集，如与用户数据的结合物理地址的交叉引用，标志和与输入用户数据一起生成的纠错数据，存储在专用开销块中的相应段中。当专用开销块被指定用于擦除时，任何当前开销段被合并并移动到新的专用开销块，并且完全或过时的块被擦除。

43. 发明申请

WO0201364A2 NON-VOLATILE CACHE INTEGRATED WITH MASS STORAGE DEVICE 审中-公开
标题翻译：非易失性高速缓存集成了大容量存储设备
公开(公告)号：WO0201364A2
公开(公告)日：2002-01-03
申请号：PCT/US0117845
申请日：2001-06-01
申请人： INTEL CORP , COULSON RICHARD
发明人： COULSON RICHARD
IPC分类号： G06F3/06 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0866 , G06F2212/214 , G06F2212/313
摘要： Apparatus and methods relating to a non-volatile mass storage device including a non-volatile cache.
摘要翻译：涉及包括非易失性高速缓存的非易失性大容量存储设备的设备和方法。

44. 发明申请

WO2016069188A8 PROCESSING OF UN-MAP COMMANDS TO ENHANCE PERFORMANCE AND ENDURANCE OF A STORAGE DEVICE 审中-公开
标题翻译：处理UN-MAP命令以提高存储设备的性能和耐久性
公开(公告)号：WO2016069188A8
公开(公告)日：2017-03-30
申请号：PCT/US2015053551
申请日：2015-10-01
申请人： SANDISK TECHNOLOGIES LLC
发明人： THANGARAJ SENTHIL M , REDDY DIVYA , PAULSAMY VENKATESH K , VASUDEVA SATISH BABU , SY JIMMY , CHANDRA RAKESH
IPC分类号： G06F12/02 , G06F11/14 , G06F12/08
CPC分类号： G06F12/0873 , G06F11/1441 , G06F11/1471 , G06F12/0246 , G06F12/0804 , G06F12/0871 , G06F2212/1016 , G06F2212/1021 , G06F2212/1036 , G06F2212/214 , G06F2212/312 , G06F2212/608 , G06F2212/7201 , G06F2212/7205 , G06F2212/7207 , G06F2212/7208
摘要： A storage device and method enable processing of un-map commands. In one aspect, the method includes (1) determining whether a size of an un-map command satisfies (e.g., is greater than or equal to) a size threshold, (2) if the size of the un-map command satisfies the size threshold, performing one or more operations of a first un-map process, wherein the first un-map process forgoes (does not include) saving a mapping table to non-volatile memory of a storage device, and (3) if the size of the un-map command does not satisfy the size threshold, performing one or more operations of a second un-map process, wherein the second un-map process forgoes (does not include) saving the mapping table to non- volatile memory of the storage device and forgoes (does not include) flushing a write cache to non¬ volatile memory of the storage device.
摘要翻译：存储设备和方法使得能够处理非映射命令。一方面，该方法包括：（1）确定un-map命令的大小是否满足（例如，大于或等于）大小阈值，（2）如果un-map命令的大小满足大小阈值，执行第一解映射处理的一个或多个操作，其中第一解映射处理放弃（不包括）将映射表保存到存储设备的非易失性存储器，以及（3）如果大小 un-map命令不满足大小阈值，执行第二解映射处理的一个或多个操作，其中第二解映射处理放弃（不包括）将映射表保存到存储器的非易失性存储器设备和放弃（不包括）将写缓存刷新到存储设备的非易失性存储器。

45. 发明申请

WO2016154088A1 MEMORY PARTITIONING STORAGE CONTROLLER 审中-公开
标题翻译：存储分区存储控制器
公开(公告)号：WO2016154088A1
公开(公告)日：2016-09-29
申请号：PCT/US2016/023359
申请日：2016-03-21
申请人： BURLYWOOD, LLC
发明人： EARHART, Tod R.
IPC分类号： G06F13/00
CPC分类号： G06F11/1068 , G06F3/0608 , G06F3/0613 , G06F3/0616 , G06F3/0619 , G06F3/0626 , G06F3/064 , G06F3/0644 , G06F3/0658 , G06F3/0659 , G06F3/0664 , G06F3/0679 , G06F3/068 , G06F11/1048 , G06F12/08 , G06F2212/1036 , G06F2212/1044 , G06F2212/151 , G06F2212/214 , G06F2212/261 , G06F2212/7208 , G11C29/52 , G11C2029/0411
摘要： A method of operating a storage controller is provided. The method includes receiving a request from a partition creator, for a first partition within a storage system, the first partition comprising one or more sequentially numbered data blocks, and receiving first partition parameters from the partition creator, the first partition parameters comprising a size of the one or more sequentially numbered data blocks. The method also includes creating the first partition within the storage system, through a storage interface, based on the first partition parameters, receiving first host data from a host, configuring the first host data as first storage data for storage within the first partition within the storage system, and sequentially storing the first storage data in the one or more sequentially numbered data blocks in the first partition, through the storage interface.
摘要翻译：提供了一种操作存储控制器的方法。该方法包括从分区创建器接收对存储系统内的第一分区的请求，第一分区包括一个或多个顺序编号的数据块，以及从分区创建器接收第一分区参数，第一分区参数包括一个或多个顺序编号的数据块。该方法还包括基于第一分区参数通过存储接口来创建存储系统内的第一分区，从主机接收第一主机数据，将第一主机数据配置为第一存储数据以存储在第一分区内存储系统，并且通过存储接口顺序地将第一存储数据存储在第一分区中的一个或多个顺序编号的数据块中。

46. 发明申请

WO2016099567A1 FLUSHING DATA CONTENT IN RESPONSE TO A POWER LOSS EVENT TO A PROCESSOR 审中-公开
标题翻译：对处理器的电力损失事件的响应中冲洗数据内容
公开(公告)号：WO2016099567A1
公开(公告)日：2016-06-23
申请号：PCT/US2014/071673
申请日：2014-12-19
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： ENGLER, David W. , KAPOOR, Mark Vinod , RAYMOND, Patrick A.
IPC分类号： G06F1/28 , G06F12/00
CPC分类号： G06F11/0793 , G06F1/28 , G06F1/30 , G06F11/073 , G06F12/00 , G06F12/0802 , G06F12/0868 , G06F2212/1032 , G06F2212/214 , G06F2212/311
摘要： In one example, a processor may include a processor core with a central processing unit as well as a processor cache separate from the processor core. The processor may also include flushing circuitry. The flushing circuitry may identify a power loss event for the processor. In response, the flushing circuitry may selectively power the processor by providing power to the processor cache but not to the processor core. The flushing circuitry may further flush data content of the processor cache to a non-volatile memory separate from the processor.
摘要翻译：在一个示例中，处理器可以包括具有中央处理单元的处理器核以及与处理器核分开的处理器高速缓存。处理器还可以包括冲洗电路。冲洗电路可以识别处理器的功率损耗事件。作为响应，冲洗电路可以通过向处理器高速缓存而不是处理器核提供电力来选择性地为处理器供电。冲洗电路还可以将处理器高速缓存的数据内容与处理器分离的非易失性存储器进行刷新。

47. 发明申请

WO2016028607A1 SYSTEMS AND METHODS FOR EXPANDING MEMORY FOR A SYSTEM ON CHIP 审中-公开
标题翻译：用于扩展芯片系统的存储器的系统和方法
公开(公告)号：WO2016028607A1
公开(公告)日：2016-02-25
申请号：PCT/US2015/045133
申请日：2015-08-13
申请人： QUALCOMM INCORPORATED
发明人： CHUN, Dexter Tamio , CHITTULURI, Suryanarayana China , LI, Yanru
IPC分类号： G06F13/16 , G06F12/06
CPC分类号： G06F3/0607 , G06F3/0631 , G06F3/0665 , G06F3/0683 , G06F12/0246 , G06F12/06 , G06F12/10 , G06F13/1684 , G06F2212/1048 , G06F2212/152 , G06F2212/171 , G06F2212/206 , G06F2212/214 , G06F2212/261 , G06F2212/654 , G06F2212/7201
摘要： Systems and methods are disclosed for expanding memory for a system on chip (SoC). A memory card is loaded in an expandable memory socket electrically and is coupled to a system on chip (SoC) via an expansion bus. The memory card comprises a first volatile memory device. In response to detecting the memory card, an expanded virtual memory map is configured. The expanded virtual memory map comprises a first virtual memory space associated the first volatile memory device and a second virtual memory space associated with a second volatile memory device electrically coupled to the SoC via a memory bus. One or more peripheral images associated with the second virtual memory space are relocated to a first portion of the first virtual memory space. A second portion of the first virtual memory space is configured as a block device for performing swap operations associated with the second virtual memory space.
摘要翻译：公开了用于扩展片上系统（SoC）的存储器的系统和方法。存储卡电气地装载在可扩展存储器插槽中，并通过扩展总线耦合到片上系统（SoC）。存储卡包括第一易失性存储器件。响应于检测到存储卡，配置扩展的虚拟存储器映射。扩展的虚拟存储器映射包括与第一易失性存储器设备相关联的第一虚拟存储器空间和与经由存储器总线电耦合到SoC的第二易失性存储器设备相关联的第二虚拟存储器空间。与第二虚拟存储器空间相关联的一个或多个周边图像被重新定位到第一虚拟存储器空间的第一部分。第一虚拟存储器空间的第二部分被配置为用于执行与第二虚拟存储器空间相关联的交换操作的块设备。

48. 发明申请

WO2016020886A1 MEMORY SYSTEM, HOST DEVICE AND INFORMATION PROCESSING SYSTEM 审中-公开
标题翻译：存储系统，主机设备和信息处理系统
公开(公告)号：WO2016020886A1
公开(公告)日：2016-02-11
申请号：PCT/IB2015/056002
申请日：2015-08-07
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： KANNO, Shinichi , NISHIMURA, Hiroshi , YOSHIDA, Hideki , MURAYAMA, Hiroshi
IPC分类号： G06F3/06 , G06F12/00 , G06F13/16
CPC分类号： G06F3/0604 , G06F1/3275 , G06F3/0619 , G06F3/0653 , G06F3/0655 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F11/1068 , G06F12/0246 , G06F2212/214 , G11C16/0483 , G11C16/24 , G11C29/52 , H03M13/2906 , Y02D10/14
摘要： According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.
摘要翻译：根据一个实施例，存储器系统包括非易失性存储器和控制非易失性存储器的控制器。控制器向外部通知指示非易失性存储器或控制器的预定状态的广泛信号。

49. 发明申请

WO2016006108A1 ストレージおよびその制御方法审中-公开
标题翻译：存储和控制方法
公开(公告)号：WO2016006108A1
公开(公告)日：2016-01-14
申请号：PCT/JP2014/068610
申请日：2014-07-11
申请人：株式会社日立製作所
发明人：保坂　文昭
IPC分类号： G06F3/06 , G06F12/08 , G06F12/16
CPC分类号： G06F11/1469 , G06F3/06 , G06F11/1435 , G06F12/08 , G06F12/0868 , G06F12/16 , G06F2201/84 , G06F2212/214 , G06F2212/225
摘要：　複数のクラスタを有するストレージは、前記クラスタごとにプロセッサとキャッシュメモリと退避メモリを有し、前記クラスタそれぞれのプロセッサは、前記キャッシュメモリに複数のデータを書き込むように制御し、障害発生時に前記キャッシュメモリに記憶しているすべてのデータを前記退避メモリへストアするように制御し、障害回復時に前記退避メモリへストアされたデータの一部を前記キャッシュメモリへリストアするように制御する。
摘要翻译：具有多个集群的存储器，其具有用于每个集群的处理器，高速缓存存储器和保存存储器。集群的每个处理器执行控制，使得多个数据被写入高速缓冲存储器，执行控制，使得当故障发生时保存在高速缓冲存储器中的所有数据都存储在保存存储器中，并执行控制存储在保存存储器中的数据的一部分在故障恢复期间被恢复在高速缓冲存储器中。

50. 发明申请

WO2015061337A1 FINAL LEVEL CACHE SYSTEM AND CORRESPONDING METHOD 审中-公开
标题翻译：最终级别缓存系统及其对应方法
公开(公告)号：WO2015061337A1
公开(公告)日：2015-04-30
申请号：PCT/US2014/061603
申请日：2014-10-21
申请人： SUTARDJA, Sehat
发明人： SUTARDJA, Sehat
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F3/061 , G06F3/0613 , G06F3/0638 , G06F3/0655 , G06F3/0656 , G06F3/0679 , G06F3/0683 , G06F9/4406 , G06F12/0804 , G06F12/0813 , G06F12/0862 , G06F12/0864 , G06F12/0868 , G06F12/0897 , G06F12/10 , G06F12/1027 , G06F2003/0691 , G06F2212/1016 , G06F2212/1021 , G06F2212/152 , G06F2212/154 , G06F2212/161 , G06F2212/171 , G06F2212/20 , G06F2212/202 , G06F2212/214 , G06F2212/22 , G06F2212/222 , G06F2212/251 , G06F2212/305 , G06F2212/50 , G06F2212/60 , G06F2212/6022 , G06F2212/6032 , G06F2212/608 , G06F2212/62 , G11C11/40607 , Y02D10/13
摘要： A data access system including a processor and a final level cache module. The processor is configured to generate a request to access a first physical address. The final level cache module includes a dynamic random access memory (DRAM), a final level cache controller, and a DRAM controller. The final level cache controller is configured to (i) receive the request from the processor, and (ii) convert the first physical address to a first virtual address. The DRAM controller is configured to (i) convert the first virtual address to a second physical address, and (ii) access the DRAM based on the second physical address.
摘要翻译：包括处理器和最终级缓存模块的数据访问系统。处理器被配置为生成访问第一物理地址的请求。最终级缓存模块包括动态随机存取存储器（DRAM），最终级高速缓存控制器和DRAM控制器。最终级缓存控制器被配置为（i）从处理器接收请求，以及（ii）将第一物理地址转换为第一虚拟地址。 DRAM控制器被配置为（i）将第一虚拟地址转换为第二物理地址，以及（ii）基于第二物理地址访问DRAM。

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