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1. 发明申请

WO2015061337A1 FINAL LEVEL CACHE SYSTEM AND CORRESPONDING METHOD 审中-公开
标题翻译：最终级别缓存系统及其对应方法
公开(公告)号：WO2015061337A1
公开(公告)日：2015-04-30
申请号：PCT/US2014/061603
申请日：2014-10-21
申请人： SUTARDJA, Sehat
发明人： SUTARDJA, Sehat
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F3/061 , G06F3/0613 , G06F3/0638 , G06F3/0655 , G06F3/0656 , G06F3/0679 , G06F3/0683 , G06F9/4406 , G06F12/0804 , G06F12/0813 , G06F12/0862 , G06F12/0864 , G06F12/0868 , G06F12/0897 , G06F12/10 , G06F12/1027 , G06F2003/0691 , G06F2212/1016 , G06F2212/1021 , G06F2212/152 , G06F2212/154 , G06F2212/161 , G06F2212/171 , G06F2212/20 , G06F2212/202 , G06F2212/214 , G06F2212/22 , G06F2212/222 , G06F2212/251 , G06F2212/305 , G06F2212/50 , G06F2212/60 , G06F2212/6022 , G06F2212/6032 , G06F2212/608 , G06F2212/62 , G11C11/40607 , Y02D10/13
摘要： A data access system including a processor and a final level cache module. The processor is configured to generate a request to access a first physical address. The final level cache module includes a dynamic random access memory (DRAM), a final level cache controller, and a DRAM controller. The final level cache controller is configured to (i) receive the request from the processor, and (ii) convert the first physical address to a first virtual address. The DRAM controller is configured to (i) convert the first virtual address to a second physical address, and (ii) access the DRAM based on the second physical address.
摘要翻译：包括处理器和最终级缓存模块的数据访问系统。处理器被配置为生成访问第一物理地址的请求。最终级缓存模块包括动态随机存取存储器（DRAM），最终级高速缓存控制器和DRAM控制器。最终级缓存控制器被配置为（i）从处理器接收请求，以及（ii）将第一物理地址转换为第一虚拟地址。 DRAM控制器被配置为（i）将第一虚拟地址转换为第二物理地址，以及（ii）基于第二物理地址访问DRAM。

2. 发明申请

WO2016209535A1 ACCELERATED ADDRESS INDIRECTION TABLE LOOKUP FOR WEAR-LEVELED NON-VOLATILE MEMORY 审中-公开
标题翻译：加速的地址间隔表用于磨损级别的非易失性存储器
公开(公告)号：WO2016209535A1
公开(公告)日：2016-12-29
申请号：PCT/US2016/034395
申请日：2016-05-26
申请人： INTEL CORPORATION
发明人： RAMANUJAN, Raj K. , ZHU, Jun , ARAFA, Mohamed , HAN, Woojong , HORWICH, Jordan A.
IPC分类号： G06F12/02 , G06F12/10 , G06F12/06 , G06F12/08
CPC分类号： G06F3/0649 , G06F3/0616 , G06F3/0685 , G06F12/0246 , G06F12/0866 , G06F12/1009 , G06F12/1027 , G06F2212/202 , G06F2212/214 , G06F2212/22 , G06F2212/7211
摘要： Embodiments are generally directed to accelerated address indirection table lookup for wear-leveled non-volatile memory. A embodiment of a memory device includes nonvolatile memory; a memory controller; and address indirection logic to provide address indirection for the nonvolatile memory, of the address indirection logic to maintain an address indirection table (AIT) in the nonvolatile memory, the AIT including a plurality of levels, and copy at least a portion of the AIT to a second memory, the second memory having less latency than the first memory.
摘要翻译：实施例通常涉及用于磨损级别的非易失性存储器的加速地址间接表查找。存储器件的实施例包括非易失性存储器; 内存控制器以及地址间接逻辑以提供所述非易失性存储器的地址间接，所述地址间接逻辑用于在所述非易失性存储器中维护地址间接表（AIT），所述AIT包括多个级别，并将所述AIT的至少一部分复制到第二存储器，第二存储器具有比第一存储器更少的延迟。

3. 发明申请

WO2015061014A1 SPLIT WRITE OPERATION FOR RESISTIVE MEMORY CACHE 审中-公开
标题翻译：电阻式存储器高速缓存的分离写操作
公开(公告)号：WO2015061014A1
公开(公告)日：2015-04-30
申请号：PCT/US2014/058668
申请日：2014-10-01
申请人： QUALCOMM INCORPORATED
发明人： DONG, Xiangyu , ZHU, Xiaochun , SUH, Jungwon
IPC分类号： G11C7/10 , G06F12/08 , G11C11/16
CPC分类号： G06F12/0802 , G06F12/08 , G06F12/0855 , G06F12/0864 , G06F2212/1016 , G06F2212/22 , G06F2212/222 , G06F2212/60 , G11C7/1015 , G11C7/1039 , G11C7/1084 , G11C11/165 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0002 , G11C2207/2245 , G11C2207/2272 , G11C2207/2281 , G11C2207/229
摘要： A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.
摘要翻译：一种读取和写入电阻式存储器高速缓存的方法包括接收写入命令并将写入命令分成多个写入子命令。该方法还包括在执行下一个写入子命令之前接收读取命令并执行读取命令。

4. 发明申请

WO2014158154A1 REGULATING MEMORY ACTIVATION RATES 审中-公开
标题翻译：调节记忆激活率
公开(公告)号：WO2014158154A1
公开(公告)日：2014-10-02
申请号：PCT/US2013/034243
申请日：2013-03-28
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： BENEDICT, Melvin, K. , WALKER, William, James , WALTON, Andrew, C.
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/123 , G06F12/0806 , G06F12/0888 , G06F12/0891 , G06F2212/1021 , G06F2212/1032 , G06F2212/22 , G06F2212/502 , G06F2212/604
摘要： A technique includes monitoring activation rates of a plurality of memory locations associated with a plurality of memory addresses and regulating the activation rates. The regulating includes selectively updating a cache with the memory addresses based on the activation rates.
摘要翻译：一种技术包括监视与多个存储器地址相关联的多个存储器位置的激活速率并调节激活速率。调节包括基于激活速率选择性地更新具有存储器地址的高速缓存。

5. 发明申请

WO2017171974A1 HANDLING OF ERROR PRONE CACHE LINE SLOTS OF MEMORY SIDE CACHE OF MULTI-LEVEL SYSTEM MEMORY 审中-公开
标题翻译：处理多级系统存储器的存储器侧缓存的错误PRONE缓存行时隙
公开(公告)号：WO2017171974A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/013442
申请日：2017-01-13
申请人： INTEL CORPORATION
发明人： YIGZAW, Theodros , RAJ, Ashok , SWANSON, Robert , KUMAR, Mohan J.
IPC分类号： G06F11/07 , G06F12/0802
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0811 , G06F2212/1021 , G06F2212/1032 , G06F2212/214 , G06F2212/22 , G06F2212/7201
摘要： An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.
摘要翻译：描述了一种包括存储器控制器逻辑电路以与多级系统存储器的存储器侧高速缓存接口的设备。存储器控制器逻辑电路包括错误跟踪电路以跟踪存储器侧高速缓存中的高速缓存线槽的错误。存储器控制器逻辑电路还包括故障列表电路，以存储被认为是过分容易出错的故障缓存线槽的标识符。存储器控制器逻辑电路将声明存储器侧高速缓存中的未命中，以寻找映射到故障列表中标识的高速缓存行槽的请求。

6. 发明申请

WO2015077951A1 TECHNIQUES FOR BLOCK-BASED INDEXING 审中-公开
标题翻译：基于块的索引技术
公开(公告)号：WO2015077951A1
公开(公告)日：2015-06-04
申请号：PCT/CN2013/088014
申请日：2013-11-28
申请人： INTEL CORPORATION , DENG, Gang , TANG, Xi , LU, Zhongyan , LOU, Ting , ZHANG, Tao , LIU, Heyuan
发明人： DENG, Gang , TANG, Xi , LU, Zhongyan , LOU, Ting , ZHANG, Tao , LIU, Heyuan
IPC分类号： G06F17/30
CPC分类号： G06F17/30324 , G06F12/0884 , G06F17/30138 , G06F17/30486 , G06F2212/22
摘要： Techniques for block-based indexing are described. In one embodiment, for example, an apparatus may comprise a multicore processor element, an assignment component for execution by the multicore processor element to generate a plurality of block-attribute pairs, each block- attribute pair corresponding to an attribute value and one of a plurality of data blocks, and an indexing component for execution by the multicore processor element to generate an index block for the plurality of data blocks based on the plurality of block-attribute pairs, the indexing component to perform parallel indexing of the plurality of block-attribute pairs using multiple indexing instances. Other embodiments are described and claimed.
摘要翻译：描述了基于块的索引的技术。在一个实施例中，例如，设备可以包括多核处理器元件，用于由多核处理器元件执行以产生多个块属性对的分配组件，每个块属性对对应于属性值，多个数据块，以及索引部件，用于由多核处理器元件执行以基于多个块属性对来生成多个数据块的索引块，索引部件执行多个块属性对的并行索引，使用多个索引实例的属性对。描述和要求保护其他实施例。

7. 发明申请

WO2012161807A1 UNIVERSAL CACHE MANAGEMENT SYSTEM 审中-公开
标题翻译：通用高速缓存管理系统
公开(公告)号：WO2012161807A1
公开(公告)日：2012-11-29
申请号：PCT/US2012/026639
申请日：2012-02-24
申请人： ORACLE INTERNATIONAL CORPORATION , BAGAL, Prasad, V. , LONG, Rich
发明人： BAGAL, Prasad, V. , LONG, Rich
IPC分类号： G06F12/08 , G06F17/30
CPC分类号： G06F12/0811 , G06F12/084 , G06F12/0897 , G06F17/3048 , G06F2212/22
摘要： Caches are allocated, in volatile memory of a computing device, to data-processing instances, where each one of the caches is exclusively allocated to a separate one of the data-processing instances. A common cache is allocated in the volatile memory of the computing device, where the common cache is shared by the data-processing instances. Each instance of the data-processing instances is configured to: indentify a data block in the particular cache allocated to that instance, where the data block has not been changed since the data block was last persistently written to one or more storage devices; cause the data block to be stored in the common cache; and remove the data block from the particular cache. Data blocks in the common cache are maintained without being persistently written to the one or more storage devices.
摘要翻译：高速缓存在计算设备的易失性存储器中被分配给数据处理实例，其中每个高速缓存独占地分配给数据处理实例中的单独一个。在计算设备的易失性存储器中分配公共高速缓存，其中公共高速缓存由数据处理实例共享。数据处理实例的每个实例被配置为：识别分配给该实例的特定高速缓存中的数据块，其中由于数据块最后一次持续写入一个或多个存储设备，数据块尚未更改; 使数据块存储在公共高速缓存中; 并从特定缓存中删除数据块。维持公用高速缓存中的数据块，而不会持续写入一个或多个存储设备。

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