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1. 发明申请

WO2009084286A1 MEMORY SYSTEM 审中-公开
标题翻译：记忆系统
公开(公告)号：WO2009084286A1
公开(公告)日：2009-07-09
申请号：PCT/JP2008/066508
申请日：2008-09-08
申请人： KABUSHIKI KAISHA TOSHIBA , KITSUNAI, Kazuya , KANNO, Shinichi , YANO, Hirokuni , HIDA, Toshikatsu , YANO, Junji
发明人： KITSUNAI, Kazuya , KANNO, Shinichi , YANO, Hirokuni , HIDA, Toshikatsu , YANO, Junji
IPC分类号： G06F12/16 , G06F12/00
CPC分类号： G06F3/0604 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0647 , G06F3/0652 , G06F3/0659 , G06F3/0679 , G06F3/0685 , G06F12/0246 , G06F2212/1036 , G06F2212/7202 , G06F2212/7205 , G06F2212/7211
摘要： A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
摘要翻译：存储器系统包括包括作为数据擦除单元的多个块的非易失性存储器，测量擦除每个块的数据的擦除时间的测量单元，以及写入从至少外部提供的数据到第一块设置为空闲状态，擦除时间最长。

2. 发明申请

WO2009147753A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2009147753A1
公开(公告)日：2009-12-10
申请号：PCT/JP2008/067602
申请日：2008-09-22
申请人： Kabushiki Kaisha Toshiba , ASANO, Shigehiro , KANNO, Shinichi , YANO, Junji
发明人： ASANO, Shigehiro , KANNO, Shinichi , YANO, Junji
IPC分类号： H01L25/065 , H01L21/822 , H01L25/07 , H01L25/18 , H01L27/04
CPC分类号： H01L23/5228 , G06F9/4401 , G11C5/005 , G11C5/04 , G11C5/066 , G11C16/0408 , H01L23/60 , H01L24/48 , H01L25/0657 , H01L2224/05554 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2924/00014 , H01L2924/01046 , H01L2924/01055 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： On a single semiconductor package PK1, m semiconductor chips CP1 to CPm are mounted, and the semiconductor package PK1 has external terminals T shared by m pad electrodes PD1 to PDm of the m semiconductor chips CP1 to CPm. An electrostatic protection circuit CD is mounted on only one CPm of the m semiconductor chips CP1 to CPm.
摘要翻译：在单个半导体封装PK1上安装半导体芯片CP1至CPm，并且半导体封装PK1具有由m个半导体芯片CP1至CPm的m个焊盘电极PD1至PDm共享的外部端子T. 静电保护电路CD仅安装在m个半导体芯片CP1至CPm的一个CPm上。

3. 发明申请

WO2013014974A1 MEMORY CONTROLLER, SEMICONDUCTOR STORAGE DEVICE, AND DECODING METHOD 审中-公开
标题翻译：存储器控制器，半导体存储器件和解码方法
公开(公告)号：WO2013014974A1
公开(公告)日：2013-01-31
申请号：PCT/JP2012/057246
申请日：2012-03-14
申请人： Kabushiki Kaisha Toshiba , HORISAKI, Koji , HIDA, Toshikatsu , KANNO, Shinichi , TORII, Osamu
发明人： HORISAKI, Koji , HIDA, Toshikatsu , KANNO, Shinichi , TORII, Osamu
IPC分类号： G06F12/16 , G11C29/42
CPC分类号： G06F11/1044 , G06F11/1048 , H03M13/1575
摘要： According to an embodiment, a memory interface that includes n number of channels and writes data subjected to an error correction encoding process having capable of correcting t symbols, n number of first error correction decoding units that perform an error correction decoding process of correcting s (s
摘要翻译：根据一个实施例，一种存储器接口，其包括n个通道并且写入经过能够校正t个符号的纠错编码处理的数据，n个第一纠错解码单元，其执行校正s（ s

4. 发明申请

WO2009107268A1 SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：半导体存储设备
公开(公告)号：WO2009107268A1
公开(公告)日：2009-09-03
申请号：PCT/JP2008/067597
申请日：2008-09-22
申请人： Kabushiki Kaisha Toshiba , HIDA, Toshikatsu , KANNO, Shinichi , YANO, Hirokuni , KITSUNAI, Kazuya , ASANO, Shigehiro , YANO, Junji
发明人： HIDA, Toshikatsu , KANNO, Shinichi , YANO, Hirokuni , KITSUNAI, Kazuya , ASANO, Shigehiro , YANO, Junji
IPC分类号： G06F12/16 , G06F12/00 , G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G06F11/1412 , G06F11/1068 , G06F11/1402 , G06F12/02 , G11C16/0483 , G11C16/3418 , G11C16/3431
摘要： As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.
摘要翻译：作为可以有效地执行刷新操作的半导体存储装置，提供了一种半导体存储装置，其包括以块为单位存储数据的非易失性半导体存储器，该块是数据擦除单元，以及监视数据的错误计数的控制单元存储在从所述块中选择的监视块和所述监视块中的刷新数据中，其中所述错误计数等于或大于阈值。

5. 发明申请

WO2009041153A1 SEMICONDUCTOR MEMORY DEVICE AND ITS CONTROL METHOD 审中-公开
标题翻译：半导体存储器件及其控制方法
公开(公告)号：WO2009041153A1
公开(公告)日：2009-04-02
申请号：PCT/JP2008/063345
申请日：2008-07-17
申请人： KABUSHIKI KAISHA TOSHIBA , KANNO, Shinichi
发明人： KANNO, Shinichi
IPC分类号： G06F11/10
CPC分类号： G06F11/1068
摘要： A semiconductor memory device includes a temporary storage circuit configured to receive data items and store the data items in rows and columns, a detecting code generator configured to generate first detecting codes used to detect errors in the data items, respectively, a first correcting code generator configured to generate first correcting codes used to correct errors in first data blocks corresponding to the columns, respectively, each of the first data blocks containing data items that are arranged in a corresponding one of the columns, and a second correcting code generator configured to generate second correcting codes used to correct errors in second data blocks corresponding to the rows, respectively, each of the second data blocks containing data items that are arranged in a corresponding one of the rows.
摘要翻译：一种半导体存储器件，包括临时存储电路，被配置为接收数据项并将数据项存储在行和列中;检测码发生器，被配置为分别生成用于检测数据项中的错误的第一检测码;第一校正码发生器被配置为分别产生用于校正与所述列相对应的第一数据块中的错误的第一校正码，每个第一数据块包含布置在对应的一列中的数据项，以及第二校正码生成器，被配置为生成用于分别对应于行的第二数据块中的错误的第二校正码，每个第二数据块包含布置在相应行中的数据项。

6. 发明申请

WO2009028281A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 审中-公开
标题翻译：半导体存储器件及其控制方法
公开(公告)号：WO2009028281A1
公开(公告)日：2009-03-05
申请号：PCT/JP2008/063344
申请日：2008-07-17
申请人： KABUSHIKI KAISHA TOSHIBA , KANNO, Shinichi , UCHIKAWA, Hironori
发明人： KANNO, Shinichi , UCHIKAWA, Hironori
IPC分类号： G06F11/10
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
摘要翻译：半导体存储器件包括多个检测码发生器，其被配置为分别产生多个检测码以分别检测多个数据项中的错误;多个第一校正码发生器，被配置为产生多个第一校正码以校正错误在多个第一数据块中，分别包含数据项之一和相应检测码的第一数据块，被配置为生成用于校正第二数据块中的错误的第二校正码的第二校正码发生器，包含第一数据块的第二数据块，以及被配置为非易失性地存储第二数据块，第一校正码和第二校正码的半导体存储器。

7. 发明申请

WO2016020886A1 MEMORY SYSTEM, HOST DEVICE AND INFORMATION PROCESSING SYSTEM 审中-公开
标题翻译：存储系统，主机设备和信息处理系统
公开(公告)号：WO2016020886A1
公开(公告)日：2016-02-11
申请号：PCT/IB2015/056002
申请日：2015-08-07
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： KANNO, Shinichi , NISHIMURA, Hiroshi , YOSHIDA, Hideki , MURAYAMA, Hiroshi
IPC分类号： G06F3/06 , G06F12/00 , G06F13/16
CPC分类号： G06F3/0604 , G06F1/3275 , G06F3/0619 , G06F3/0653 , G06F3/0655 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F11/1068 , G06F12/0246 , G06F2212/214 , G11C16/0483 , G11C16/24 , G11C29/52 , H03M13/2906 , Y02D10/14
摘要： According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.
摘要翻译：根据一个实施例，存储器系统包括非易失性存储器和控制非易失性存储器的控制器。控制器向外部通知指示非易失性存储器或控制器的预定状态的广泛信号。

8. 发明申请

WO2009130809A1 MEMORY SYSTEM 审中-公开
标题翻译：记忆系统
公开(公告)号：WO2009130809A1
公开(公告)日：2009-10-29
申请号：PCT/JP2008/066507
申请日：2008-09-08
申请人： KABUSHIKI KAISHA TOSHIBA , KANNO, Shinichi , YANO, Hirokuni , HIDA, Toshikatsu , KITSUNAI, Kazuya , YANO, Junji
发明人： KANNO, Shinichi , YANO, Hirokuni , HIDA, Toshikatsu , KITSUNAI, Kazuya , YANO, Junji
IPC分类号： G06F12/16
CPC分类号： G11C16/349 , G06F11/1068 , G06F12/0246 , G06F2212/7211 , G11C16/16 , G11C29/76
摘要： A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data in each block is erased, a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block, a detector which detects blocks in which rewrite has collectively occurred within a short period, a first selector which selects a free block having an old erase time as a first block, on the basis of an information in the block table, a second selector which selects a block in use having an old erase time as a second block, on the basis of the information in the block table, and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector.
摘要翻译：存储器系统包括：包括作为数据擦除单元的多个块的非易失性存储器;测量单元，其测量擦除每个块中的数据的擦除时间;块控制器，具有块表，其将指示自由状态和每个块的擦除时间的使用状态，检测在短时间内共同发生重写的块的检测器，选择具有旧擦除时间的空闲块作为第一块的第一选择器，基于块表中的信息，第二选择器，其基于块表中的信息选择具有旧擦除时间的块的块;以及调度单元，其在第二块中移动数据如果第一块被包括在由检测器检测到的块中，则到第一块。

9. 发明申请

WO2009107506A1 MEMORY SYSTEM 审中-公开
标题翻译：记忆系统
公开(公告)号：WO2009107506A1
公开(公告)日：2009-09-03
申请号：PCT/JP2009/052590
申请日：2009-02-10
申请人： Kabushiki Kaisha Toshiba , YANO, Junji , MATSUZAKI, Hidenori , HATSUDA, Kosuke , ASANO, Shigehiro , KANNO, Shinichi , HIDA, Toshikatsu
发明人： YANO, Junji , MATSUZAKI, Hidenori , HATSUDA, Kosuke , ASANO, Shigehiro , KANNO, Shinichi , HIDA, Toshikatsu
IPC分类号： G06F12/16 , G11C16/02
CPC分类号： G06F11/1451 , G06F11/1471 , G06F12/0246 , G06F12/06 , G06F2212/7207 , G11C7/20 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/105
摘要： A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer. The first pointer is stored in a fixed area in the second storing unit and the second pointer is stored in an area excluding the fixed area in the second storing unit.
摘要翻译：存储系统包括易失性第一存储单元，非易失性第二存储单元和控制器。控制器执行数据传送，将存储在第二存储单元中的数据的存储位置的管理信息存储到第一存储单元中，并且在更新管理信息的同时执行数据管理。第二存储单元具有用于存储管理信息存储信息的管理信息存储区域，该管理信息存储信息包括最新状态的管理信息和管理信息的存储位置。存储位置信息在存储器系统的启动操作期间由控制器读取，并且包括指示管理信息存储区域中处于最新状态的管理信息的存储位置的第二指针和指示第二存储器的存储位置的第一指针指针。第一指针存储在第二存储单元中的固定区域中，并且第二指针存储在除了第二存储单元中的固定区域之外的区域中。

10. 发明申请

WO2009084724A1 SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：半导体存储设备
公开(公告)号：WO2009084724A1
公开(公告)日：2009-07-09
申请号：PCT/JP2008/073950
申请日：2008-12-25
申请人： KABUSHIKI KAISHA TOSHIBA , YANO, Hirokuni , KANNO, Shinichi , HIDA, Toshikatsu , MATSUZAKI, Hidenori , KITSUNAI, Kazuya , ASANO, Shigehiro
发明人： YANO, Hirokuni , KANNO, Shinichi , HIDA, Toshikatsu , MATSUZAKI, Hidenori , KITSUNAI, Kazuya , ASANO, Shigehiro
IPC分类号： G06F12/00 , G06F3/06 , G06F3/08 , G06F12/02 , G06F12/04 , G06F12/08 , G11C16/02
CPC分类号： G06F3/0604 , G06F3/0616 , G06F3/0631 , G06F3/064 , G06F3/0656 , G06F3/0658 , G06F3/0679 , G06F3/0685 , G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F2212/7201 , G06F2212/7202 , G06F2212/7203 , G06F2212/7209 , G11C11/5628
摘要： A semiconductor storage device includes a first memory area 11 configured in a volatile semiconductor memory, second and third memory areas 12 and 13 configured in a nonvolatile semiconductor memory, and a controller 10 which executes following processing. The controller 10 executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
摘要翻译：半导体存储装置包括配置在易失性半导体存储器中的第一存储区域11，配置在非易失性半导体存储器中的第二和第三存储器区域12和13，以及执行以下处理的控制器10。控制器10执行用于在第一存储区域中由第一单元存储多个数据的第一处理，用于存储由第二存储区域中的第一管理单元从第一存储区域输出的数据的第二处理，以及第三处理用于通过第三存储区域中的第二管理单元存储从第一存储区域输出的数据。

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