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1. 发明申请

WO1993026047A1 SILICON CARBIDE POWER MOSFET WITH FLOATING FIELD RING AND FLOATING FIELD PLATE 审中-公开
标题翻译：具有浮动场环和浮动场板的硅碳粉功率MOSFET
公开(公告)号：WO1993026047A1
公开(公告)日：1993-12-23
申请号：PCT/US1993005381
申请日：1993-06-07
申请人： NORTH CAROLINA STATE UNIVERSITY , BALIGA, Bantval, Jayant
发明人： NORTH CAROLINA STATE UNIVERSITY
IPC分类号： H01L29/24
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0649 , H01L29/1608 , H01L29/404 , H01L29/407 , H01L29/66068 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A silicon carbide power MOSFET device includes a first silicon carbide layer, epitaxially formed on the silicon carbide substrate of opposite conductivity type. A second silicon carbide layer of the same conductivity type as the substrate is formed on the first silicon carbide layer. A power field effect transistor is formed in the device region of the substrate and in the first and second silicon carbide layers thereover. At least one termination trench is formed in the termination region of the silicon carbide substrate, extending through the first and second silicon carbide layers thereover. The termination trench defines one or more isolated mesas in the termination region which act as floating field rings. The termination trenches are preferably insulator lined and filled with conductive material to form floating field plates. The outermost trench may be a deep trench which extends through the first and second silicon carbide layers and through the drift region of the silicon carbide substrate. Since the termination region is formed from the first and second silicon carbide layers in the termination region, a time consuming, high temperature diffusion to form a floating field ring is not necessary. Rather, the same epitaxial first and second silicon carbide layers which are used to form an FET in the device region may also be used to form the floating field ring in the termination region.

2. 发明申请

WO1996015557A1 SILICON CARBIDE SEMICONDUCTOR DEVICES HAVING BURIED SILICON CARBIDE CONDUCTION BARRIER LAYERS THEREIN AND METHODS OF FORMING SAME 审中-公开
标题翻译：带有碳化硅碳化硅导体阻挡层的硅碳化硅半导体器件及其形成方法
公开(公告)号：WO1996015557A1
公开(公告)日：1996-05-23
申请号：PCT/US1995014580
申请日：1995-11-09
申请人： NORTH CAROLINA STATE UNIVERSITY , BALIGA, Bantval, Jayant
发明人： NORTH CAROLINA STATE UNIVERSITY
IPC分类号： H01L29/24
CPC分类号： H01L29/7806 , H01L21/0445 , H01L29/0649 , H01L29/1079 , H01L29/1608 , H01L29/66068 , H01L29/7802 , H01L29/812 , H01L29/8122 , Y10S438/931
摘要： A silicon carbide semiconductor device includes a silicon carbide substrate (12), an active layer (15) in the substrate and a silicon carbide buried (18) layer which provides a conduction barrier between the substrate and at least a portion of the active layer. The buried layer (18) is preferably formed by implanting second conductivity type dopants into the substrate so that a P-N junction barrier is provided between the active layer (15) and the substrate (12). The buried layer (18) may also be formed by implanting electrically inactive ions into the substrate so that a relatively high resistance barrier is provided between the active layer (15) and the substrate (12). The electrically inactive ions are preferably selected from the group consisting of argon, neon, carbon and silicon, although other ions which are electrically inactive in silicon carbide may be used. The implantation of the electrically inactive ions is designed to cause the formation of a large number of electrically active deep level defects in the buried layer, particularly near the peak of the implant profile which is Gaussian in shape. These steps can be utilized in the formation of a variety of silicon carbide semiconductor devices such as lateral field effect devices and devices having both vertical and lateral active regions which are designed for high power applications. In particular, lateral silicon carbide-on-insulator enhancement and depletion mode field effect transistors (FETs) can be formed in accordance with the present invention. Vertical silicon carbide power MESFET devices can also be formed by incorporating a silicon carbide source region in the active layer at the first face of a silicon carbide substrate and a drain region at the second face and by providing a Schottky barrier gate electrode on the first face.
摘要翻译：碳化硅半导体器件包括碳化硅衬底（12），衬底中的有源层（15）和在衬底和有源层的至少一部分之间提供导电阻挡层的碳化硅掩埋（18）层。掩埋层（18）优选通过将第二导电类型的掺杂剂注入衬底中形成，使得在有源层（15）和衬底（12）之间提供P-N结屏障。掩埋层（18）也可以通过将非活性离子注入衬底而形成，使得在有源层（15）和衬底（12）之间提供相对较高的电阻屏障。电惰性离子优选选自氩，氖，碳和硅，尽管可以使用在碳化硅中电惰性的其它离子。电惰性离子的注入被设计成在掩埋层中形成大量的电活性深层缺陷，特别是在高斯形状的植入物轮廓的峰附近。这些步骤可以用于形成各种碳化硅半导体器件，例如横向场效应器件和具有设计用于高功率应用的垂直和横向有源区的器件。特别地，根据本发明可以形成横向碳化硅 - 绝缘体上的增强和耗尽型场效应晶体管（FET）。垂直碳化硅功率MESFET器件还可以通过在碳化硅衬底的第一面和第二面上的漏极区域的有源层中并入碳化硅源区域并且在第一面上设置肖特基势垒栅电极来形成。

3. 发明申请

WO2002084745A2 POWER SEMICONDUCTOR DEVICES HAVING LATERALLY EXTENDING BASE SHIELDING REGIONS THAT INHIBIT BASE REACH THROUGH AND METHODS OF FORMING SAME 审中-公开
标题翻译：具有通过其抑制基础接近的侧向延伸基板屏蔽区域的功率半导体器件及其形成方法
公开(公告)号：WO2002084745A2
公开(公告)日：2002-10-24
申请号：PCT/US2002/012775
申请日：2002-04-05
申请人： SILICON WIRELESS CORPORATION , BALIGA, Bantval, Jayant
发明人： BALIGA, Bantval, Jayant
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/66727 , H01L29/7806 , H01L29/872
摘要： A power MOSFET (10) includes a semiconductor substrate having a drift region therein (102) and a transition region (130) that extends between the drift region and a first surface (102a) of the semiconductor substrate. The transition region (130) has a vertically retrograded doping profile therein that peaks at a first depth relative to the first surface (102a). First and second base shielding regions (128) are moreover provided under respective first and second base regions (126) to deplete the transition region (130).
摘要翻译：功率MOSFET（10）包括其中具有漂移区（102）的半导体衬底和在所述漂移区和所述半导体衬底的第一表面（102a）之间延伸的过渡区（130）。过渡区域（130）在其中具有垂直退化的掺杂分布，其中相对于第一表面（102a）在第一深度处达到峰值。此外，在相应的第一和第二基区（126）下设置第一和第二基底屏蔽区域（128）以消耗过渡区域（130）。

4. 发明申请

WO0025365A3 POWER SEMICONDUCTOR DEVICES HAVING IMPROVED HIGH FREQUENCY SWITCHING AND BREAKDOWN CHARACTERISTICS 审中-公开
标题翻译：具有改进的高频切换和断开特性的功率半导体器件
公开(公告)号：WO0025365A3
公开(公告)日：2001-09-07
申请号：PCT/US9924539
申请日：1999-10-20
申请人： UNIV NORTH CAROLINA STATE , BALIGA BANTVAL JAYANT
发明人： BALIGA BANTVAL JAYANT
IPC分类号： H01L21/8234 , H01L27/04 , H01L27/088 , H01L27/095 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/088 , H01L27/095 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/42368 , H01L29/7806 , H01L29/7808 , H01L29/7811 , H01L29/8725 , H01L2924/0002 , H01L2924/00
摘要： Integrated power semiconductor devices having improved high frequency switching performance, improved edge termination characteristics and reduced on-state resistance include GD-UMOSFET unit cells with upper trench-based gate electrodes and lower-trench based source electrodes. The use of the trench-based source electrode instead of a larger gate electrode reduces the gate-to-drain capacitance (CGD) of the UMOSFET and improves switching speed by reducing the amount of gate charging and discharging current that is needed during high frequency operation.
摘要翻译：具有改进的高频切换性能，改进的边缘终止特性和降低的导通状态电阻的集成功率半导体器件包括具有上沟槽基栅极电极和下沟槽基源电极的GD-UMOSFET单元电池。使用基于沟槽的源电极代替较大的栅电极减小了UMOSFET的栅 - 漏电容（CGD），并且通过减少在高频操作期间所需的栅极充电和放电电流的量来提高开关速度。

5. 发明申请

WO0241402A3 DISCRETE AND PACKAGED POWER DEVICES FOR RADIO FREQUENCY (RF) APPLICATIONS AND METHODS OF FORMING SAME 审中-公开
标题翻译：用于无线电频率（RF）应用的分离和封装功率器件及其形成方法
公开(公告)号：WO0241402A3
公开(公告)日：2004-02-26
申请号：PCT/US0144168
申请日：2001-11-05
申请人： SILICON WIRELESS CORP , BALIGA BANTVAL JAYANT
发明人： BALIGA BANTVAL JAYANT
IPC分类号： H01L21/336 , H01L23/552 , H01L23/60 , H01L23/66 , H01L27/088 , H01L29/06 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/78 , H01L23/047 , H01L23/492 , H01L27/06 , H01L29/41
CPC分类号： H01L23/66 , H01L23/552 , H01L23/60 , H01L24/37 , H01L24/40 , H01L24/41 , H01L27/088 , H01L29/0696 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/4238 , H01L29/66712 , H01L29/7802 , H01L29/7803 , H01L29/7813 , H01L2223/6627 , H01L2224/371 , H01L2224/40095 , H01L2224/40245 , H01L2224/83801 , H01L2924/10253 , H01L2924/1305 , H01L2924/1306 , H01L2924/13063 , H01L2924/13091 , H01L2924/14 , H01L2924/15787 , H01L2924/1903 , H01L2924/3011 , H01L2924/00 , H01L2924/00014
摘要： Integrated power devices include a plurality of field effect transistor unit cells and a Faraday shield layer that reduces parasitic gate-to-drain capacitance (Cgd) and concomitantly improves high frequency switching performance. These power devices may include a field effect transistor in an active portion of a semiconductor substrate and a gate electrode that is electrically connected to a gate of the field effect transistor. A Faraday shield layer is provided between at least a first portion of the gate electrode and a drain of the field effect transistor in order to capacitively decouple the first portion of the gate electrode from the drain. The gate electrode and drain typically extend adjacent opposing faces of the semiconductor substrate. The Faraday shield layer is preferably electrically connected to a source of the field effect transistor and provides edge termination.
摘要翻译：集成的功率器件包括多个场效应晶体管单元单元和减小寄生栅 - 漏电容（Cgd）的法拉第屏蔽层，并且伴随地提高了高频开关性能。这些功率器件可以包括在半导体衬底的有源部分中的场效应晶体管和电连接到场效应晶体管的栅极的栅电极。在栅电极的至少第一部分和场效应晶体管的漏极之间设置法拉第屏蔽层，以便电容性地将栅电极的第一部分与漏极分离。栅电极和漏极通常延伸相邻的半导体衬底的相对面。法拉第屏蔽层优选地电连接到场效应晶体管的源极并且提供边缘终止。

6. 发明申请

WO02084745A3 POWER SEMICONDUCTOR DEVICES AND METHODS OF FORMING SAME 审中-公开
标题翻译：功率半导体器件及其形成方法
公开(公告)号：WO02084745A3
公开(公告)日：2003-08-21
申请号：PCT/US0212775
申请日：2002-04-05
申请人： SILICON WIRELESS CORP , BALIGA BANTVAL JAYANT
发明人： BALIGA BANTVAL JAYANT
IPC分类号： H01L21/76 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/78 , H01L29/872 , H01L21/336 , H01L29/36
CPC分类号： H01L29/0878 , H01L29/0847 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/66727 , H01L29/7802 , H01L29/7806 , H01L29/872
摘要： A power MOSFET (10) includes a semiconductor substrate having a drift region therein (102) and a transition region (130) that extends between the drift region and a first surface (102a) of the semiconductor substrate. The transition region (130) has a vertically retrograded doping profile therein that peaks at a first depth relative to the first surface (102a). First and second base shielding regions (128) are moreover provided under respective first and second base regions (126) to deplete the transition region (130).
摘要翻译：功率MOSFET（10）包括其中具有漂移区（102）的半导体衬底和在所述漂移区和所述半导体衬底的第一表面（102a）之间延伸的过渡区（130）。过渡区域（130）在其中具有垂直退化的掺杂分布，其中相对于第一表面（102a）在第一深度处达到峰值。此外，在相应的第一和第二基区（126）下设置第一和第二基底屏蔽区域（128）以消耗过渡区域（130）。

7. 发明申请

WO0201644A3 POWER MOSFET AND METHODS OF FORMING AND OPERATING THE SAME 审中-公开
标题翻译：功率MOSFET及其形成和操作的方法
公开(公告)号：WO0201644A3
公开(公告)日：2002-07-04
申请号：PCT/US0118072
申请日：2001-06-05
申请人： SILICON WIRELESS CORP , GIANT SEMICONDUCTOR CORP , BALIGA BANTVAL JAYANT
发明人： BALIGA BANTVAL JAYANT
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/772 , H01L29/78 , H01L21/336 , H01L29/36
CPC分类号： H01L29/7816 , H01L21/823487 , H01L27/088 , H01L29/063 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/42368 , H01L29/7722 , H01L29/7802 , H01L29/7813 , H01L29/7832
摘要： In power MOSFET embodiments of the present invention which provide highly linear transfer characteristics and can be used effectively in linear power amplifiers a relatively highly doped transition region (117) is preferably provided between the channel region (116) and the drift region (112). Upon depletion, this transition region provides a potential barrier that supports separate and simultaneous linear and current saturation modes.
摘要翻译：在本发明的功率MOSFET实施例中，提供高度线性的传输特性并且可以有效地用于线性功率放大器中，优选地，在沟道区（116）和漂移区（112）之间提供相对高掺杂的过渡区（117）。在耗尽时，该过渡区域提供支持分离和同时线性和电流饱和模式的势垒。

8. 发明申请

WO1995009439A1 SILICON CARBIDE FIELD EFFECT DEVICE 审中-公开
标题翻译：碳化硅场效应器件
公开(公告)号：WO1995009439A1
公开(公告)日：1995-04-06
申请号：PCT/US1994009826
申请日：1994-08-31
申请人： NORTH CAROLINA STATE UNIVERSITY , BALIGA, Bantval, Jayant
发明人： NORTH CAROLINA STATE UNIVERSITY
IPC分类号： H01L29/772
CPC分类号： H01L29/1608 , H01L29/0865 , H01L29/41775 , H01L29/7828
摘要： A silicon carbide field effect device includes vertically stacked silicon carbide regions of first conductivity type, extending from a lowermost drain region to an uppermost source region. In between the drain and source regions, a drift region and a channel region are provided. The drift region extends adjacent the drain region and the channel region extends between the drift region and the source region. Control of majority carrier conduction between the source and drain regions is provided by a plurality of trenches, which extend through the source and channel region, and conductive gate electrodes therein. To provide high blocking voltage capability and low on-state resistance, the doping concentration in the drift region is selected to be greater than the doping concentration of the channel region but below the doping concentration of the drain and source regions. Preferably, the material used for the gate electrodes, the spacing between adjacent trenches and the doping concentration of the channel region are chosen so that the channel region is depleted of majority charge carriers when zero potential bias is applied to the gate electrodes.
摘要翻译：碳化硅场效应器件包括从最下面的漏极区域延伸到最上面的源极区域的垂直堆叠的第一导电类型的碳化硅区域。在漏极和源极区域之间，提供漂移区域和沟道区域。漂移区域相邻于漏极区域延伸，并且沟道区域在漂移区域和源极区域之间延伸。源极和漏极区域之间的多数载流子传导的控制由延伸穿过源极和沟道区域的多个沟槽以及其中的导电栅极电极提供。为了提供高阻挡电压能力和低导通电阻，漂移区中的掺杂浓度选择为大于沟道区的掺杂浓度，但低于漏极和源极区的掺杂浓度。优选地，选择用于栅极电极的材料，相邻沟槽之间的间隔和沟道区域的掺杂浓度，使得当将零电位偏压施加到栅电极时，沟道区域耗尽多数电荷载流子。

9. 发明申请

WO0070684A3 SILICON CARBIDE POWER DEVICES COMPRISING CHARGE COUPLING REGIONS 审中-公开
标题翻译：包含充电耦合区域的碳化硅电力装置
公开(公告)号：WO0070684A3
公开(公告)日：2001-06-14
申请号：PCT/US0013455
申请日：2000-05-16
申请人： UNIV NORTH CAROLINA STATE , BALIGA BANTVAL JAYANT
发明人： BALIGA BANTVAL JAYANT
IPC分类号： H01L29/06 , H01L29/24 , H01L29/40 , H01L29/78 , H01L29/808 , H01L29/872
CPC分类号： H01L29/408 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/1608 , H01L29/7813 , H01L29/8083 , H01L29/872
摘要： Silicon carbide power devices (10, 10', 30) having trench-based charge coupling regions include a silicon carbide substrate having a silicon carbide drift region (12) of first conductivity type (e.g., N-type) and a trench (T1, T2) therein at a first face (11a) thereof. A uniformly doped silicon carbide charge coupling region (14a, 14b) of second conductivity type is also provided in the trench. This charge coupling region forms a P-N rectifying junction with the drift region that extends along a sidewall of the trench. The drift region and charge coupling region are both uniformly doped at equivalent and relatively high net majority carrier doping concentrations. Siilicon carbide switching devices that use the present charge coupling regions include Schottky barrier rectifiers (SBRs) (10, 10'), junction field effect transistors (JFETs) (30) and metal-oxide-semiconductor field effect transistors (MOSFETs) (30). Alternatively, the charge coupling regions may be replaced by semi-insulting regions.
摘要翻译：具有基于沟槽的电荷耦合区域的碳化硅功率器件（10,10'，30）包括具有第一导电类型（例如，N型）的碳化硅漂移区（12）和沟槽（T1， T2）的第一面（11a）。在沟槽中还提供了第二导电类型的均匀掺杂的碳化硅电荷耦合区域（14a，14b）。该电荷耦合区域与沿着沟槽的侧壁延伸的漂移区域形成P-N整流结。漂移区域和电荷耦合区域都以相等和相对较高的净多数载流子掺杂浓度均匀掺杂。使用本电荷耦合区的硅碳化物开关器件包括肖特基势垒整流器（SBR）（10,10'），结场效应晶体管（JFET）（30）和金属氧化物半导体场效应晶体管（MOSFET）30。。或者，电荷耦合区域可以由半绝缘区域代替。

10. 发明申请

WO1997043789A1 SCHOTTKY BARRIER RECTIFIERS AND METHODS OF FORMING SAME 审中-公开
标题翻译：肖特基障碍整流器及其形成方法
公开(公告)号：WO1997043789A1
公开(公告)日：1997-11-20
申请号：PCT/US1997007866
申请日：1997-05-09
申请人： NORTH CAROLINA STATE UNIVERSITY , BALIGA, Bantval, Jayant
发明人： NORTH CAROLINA STATE UNIVERSITY
IPC分类号： H01L29/872
CPC分类号： H01L29/8725 , H01L29/872
摘要： A Schottky rectifier (10) includes MOS-filled trenches and an anode electrode at a face of a semiconductor substrate and an optimally nonuniformly doped drift (12d) region therein which in combination provide high blocking voltage capability with low reverse-biased leakage current and low forward voltage drop. The nonuniformly doped drift (12d) region contains a concentration of first conductivity type dopants therein which increases monotonically in a direction away from a Schottky rectifying function formed between the anode electrode (18) and the drift region (12d). A profile of the doping concentration in the drift region is preferably a linear or step graded profile with a concentration of less than about 5x10 cm (e.g., 1x10 cm ) at the Schottky rectifying junction and a concentration of about ten times greater (e.g., 3x10 cm ) at a junction between the drift region (12d) and a cathode region (12c). The thickness of the insulating regions (16) (e.g., SiO2) in the MOS-filled trenches is also greater than about 1000 ANGSTROM to simultaneously inhibit field crowding and increase the breakdown voltage of the device. The nonuniformly doped drift region (12d) is preferably formed by epitaxial growth from the cathode region (12c) and doped in-situ.
摘要翻译：肖特基整流器（10）包括MOS填充的沟槽和在半导体衬底的表面处的阳极电极和在其中的最佳不均匀掺杂的漂移（12d）区域，其组合提供高阻断电压能力和低反向偏置漏电流和低正向压降。不均匀掺杂的漂移（12d）区域包含其中在远离形成在阳极电极（18）和漂移区域（12d）之间的肖特基整流功能的方向上单调增加的第一导电类型掺杂剂的浓度。漂移区域中掺杂浓度的曲线优选是肖特基（Schottky）的浓度小于约5×10 16 cm -3（例如，1×10 16 cm -3）的线性或阶梯分布曲线整流结和在漂移区（12d）和阴极区（12c）之间的接合处的浓度约为十倍（例如3×10 17 cm -3）。 MOS填充沟槽中的绝缘区域（16）（例如SiO 2）的厚度也大于约1000，以同时抑制场占据并增加器件的击穿电压。非均匀掺杂漂移区（12d）优选通过从阴极区（12c）外延生长并原位掺杂而形成。

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