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1. 发明授权

US5227995A High density semiconductor memory module using split finger lead frame 失效
标题翻译：高密度半导体存储器模块，使用分割指尖引线框架
公开(公告)号：US5227995A
公开(公告)日：1993-07-13
申请号：US554635
申请日：1990-07-17
申请人： Erich Klink , Helmut Kohler , Harald Pross
发明人： Erich Klink , Helmut Kohler , Harald Pross
IPC分类号： H01L23/50 , H01L23/495 , H01L23/498
CPC分类号： H01L23/49811 , H01L23/4951 , H01L23/49551 , H01L23/49555 , H01L23/49575 , H01L24/49 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/4918 , H01L2224/73215 , H01L24/48 , H01L2924/00014 , H01L2924/01032 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181
摘要： The semiconductor memory module comprises a housing of plastic or ceramic in which two chips are stacked together back-to-back. The pads of the chips are electrically connected by wire bonding to beam leads which comprise outer bond leads, generally arranged outside the housing to form the contact pins or contact leads of the module to a printed circuit board, and inner bond leads in the housing. The inner bond leads are split and spread in the area of the inner lead bond ends into upper and lower sets forming a gap for receiving and holding the stacked chips.
摘要翻译：提供了一种方法和存储器模块，其允许以最小的模块尺寸增加和低制造成本来重复存储器模块的密度。该方法使用众所周知的技术，其通过制造在模制塑料或陶瓷壳体内仅包含一个芯片的DIP模块来使用。与通常的方法相反，内部接合引线被冲压，使得它们具有比普通内部引线更大的宽度。随后或与冲压步骤一起，将内部接合引线开槽，以便允许在之前获得的每个较小内部接合引线中的至少一个弯曲以在两个内部引线之间提供空间。接下来，两个半导体存储器芯片被背对背地粘合在一起，并且插入在上部内部接合引线和下部内部接合引线之间的间隙中，使得上部和下部结合引线包围两个芯片。芯片可以等同于垫的占用，或镜像。该方法适用于双列直插封装（DIP）以及ZIG-ZAG封装。半导体存储器模块包括塑料或陶瓷的壳体（4），其中两个芯片（8,10）背对背地堆叠在一起。芯片的焊盘（20）通过引线接合电连接到通常布置在壳体外部的外部引线（6）的波纹引线（14），以形成模块的触发引脚或触点引线到印刷电路板和内部接合引线（16）。内部引线引线在内部引线接合端部扩展到上部（16a）和下部（16b）接合引线中，形成用于接收和包围堆叠的芯片的间隙（22）。

2. 发明申请

US20070022398A1 Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules 有权
标题翻译：通过/ BSM模式优化，可以降低单个和多个芯片模块上的直流梯度和引脚电流密度
公开(公告)号：US20070022398A1
公开(公告)日：2007-01-25
申请号：US11184350
申请日：2005-07-19
申请人： Anand Haridass , Andreas Huber , Erich Klink , Thomas Strach , Jochen Supper
发明人： Anand Haridass , Andreas Huber , Erich Klink , Thomas Strach , Jochen Supper
IPC分类号： G06F17/50 , H01L21/00
CPC分类号： H01L23/49833 , G06F17/5068 , H01L23/50 , H01L23/5385 , H01L2224/16 , H01L2924/09701 , H01L2924/15311 , H01L2924/3011
摘要： A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while providing a common electrical ground for both voltage domains. The integrated circuit chip may be a microprocessor having a nominal operating voltage, and the different voltages of the two voltage domains are both within the tolerance range of the nominal operating voltage but one of the voltage domains is aligned with a high power density area of the microprocessor (e.g., the microprocessor core) and provides a slightly greater voltage. The higher power voltage domain preferably has a ratio of voltage pins to ground pins that is greater than one.
摘要翻译：通过将两个不同的电压域分配给载体的接触表面的两个分开的区域，同时为两个电压域提供公共电接地来设计诸如集成电路芯片的电子装置的载体。集成电路芯片可以是具有额定工作电压的微处理器，并且两个电压域的不同电压都在标称工作电压的公差范围内，但是一个电压域与高功率密度区域微处理器（例如，微处理器内核）并提供略高的电压。较高的电源电压域优选地具有大于1的电压引脚与接地引脚的比率。

3. 发明申请

US20060219427A1 System and method for increasing wiring channels/density under dense via fields 失效
标题翻译：增加密集通道的布线通道/密度的系统和方法
公开(公告)号：US20060219427A1
公开(公告)日：2006-10-05
申请号：US11095741
申请日：2005-03-31
申请人： Anand Haridass , Dierk Kaller , Erich Klink , Gisbert Thomke
发明人： Anand Haridass , Dierk Kaller , Erich Klink , Gisbert Thomke
IPC分类号： H05K7/06
CPC分类号： G06F17/5077 , H01L21/486 , H01L23/49822 , H01L23/49838 , H01L2924/0002 , H05K1/111 , H05K1/112 , H05K3/0005 , H05K3/429 , H05K2201/09227 , H05K2201/10734 , Y10T29/49156 , H01L2924/00
摘要： A system and method for increasing the wiring channels/density under dense via fields of a circuit board are provided. With the system and method, the power/ground lines for the circuit board are designed to be provided in an orthogonal or diagonal pattern. The land grid array (LGA)/ball grid array (BGA) makes contact only on the surface pads of the printed circuit board with no plated through holes/vias underneath these surface pads. This opens up wiring channels, which previously used to be occupied by plated through holes and anti-pads, that can now be used for maximizing signal line wiring routing.
摘要翻译：提供了一种用于增加电路板密集通孔的布线通道/密度的系统和方法。利用系统和方法，电路板的电源/接地线被设计成以正交或对角线图案提供。栅格阵列（LGA）/球栅阵列（BGA）仅在印刷电路板的表面焊盘上接触，在这些表面焊盘下方没有电镀通孔/通孔。这打开了以前用于通过电镀通孔和防焊盘占用的接线通道，现在可以用于最大化信号线路由布线。

4. 发明授权

US06774836B2 Method for delta-noise reduction 失效
标题翻译：减少降噪的方法
公开(公告)号：US06774836B2
公开(公告)日：2004-08-10
申请号：US10462529
申请日：2003-06-16
申请人： Roland Frech , Bernd Garben , Hubert Harrer , Andreas Huber , Dierk Kaller , Erich Klink , Thomas-Michael Winkel , Wiren Dale Becker
发明人： Roland Frech , Bernd Garben , Hubert Harrer , Andreas Huber , Dierk Kaller , Erich Klink , Thomas-Michael Winkel , Wiren Dale Becker
IPC分类号： H04L1702
CPC分类号： G05F1/46
摘要： A method, digital circuit system and program product for reducing delta-I noise in a plurality of activity units connected to a common DC-supply voltage. In order to smooth the fluctuations (delta-I) of a total current demand I, and a respective resulting fluctuation of the supply voltage, a signalling scheme between said activity units and a supervisor unit which holds a system-specific “database” containing at least the current demand of each activity unit device when operating regularly. Dependent of the quantity of calculated, imminent delta-I a subset of said activity units with a respective current I demand is selected and controlled, for either temporarily delaying their beginning of activity in case of an imminent supply voltage drop, or temporarily continuing their activity with a predetermined, activity-specific NO-OP phase in case of an imminent supply voltage rise.
摘要翻译：一种用于减少连接到公共DC电源电压的多个活动单元中的Δ-I噪声的方法，数字电路系统和程序产品。为了平滑总电流需求I的波动（Δ-I）和相应的电源电压波动，所述活动单元与保持包含在系统特定的“数据库”的管理单元之间的信令方案最小化每个活动单位设备当定期运行时的当前需求。选择和控制所计算的即将来临的Delta-I的量的所述活动单元的一个子集，以便在即将发生的电源电压下降的情况下暂时延迟其开始的活动，或者暂时继续其活动在即将来临的电源电压升高的情况下具有预定的活动特定的NO-OP相。

5. 发明授权

US4259730A IIL With partially spaced collars 失效
标题翻译： IIL具有部分间隔的衣领
公开(公告)号：US4259730A
公开(公告)日：1981-03-31
申请号：US027223
申请日：1979-04-05
申请人： Klaus Heuber , Erich Klink , Volker Rudolph , Siegfried K. Wiedmann
发明人： Klaus Heuber , Erich Klink , Volker Rudolph , Siegfried K. Wiedmann
IPC分类号： G11C11/411 , H01L21/331 , H01L21/761 , H01L21/8226 , H01L27/02 , H01L27/082 , H01L29/73 , H03K3/288 , H03K19/091 , H01L27/04 , G11C11/40
CPC分类号： G11C11/4113 , H01L21/761 , H01L27/0233 , H01L27/0821 , H03K3/288
摘要： The invention relates to a monolithically integrated semiconductor arrangement with at least one integrated injection logic (I.sup.2 L) structure including an injection zone and an inverting transistor, the injection zone, and lateral thereto, the transistor base zone of a same first conductivity type being arranged in a semiconductor layer of a second conductivity type, which forms the emitter zone of the transistor, the transistor being completed by a collector zone of the second conductivity type, which is formed in the base zone, and the I.sup.2 L structure being surrounded at least partly by a separating zone introduced at a predetermined spacing into the semiconductor layer. The injection zone and the transistor base zone in the region of their edges facing each other are extended up to or into the separating zone, while in the region of their remaining edges they are spaced therefrom at the predetermined distance. The invention further relates to a storage arrangement having storage cells including two such I.sup.2 L structures each which are cross-coupled in the manner of a flip-flop.
摘要翻译：本发明涉及一种具有至少一个集成注入逻辑（I2L）结构的单片集成半导体装置，该集成注入逻辑（I2L）结构包括注入区和反相晶体管，注入区和与其侧向的相同的第一导电类型的晶体管基极区布置在第二导电类型的半导体层，其形成晶体管的发射极区，晶体管由形成在基极区中的第二导电类型的集电极区完成，并且该I2L结构至少部分地被以预定间隔引入到半导体层中的分离区。注入区和位于其边缘彼此面对的区域中的晶体管基区延伸到分离区或分离区，而在其剩余边缘的区域中，它们以预定距离与其间隔开。本发明还涉及具有存储单元的存储装置，该存储单元包括两个这样的I2L结构，每个结构以触发器的方式交叉耦合。

6. 发明授权

US07742315B2 Circuit on a printed circuit board 失效
标题翻译：印刷电路板上的电路
公开(公告)号：US07742315B2
公开(公告)日：2010-06-22
申请号：US11282041
申请日：2005-11-17
申请人： Wiren D. Becker , Bruce J. Chamberlin , Gerald J. Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
发明人： Wiren D. Becker , Bruce J. Chamberlin , Gerald J. Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
IPC分类号： H05K1/11 , H05K1/14
CPC分类号： H05K1/11 , H01R12/523 , H01R13/6466 , H01R13/6471 , H01R13/6589 , H01R13/6625 , H05K1/0216 , H05K1/162 , H05K3/429 , H05K2201/044 , H05K2201/09309 , H05K2201/09336 , H05K2201/10189
摘要： The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring.In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.
摘要翻译：本发明涉及计算机硬件设计，特别涉及一种包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板组件的布线的印刷电路板（卡）。特别是在卡到卡连接器的引脚进入卡不连续的层结构的位置处，制动给定信号布线的高频信号返回路径。为了封闭从包括连接器的卡到卡的信号路径周围的信号返回路径，并且因此限制信号耦合，同时保持卡设计尽可能简单，建议提供a）附加电容在不连续部分中的给定信号布线，b）其中附加电容由放置在位于给定信号布线旁边的信号层内的电压岛形成。

7. 发明授权

US07302664B2 System and method for automatic insertion of on-chip decoupling capacitors 失效
标题翻译：自动插入片上去耦电容的系统和方法
公开(公告)号：US07302664B2
公开(公告)日：2007-11-27
申请号：US11054916
申请日：2005-02-10
申请人： Anand Haridass , Andreas Huber , Erich Klink , Jochen Supper
发明人： Anand Haridass , Andreas Huber , Erich Klink , Jochen Supper
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise distribution per cell of an integrated circuit is determined. This noise distribution may be generated using any of a number of different known mechanisms and generally results in a noise-map being generated for the integrated circuit. Thereafter, a mapping function is applied to the noise map for each cell to determine a required capacitance for the cells of the integrated circuit. From this required capacitance per cell, the necessary decoupling capacitors may be identified as well as the location for insertion of these decoupling capacitors. In a similar manner, decoupling capacitors may be removed from cells of the integrated circuit based upon the determined required capacitance per cell.
摘要翻译：提供一种用于自动插入片上去耦电容器的系统和方法。利用该系统和方法，将集成电路设计划分为单元，确定集成电路的每个单元的噪声分布。该噪声分布可以使用多个不同的已知机构中的任何一个产生，并且通常导致为集成电路产生噪声映射。此后，将映射函数应用于每个单元的噪声图，以确定集成电路的单元所需的电容。根据每个电池所需的电容，可以识别必要的去耦电容以及插入这些去耦电容器的位置。以类似的方式，可以基于每个单元所确定的所需电容从集成电路的单元去除去耦电容器。

8. 发明申请

US20070111576A1 Circuit on a printed circuit board 失效
标题翻译：印刷电路板上的电路
公开(公告)号：US20070111576A1
公开(公告)日：2007-05-17
申请号：US11282041
申请日：2005-11-17
申请人： Wiren Becker , Bruce Chamberlin , Gerald Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
发明人： Wiren Becker , Bruce Chamberlin , Gerald Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
IPC分类号： H01R13/15
CPC分类号： H05K1/11 , H01R12/523 , H01R13/6466 , H01R13/6471 , H01R13/6589 , H01R13/6625 , H05K1/0216 , H05K1/162 , H05K3/429 , H05K2201/044 , H05K2201/09309 , H05K2201/09336 , H05K2201/10189
摘要： The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring. In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.
摘要翻译：本发明涉及计算机硬件设计，特别涉及一种包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板组件的布线的印刷电路板（卡）。特别是在卡到卡连接器的引脚进入卡不连续的层结构的位置处，制动给定信号布线的高频信号返回路径。为了封闭从包括连接器的卡到卡的信号路径周围的信号返回路径，并且因此限制信号耦合，同时保持卡设计尽可能简单，建议提供a）附加电容在不连续部分中的给定信号布线，b）其中附加电容由放置在位于给定信号布线旁边的信号层内的电压岛形成。

9. 发明申请

US20060214190A1 System and method for noise reduction in multi-layer ceramic packages 有权
标题翻译：多层陶瓷封装中降噪的系统和方法
公开(公告)号：US20060214190A1
公开(公告)日：2006-09-28
申请号：US11086719
申请日：2005-03-22
申请人： Sungjun Chun , Jason Frankel , Anand Haridass , Erich Klink , Brian Singletary
发明人： Sungjun Chun , Jason Frankel , Anand Haridass , Erich Klink , Brian Singletary
IPC分类号： H01L27/10
CPC分类号： H01L23/49822 , H01L23/49838 , H01L23/552 , H01L23/66 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0224 , H05K1/0253 , H05K1/0306 , H05K3/4629 , H05K2201/09681 , H01L2924/00
摘要： A system and method for reducing noise in a multi-layer ceramic package are provided. With the system and method, additional shielding wires are inserted into the reference planes wherever there are no signal vias present. These additional lines in the reference planes force stronger signal interaction with the reference (vdd/gnd) thereby reducing the interaction between the signals in the signal layers. As a result, the noise present in the signals of the signal layers is reduced.
摘要翻译：提供了一种用于降低多层陶瓷封装中的噪声的系统和方法。利用系统和方法，在没有信号通孔的地方，附加的屏蔽线插入参考平面。参考平面中的这些附加线强制与参考（vdd / gnd）的信号相互作用更强，从而减少信号层中信号之间的相互作用。结果，信号层的信号中存在的噪声降低。

10. 发明申请

US20060190892A1 System and method for automatic insertion of on-chip decoupling capacitors 失效
标题翻译：自动插入片上去耦电容的系统和方法
公开(公告)号：US20060190892A1
公开(公告)日：2006-08-24
申请号：US11054916
申请日：2005-02-10
申请人： Anand Haridass , Andreas Huber , Erich Klink , Jochen Supper
发明人： Anand Haridass , Andreas Huber , Erich Klink , Jochen Supper
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise distribution per cell of an integrated circuit is determined. This noise distribution may be generated using any of a number of different known mechanisms and generally results in a noise-map being generated for the integrated circuit. Thereafter, a mapping function is applied to the noise map for each cell to determine a required capacitance for the cells of the integrated circuit. From this required capacitance per cell, the necessary decoupling capacitors may be identified as well as the location for insertion of these decoupling capacitors. In a similar manner, decoupling capacitors may be removed from cells of the integrated circuit based upon the determined required capacitance per cell.
摘要翻译：提供一种用于自动插入片上去耦电容器的系统和方法。利用该系统和方法，将集成电路设计划分为单元，确定集成电路的每个单元的噪声分布。该噪声分布可以使用多个不同的已知机构中的任何一个产生，并且通常导致为集成电路产生噪声映射。此后，将映射函数应用于每个单元的噪声图，以确定集成电路的单元所需的电容。根据每个电池所需的电容，可以识别必要的去耦电容以及插入这些去耦电容器的位置。以类似的方式，可以基于每个单元所确定的所需电容从集成电路的单元去除去耦电容器。

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