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1. 发明授权

US07503111B2 Method for increasing wiring channels/density under dense via fields 失效
标题翻译：增加密集通道的布线通道/密度的方法
公开(公告)号：US07503111B2
公开(公告)日：2009-03-17
申请号：US11095741
申请日：2005-03-31
申请人： Anand Haridass , Dierk Kaller , Erich Klink , Gisbert Gerhard Thomke
发明人： Anand Haridass , Dierk Kaller , Erich Klink , Gisbert Gerhard Thomke
IPC分类号： H05K3/02
CPC分类号： G06F17/5077 , H01L21/486 , H01L23/49822 , H01L23/49838 , H01L2924/0002 , H05K1/111 , H05K1/112 , H05K3/0005 , H05K3/429 , H05K2201/09227 , H05K2201/10734 , Y10T29/49156 , H01L2924/00
摘要： A method for increasing the wiring channels/density under dense via fields of a circuit board are provided. With the method, the power/ground lines for the circuit board are designed to be provided in an orthogonal or diagonal pattern. The land grid array (LGA)/ball grid array (BGA) makes contact only on the surface pads of the printed circuit board with no plated through holes/vias underneath these surface pads. This opens up wiring channels, which previously used to be occupied by plated through holes and anti-pads, that can now be used for maximizing signal line wiring routing.
摘要翻译：提供了一种用于增加电路板密集通孔的布线通道/密度的方法。利用该方法，电路板的电源/接地线被设计成以正交或对角线图案提供。栅格阵列（LGA）/球栅阵列（BGA）仅在印刷电路板的表面焊盘上接触，在这些表面焊盘下方没有电镀通孔/通孔。这打开了以前用于通过电镀通孔和防焊盘占用的接线通道，现在可以用于最大化信号线路由布线。

2. 发明授权

US07266788B2 Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules 有权
公开(公告)号：US07266788B2
公开(公告)日：2007-09-04
申请号：US11184350
申请日：2005-07-19
申请人： Anand Haridass , Andreas Huber , Erich Klink , Thomas Strach , Jochen Supper
发明人： Anand Haridass , Andreas Huber , Erich Klink , Thomas Strach , Jochen Supper
IPC分类号： G06F17/50
CPC分类号： H01L23/49833 , G06F17/5068 , H01L23/50 , H01L23/5385 , H01L2224/16 , H01L2924/09701 , H01L2924/15311 , H01L2924/3011
摘要： A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while providing a common electrical ground for both voltage domains. The integrated circuit chip may be a microprocessor having a nominal operating voltage, and the different voltages of the two voltage domains are both within the tolerance range of the nominal operating voltage but one of the voltage domains is aligned with a high power density area of the microprocessor (e.g., the microprocessor core) and provides a slightly greater voltage. The higher power voltage domain preferably has a ratio of voltage pins to ground pins that is greater than one.

3. 发明申请

US20070080436A1 System and Method for Noise Reduction in Multi-Layer Ceramic Packages 审中-公开
标题翻译：多层陶瓷封装降噪系统及方法
公开(公告)号：US20070080436A1
公开(公告)日：2007-04-12
申请号：US11538531
申请日：2006-10-04
申请人： Sungjun Chun , Jason Frankel , Anand Haridass , Erich Klink , Brian Singletary
发明人： Sungjun Chun , Jason Frankel , Anand Haridass , Erich Klink , Brian Singletary
IPC分类号： H01L23/495
CPC分类号： H01L23/49822 , H01L23/49838 , H01L23/552 , H01L23/66 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0224 , H05K1/0253 , H05K1/0306 , H05K3/4629 , H05K2201/09681 , H01L2924/00
摘要： A system and method for reducing noise in a multi-layer ceramic package are provided. With the system and method, additional shielding wires are inserted into the reference planes wherever there are no signal vias present. These additional lines in the reference planes force stronger signal interaction with the reference (vdd/gnd) thereby reducing the interaction between the signals in the signal layers. As a result, the noise present in the signals of the signal layers is reduced.
摘要翻译：提供了一种用于降低多层陶瓷封装中的噪声的系统和方法。利用系统和方法，在没有信号通孔的地方，附加的屏蔽线插入到参考平面中。参考平面中的这些附加线强制与参考（vdd / gnd）的信号相互作用更强，从而减少信号层中信号之间的相互作用。结果，信号层的信号中存在的噪声降低。

4. 发明授权

US06967398B2 Module power distribution network 失效
标题翻译：模块配电网络
公开(公告)号：US06967398B2
公开(公告)日：2005-11-22
申请号：US10906152
申请日：2005-02-04
申请人： Roland Frech , Bernd Garben , Erich Klink , Stefano Oggioni
发明人： Roland Frech , Bernd Garben , Erich Klink , Stefano Oggioni
IPC分类号： H01L23/12 , H01L23/498 , H05K1/00 , H05K1/02 , H01L23/52
CPC分类号： H05K1/0216 , H01L23/49822 , H01L2224/16 , H01L2224/16235 , H01L2924/09701 , H01L2924/15192 , H01L2924/19105 , H01L2924/3011 , H05K1/0231 , H05K1/0298 , H05K2201/09327 , H05K2201/10522 , H05K2201/10734
摘要： A multi-layer module for packaging an electronic component comprises an uppermost electrically conductive layer for mounting the component, a plurality of electrically insulative layers, and a plurality of electrically conductive layers disposed between the insulative layers. The electrically conductive layers form staggered placements of at least three voltage and/or ground distribution layers close to the module surface without signal wiring layers in between, and signal distribution layers comprising signal conductors. Vias form conductive paths through the insulative layers and conductive layers; the corresponding signal, voltage and ground distribution layers are electrically connected with each other and with the uppermost layer.
摘要翻译：用于封装电子部件的多层模块包括用于安装部件的最上层的导电层，多个电绝缘层以及设置在绝缘层之间的多个导电层。导电层在靠近模块表面的至少三个电压和/或接地分布层之间形成交错布置，而其间不包括信号布线层，以及包括信号导体的信号分布层。通孔形成穿过绝缘层和导电层的导电路径; 相应的信号，电压和地面分布层彼此电连接并与最上层电连接。

5. 发明授权

US06665843B2 Method and system for quantifying the integrity of an on-chip power supply network 失效
公开(公告)号：US06665843B2
公开(公告)日：2003-12-16
申请号：US10053197
申请日：2002-01-18
申请人： Roland Frech , Andreas Huber , Erich Klink , Jochen Supper
发明人： Roland Frech , Andreas Huber , Erich Klink , Jochen Supper
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method and system for analyzing the dynamic behavior of an electrical circuit to determine whether a voltage level provided by a power supply network drops below a predetermined voltage level during operation of the electrical circuit is described. In a first step, a design data set representing pertinent technical specifications of an electrical or an integrated circuit are read in order to extract location information and value of switching and non-switching capacitance. Next, the circuit and technology propagation speeds are inputted therein. The length for specifying the size of a portion of a circuit area is determined wherein the electrical circuit is formed. Next, the circuit area is divided into a plurality of partitions of a specified size, and the switching capacitance and the non-switching capacitance are separately summarized for each partition. The voltage level drop is then calculated for each partition. Finally, the calculated voltage level drop is displayed in relation to the respective partition. The present method and system can be advantageously used for an on-chip power supply network evaluation as well as for an early chip development process.

6. 发明授权

US06535075B2 Tunable on-chip capacity 失效
标题翻译：可调芯片容量
公开(公告)号：US06535075B2
公开(公告)日：2003-03-18
申请号：US09737929
申请日：2000-12-15
申请人： Roland Frech , Erich Klink , Jochen Supper
发明人： Roland Frech , Erich Klink , Jochen Supper
IPC分类号： H03H701
CPC分类号： H01L27/0805
摘要： The invention relates to a tunable on-chip capacity circuit for a semiconductor chip (10) mounted on a substrate (30) and including a plurality of power supply decoupling capacitors (20-23) which can be selectively activated or deactivated by being switched on or off the power supply system. An on-chip detecting circuit (32) determines a circuit specific load/unload frequency of the on-chip power supply network, and on-chip control means (28, 33) responsive to signals of the detecting circuit increases or decreases the total of the on-chip capacity (CSD) by selectively activating or deactivating power supply decoupling capacitors (20-23). Off-chip path impedances (LMC, RMC), an off-chip capacity (CM) and the total on-chip capacity (CC), including the plurality of power supply decoupling capacitors (20-23) and parasitic on-chip capacities (CP), form a resonance loop (40) which is tunable by changing the total capacity (CSD) of the on-chip power supply decoupling capacitors. By tuning the total capacity (CSD) of the decoupling capacitors a resonance condition of the resonance loop (40) is met under which a minimum of switching power noise and a minimum switching power consumption is achieved.
摘要翻译：本发明涉及一种用于半导体芯片（10）的可调片上容量电路，该半导体芯片（10）安装在基板（30）上并且包括多个电源去耦电容器（20-23），该电源去耦电容器可通过接通而被选择性地激活或去激活或关闭供电系统。片上检测电路（32）确定片上电源网络的电路特定的负载/卸载频率，响应于检测电路的信号的片上控制装置（28,33）增加或减少片上容量（CSD）通过选择性地激活或去激活电源去耦电容器（20-23）。片外路径阻抗（LMC，RMC），片外容量（CM）和片上容量（CC），包括多个电源去耦电容器（20-23）和寄生片上容量（ CP）形成谐振回路（40），其可通过改变片上电源去耦电容器的总容量（CSD）来调节。通过调谐去耦电容器的总容量（CSD），满足谐振回路（40）的谐振条件，在该谐振回路（40）的谐振条件下达到最小开关功率噪声和最小开关功耗。

7. 发明授权

US06442041B2 MCM—MLC technology 失效
标题翻译： MCM-MLC技术
公开(公告)号：US06442041B2
公开(公告)日：2002-08-27
申请号：US09740280
申请日：2000-12-19
申请人： Simone Rehm , Bernd Garden , Erich Klink , Gisbert Thomke , William F. Shutler
发明人： Simone Rehm , Bernd Garden , Erich Klink , Gisbert Thomke , William F. Shutler
IPC分类号： H05K702
CPC分类号： H05K1/0224 , H01L23/5383 , H01L23/5384 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0253 , H05K1/0289 , H05K1/0298 , H05K2201/09681 , H01L2924/00
摘要： Disclosed is a multilayer electronics packaging structure, especially for use in a multi chip module. By forming an overlap of signal conductors by the respective mesh conductors, an improved shielding effect is achieved and coupling between signal conductors is reduced. By increasing the via punch pitch such that multiple wiring channels are formed between adjacent vias, wirability is improved and the number of signal distribution layers may be reduced. The new structure thus shows improved electrical properties over the state-of-the-art structures, combined with a cost reduction of about 35%.
摘要翻译：公开了一种多层电子封装结构，特别适用于多芯片模块。通过由相应的网状导体形成信号导体的重叠，实现了改进的屏蔽效果，并且减少了信号导线之间的耦合。通过增加通孔冲压间距，使得在相邻通路之间形成多个布线通道，可改善布线性，并且可以减少信号分布层的数量。因此，新结构显示出比现有技术结构更好的电性能，同时成本降低约35％。

8. 发明授权

US5157635A Input signal redriver for semiconductor modules 失效
标题翻译：用于半导体模块的输入信号转接器
公开(公告)号：US5157635A
公开(公告)日：1992-10-20
申请号：US728831
申请日：1991-07-09
申请人： Wayne F. Ellis , Erich Klink , Knut Najmann
发明人： Wayne F. Ellis , Erich Klink , Knut Najmann
IPC分类号： G11C7/22 , G11C8/18
CPC分类号： G11C8/18 , G11C7/22
摘要： A semiconductor packaging subassembly is described in which a plurality of modules or chips, repsonsive to a plurality of common input signals, are provided with input signal redriver circuits. Each redriver circuit is responsive to an input and provides an output signal to each the of chips in the subassembly. The preferred embodiment is directed to a multi-module memory arrangement in which input signals including CAS, RAS, W and address signals are received and redriven.
摘要翻译：描述了一种半导体封装子组件，其中对多个公共输入信号重现的多个模块或芯片设置有输入信号转接电路。每个转接电路响应于输入，并向子组件中的每个芯片提供输出信号。优选实施例涉及一种多模块存储装置，其中包括CAS，RAS，W和地址信号的输入信号被接收并重新驱动。

9. 发明授权

US4313177A Storage cell simulation for generating a reference voltage for semiconductor stores in mtl technology 失效
标题翻译：用于在mtl技术中为半导体存储器生成参考电压的存储单元模拟
公开(公告)号：US4313177A
公开(公告)日：1982-01-26
申请号：US147997
申请日：1980-05-12
申请人： Klaus Heuber , Erich Klink , Volker Rudolph , Siegfried K. Wiedmann
发明人： Klaus Heuber , Erich Klink , Volker Rudolph , Siegfried K. Wiedmann
IPC分类号： G11C11/414 , G11C11/4063 , G11C11/413 , H01L21/822 , H01L21/8229 , H01L27/02 , H01L27/04 , H01L27/102 , G11C11/40
CPC分类号： G11C11/413 , G11C11/4063 , H01L27/0233
摘要： Disclosed is a simulated storage cell structure for use as a reference voltage generator in a semiconductor store fabricated in Merged Transistor Logic (MTL) technology. The simulated storage cell structure includes n elongated regions of P-type diffusion arranged in parallel to each other in an N-type trough of semiconductor material. The elongated P-type regions are alternately designed as collector and Injector strips.
摘要翻译：公开了一种用于以合并晶体管逻辑（MTL）技术制造的半导体存储器中的参考电压发生器的模拟存储单元结构。模拟存储单元结构包括在半导体材料的N型槽中彼此平行布置的n个P型扩散区域。细长的P型区域交替设计为收集器和注射器条。

10. 发明授权

US07742315B2 Circuit on a printed circuit board 失效
标题翻译：印刷电路板上的电路
公开(公告)号：US07742315B2
公开(公告)日：2010-06-22
申请号：US11282041
申请日：2005-11-17
申请人： Wiren D. Becker , Bruce J. Chamberlin , Gerald J. Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
发明人： Wiren D. Becker , Bruce J. Chamberlin , Gerald J. Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
IPC分类号： H05K1/11 , H05K1/14
CPC分类号： H05K1/11 , H01R12/523 , H01R13/6466 , H01R13/6471 , H01R13/6589 , H01R13/6625 , H05K1/0216 , H05K1/162 , H05K3/429 , H05K2201/044 , H05K2201/09309 , H05K2201/09336 , H05K2201/10189
摘要： The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring.In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.
摘要翻译：本发明涉及计算机硬件设计，特别涉及一种包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板组件的布线的印刷电路板（卡）。特别是在卡到卡连接器的引脚进入卡不连续的层结构的位置处，制动给定信号布线的高频信号返回路径。为了封闭从包括连接器的卡到卡的信号路径周围的信号返回路径，并且因此限制信号耦合，同时保持卡设计尽可能简单，建议提供a）附加电容在不连续部分中的给定信号布线，b）其中附加电容由放置在位于给定信号布线旁边的信号层内的电压岛形成。

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