专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07266788B2 Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules 有权
公开(公告)号：US07266788B2
公开(公告)日：2007-09-04
申请号：US11184350
申请日：2005-07-19
申请人： Anand Haridass , Andreas Huber , Erich Klink , Thomas Strach , Jochen Supper
发明人： Anand Haridass , Andreas Huber , Erich Klink , Thomas Strach , Jochen Supper
IPC分类号： G06F17/50
CPC分类号： H01L23/49833 , G06F17/5068 , H01L23/50 , H01L23/5385 , H01L2224/16 , H01L2924/09701 , H01L2924/15311 , H01L2924/3011
摘要： A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while providing a common electrical ground for both voltage domains. The integrated circuit chip may be a microprocessor having a nominal operating voltage, and the different voltages of the two voltage domains are both within the tolerance range of the nominal operating voltage but one of the voltage domains is aligned with a high power density area of the microprocessor (e.g., the microprocessor core) and provides a slightly greater voltage. The higher power voltage domain preferably has a ratio of voltage pins to ground pins that is greater than one.

2. 发明申请

US20070022398A1 Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules 有权
标题翻译：通过/ BSM模式优化，可以降低单个和多个芯片模块上的直流梯度和引脚电流密度
公开(公告)号：US20070022398A1
公开(公告)日：2007-01-25
申请号：US11184350
申请日：2005-07-19
申请人： Anand Haridass , Andreas Huber , Erich Klink , Thomas Strach , Jochen Supper
发明人： Anand Haridass , Andreas Huber , Erich Klink , Thomas Strach , Jochen Supper
IPC分类号： G06F17/50 , H01L21/00
CPC分类号： H01L23/49833 , G06F17/5068 , H01L23/50 , H01L23/5385 , H01L2224/16 , H01L2924/09701 , H01L2924/15311 , H01L2924/3011
摘要： A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while providing a common electrical ground for both voltage domains. The integrated circuit chip may be a microprocessor having a nominal operating voltage, and the different voltages of the two voltage domains are both within the tolerance range of the nominal operating voltage but one of the voltage domains is aligned with a high power density area of the microprocessor (e.g., the microprocessor core) and provides a slightly greater voltage. The higher power voltage domain preferably has a ratio of voltage pins to ground pins that is greater than one.
摘要翻译：通过将两个不同的电压域分配给载体的接触表面的两个分开的区域，同时为两个电压域提供公共电接地来设计诸如集成电路芯片的电子装置的载体。集成电路芯片可以是具有额定工作电压的微处理器，并且两个电压域的不同电压都在标称工作电压的公差范围内，但是一个电压域与高功率密度区域微处理器（例如，微处理器内核）并提供略高的电压。较高的电源电压域优选地具有大于1的电压引脚与接地引脚的比率。

3. 发明授权

US07302664B2 System and method for automatic insertion of on-chip decoupling capacitors 失效
标题翻译：自动插入片上去耦电容的系统和方法
公开(公告)号：US07302664B2
公开(公告)日：2007-11-27
申请号：US11054916
申请日：2005-02-10
申请人： Anand Haridass , Andreas Huber , Erich Klink , Jochen Supper
发明人： Anand Haridass , Andreas Huber , Erich Klink , Jochen Supper
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise distribution per cell of an integrated circuit is determined. This noise distribution may be generated using any of a number of different known mechanisms and generally results in a noise-map being generated for the integrated circuit. Thereafter, a mapping function is applied to the noise map for each cell to determine a required capacitance for the cells of the integrated circuit. From this required capacitance per cell, the necessary decoupling capacitors may be identified as well as the location for insertion of these decoupling capacitors. In a similar manner, decoupling capacitors may be removed from cells of the integrated circuit based upon the determined required capacitance per cell.
摘要翻译：提供一种用于自动插入片上去耦电容器的系统和方法。利用该系统和方法，将集成电路设计划分为单元，确定集成电路的每个单元的噪声分布。该噪声分布可以使用多个不同的已知机构中的任何一个产生，并且通常导致为集成电路产生噪声映射。此后，将映射函数应用于每个单元的噪声图，以确定集成电路的单元所需的电容。根据每个电池所需的电容，可以识别必要的去耦电容以及插入这些去耦电容器的位置。以类似的方式，可以基于每个单元所确定的所需电容从集成电路的单元去除去耦电容器。

4. 发明申请

US20060190892A1 System and method for automatic insertion of on-chip decoupling capacitors 失效
标题翻译：自动插入片上去耦电容的系统和方法
公开(公告)号：US20060190892A1
公开(公告)日：2006-08-24
申请号：US11054916
申请日：2005-02-10
申请人： Anand Haridass , Andreas Huber , Erich Klink , Jochen Supper
发明人： Anand Haridass , Andreas Huber , Erich Klink , Jochen Supper
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise distribution per cell of an integrated circuit is determined. This noise distribution may be generated using any of a number of different known mechanisms and generally results in a noise-map being generated for the integrated circuit. Thereafter, a mapping function is applied to the noise map for each cell to determine a required capacitance for the cells of the integrated circuit. From this required capacitance per cell, the necessary decoupling capacitors may be identified as well as the location for insertion of these decoupling capacitors. In a similar manner, decoupling capacitors may be removed from cells of the integrated circuit based upon the determined required capacitance per cell.
摘要翻译：提供一种用于自动插入片上去耦电容器的系统和方法。利用该系统和方法，将集成电路设计划分为单元，确定集成电路的每个单元的噪声分布。该噪声分布可以使用多个不同的已知机构中的任何一个产生，并且通常导致为集成电路产生噪声映射。此后，将映射函数应用于每个单元的噪声图，以确定集成电路的单元所需的电容。根据每个电池所需的电容，可以识别必要的去耦电容以及插入这些去耦电容器的位置。以类似的方式，可以基于每个单元所确定的所需电容从集成电路的单元去除去耦电容器。

5. 发明授权

US06665843B2 Method and system for quantifying the integrity of an on-chip power supply network 失效
公开(公告)号：US06665843B2
公开(公告)日：2003-12-16
申请号：US10053197
申请日：2002-01-18
申请人： Roland Frech , Andreas Huber , Erich Klink , Jochen Supper
发明人： Roland Frech , Andreas Huber , Erich Klink , Jochen Supper
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method and system for analyzing the dynamic behavior of an electrical circuit to determine whether a voltage level provided by a power supply network drops below a predetermined voltage level during operation of the electrical circuit is described. In a first step, a design data set representing pertinent technical specifications of an electrical or an integrated circuit are read in order to extract location information and value of switching and non-switching capacitance. Next, the circuit and technology propagation speeds are inputted therein. The length for specifying the size of a portion of a circuit area is determined wherein the electrical circuit is formed. Next, the circuit area is divided into a plurality of partitions of a specified size, and the switching capacitance and the non-switching capacitance are separately summarized for each partition. The voltage level drop is then calculated for each partition. Finally, the calculated voltage level drop is displayed in relation to the respective partition. The present method and system can be advantageously used for an on-chip power supply network evaluation as well as for an early chip development process.

6. 发明授权

US07920978B2 Method for detecting noise events in systems with time variable operating points 失效
标题翻译：用于检测具有时间可变工作点的系统中的噪声事件的方法
公开(公告)号：US07920978B2
公开(公告)日：2011-04-05
申请号：US12262021
申请日：2008-10-30
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
IPC分类号： G06F1/26 , G06F11/30
CPC分类号： G06F1/305
摘要： A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.
摘要翻译：提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路。将经过时间平均的第一电压与第二电压进行比较。生成信号以指示处理器内的电路以启动动作以使电压进一步下降。

7. 发明授权

US07765504B2 Design method and system for minimizing blind via current loops 有权
标题翻译：通过电流回路最小化设计方法和系统
公开(公告)号：US07765504B2
公开(公告)日：2010-07-27
申请号：US11829179
申请日：2007-07-27
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Roger D. Weekly
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , H05K1/0216 , H05K1/115 , H05K3/0005 , H05K2201/09636
摘要： A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via.
摘要翻译：用于最小化盲通过电流回路的设计方法和系统提供了电互连结构设计的改进，而不需要广泛的电磁分析。检查通过携带关键信号的盲目附近的其他通孔是否适合于进行对应于由两个金属平面之间的层到另一层之间的过渡而被破坏的关键信号的返回电流。检查通过（s）的返回电流的距离，并且如果距离大于指定的阈值，则设计被调整以减小距离。如果盲目通过转换到外部层，合适的通孔将盲通孔内部的参考平面连接到外部端子。如果过渡在内层之间，合适的通孔是连接围绕由盲孔通过的参考平面的两个参考平面的通孔。

8. 发明授权

US07607028B2 Mitigate power supply noise response by throttling execution units based upon voltage sensing 失效
标题翻译：基于电压检测，通过调节执行单元来缓解电源噪声响应
公开(公告)号：US07607028B2
公开(公告)日：2009-10-20
申请号：US11420820
申请日：2006-05-30
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A system for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing in a circuit is provided. A sensing unit senses the voltage of a circuit. The sensing unit determines if the execution of another execution unit will cause the circuit voltage to drop below a threshold level. In response to a determination that the execution of another execution unit will cause the circuit voltage to drop below the threshold level, the execution unit is throttled.
摘要翻译：提供了一种通过基于电路中的电压感测的节流执行单元来减轻电源和配电系统噪声响应的系统。感测单元感测电路的电压。感测单元确定另一个执行单元的执行是否会导致电路电压降至阈值以下。响应于确定另一执行单元的执行将导致电路电压降低到阈值水平以下，执行单元被调节。

9. 发明授权

US07467050B2 Method for detecting noise events in systems with time variable operating points 失效
标题翻译：用于检测具有时间可变工作点的系统中的噪声事件的方法
公开(公告)号：US07467050B2
公开(公告)日：2008-12-16
申请号：US11420825
申请日：2006-05-30
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
IPC分类号： G06F1/26 , G06F11/30
CPC分类号： G06F1/305
摘要： A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.
摘要翻译：提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路。将经过时间平均的第一电压与第二电压进行比较。生成信号以指示处理器内的电路以启动动作以使电压进一步下降。

10. 发明申请

US20120148187A1 INTEGRATED CIRCUIT PACKAGE CONNECTED TO A DATA TRANSMISSION MEDIUM 有权
标题翻译：集成电路连接到数据传输介质的电路
公开(公告)号：US20120148187A1
公开(公告)日：2012-06-14
申请号：US13312327
申请日：2011-12-06
申请人： Harry Barowski , Thomas Brunschwiler , Roger F. Dangel , Hubert Harrer , Andreas Huber , Norbert M. Meier , Bruno Michel , Tim Niggemeier , Stephan Paredes , Jochen Supper , Jonas R. Weiss
发明人： Harry Barowski , Thomas Brunschwiler , Roger F. Dangel , Hubert Harrer , Andreas Huber , Norbert M. Meier , Bruno Michel , Tim Niggemeier , Stephan Paredes , Jochen Supper , Jonas R. Weiss
IPC分类号： H01L23/538 , H01L21/50 , G02B6/12
CPC分类号： G02B6/43 , H01L23/3128 , H01L23/481 , H01L23/5226 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0657 , H01L2224/03464 , H01L2224/0401 , H01L2224/05009 , H01L2224/051 , H01L2224/05147 , H01L2224/05184 , H01L2224/05655 , H01L2224/131 , H01L2224/14183 , H01L2224/16145 , H01L2224/16195 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06534 , H01L2225/06551 , H01L2225/06565 , H01L2924/14 , H01L2924/1533 , H01L2924/014
摘要： An integrated circuit coupling device includes an integrated circuit package with N integrated circuit layers (L1-LN) arranged as a 3D stack; and a data transmission medium with n data transmission layers (l1-ln), wherein n≧1 and N≧2, and wherein the N integrated circuit layers are electrically connectable to the n data transmission layers.
摘要翻译：集成电路耦合装置包括具有以3D叠层排列的N个集成电路层（L1-LN）的集成电路封装; 以及具有n个数据传输层（111-1）的数据传输介质，其中n≥1且N≥2，并且其中所述N个集成电路层可电连接到所述n个数据传输层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式