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1. 发明申请

US20050167811A1 MODULE POWER DISTRIBUTION NETWORK 失效
标题翻译：模块电力分配网络
公开(公告)号：US20050167811A1
公开(公告)日：2005-08-04
申请号：US10906152
申请日：2005-02-04
申请人： Roland Frech , Bernd Garben , Erich Klink , Stefano Oggioni
发明人： Roland Frech , Bernd Garben , Erich Klink , Stefano Oggioni
IPC分类号： H01L23/12 , H01L23/498 , H05K1/00 , H05K1/02 , H01L23/495
CPC分类号： H05K1/0216 , H01L23/49822 , H01L2224/16 , H01L2224/16235 , H01L2924/09701 , H01L2924/15192 , H01L2924/19105 , H01L2924/3011 , H05K1/0231 , H05K1/0298 , H05K2201/09327 , H05K2201/10522 , H05K2201/10734
摘要： A multi-layer module for packaging an electronic component comprises an uppermost electrically conductive layer for mounting the component, a plurality of electrically insulative layers, and a plurality of electrically conductive layers disposed between the insulative layers. The electrically conductive layers form staggered placements of at least three voltage and/or ground distribution layers close to the module surface without signal wiring layers in between, and signal distribution layers comprising signal conductors. Vias form conductive paths through the insulative layers and conductive layers; the corresponding signal, voltage and ground distribution layers are electrically connected with each other and with the uppermost layer.
摘要翻译：用于封装电子部件的多层模块包括用于安装部件的最上层的导电层，多个电绝缘层以及设置在绝缘层之间的多个导电层。导电层在靠近模块表面的至少三个电压和/或接地分布层之间形成交错布置，而其间不包括信号布线层，以及包括信号导体的信号分布层。通孔形成穿过绝缘层和导电层的导电路径; 相应的信号，电压和地面分布层彼此电连接并与最上层电连接。

2. 发明授权

US5956563A Method for reducing a transient thermal mismatch 失效
标题翻译：降低瞬态热失配的方法
公开(公告)号：US5956563A
公开(公告)日：1999-09-21
申请号：US765525
申请日：1997-01-09
申请人： Erich Klink , Dietmar Schmunkamp , Helmut Weber , Roland Frech , Bernd Garben , Hubert Harrer
发明人： Erich Klink , Dietmar Schmunkamp , Helmut Weber , Roland Frech , Bernd Garben , Hubert Harrer
IPC分类号： G06F1/20 , G06F1/10 , H01L21/321 , H01L21/60 , H01L23/34 , H03L7/06 , H01L21/00
CPC分类号： H01L23/34 , H01L2924/0002 , H01L2924/09701
摘要： The invention relates to a method for reducing a transient thermal mismatch between a first component and a second component which are in mechanical contact with one another. The temperature of the first component is controlled by the amount of energy dissipated thereby. The amount of energy dissipated is controlled as a function of a data pattern input into the first component which causes a certain number of gates within the component to switch per clock cycle. By determining the desired energy dissipation in terms of the number of gates which are to be switched and arranging the input data pattern accordingly, the thermal mismatch between the components may be reduced.
摘要翻译： PCT No.PCT / EP95 / 02152 Sec。 371日期1997年1月9日 102（e）日期1997年1月9日PCT Filed June 6，1995 PCT Pub。公开号WO96 / 39714 PCT 日期：1996年12月12日本发明涉及一种降低彼此机械接触的第一部件和第二部件之间的瞬态热失配的方法。第一部件的温度由其消耗的能量的量来控制。根据输入到第一组件的数据模式来控制消耗的能量，这导致组件内的一定数量的门在每个时钟周期内切换。通过根据要切换的栅极的数量确定期望的能量耗散并且相应地布置输入数据模式，可以减少部件之间的热失配。

3. 发明授权

US5812380A Mesh planes for multilayer module 失效
标题翻译：多层模块的网格平面
公开(公告)号：US5812380A
公开(公告)日：1998-09-22
申请号：US765526
申请日：1997-01-09
申请人： Roland Frech , Bernd Garben , Hubert Harrer , Erich Klink
发明人： Roland Frech , Bernd Garben , Hubert Harrer , Erich Klink
IPC分类号： H01L25/00 , H01L23/522 , H01L23/538 , H05K1/03 , H05K1/09 , H05K1/16
CPC分类号： H01L23/5383 , H01L2224/16225 , H01L2924/09701
摘要： A multilayer module for packaging at least one electronic component 50. The module includes a plurality of thickfilm layers, and a wiring structure 45 to permit the connection of on-module capacitors. The multilayer module is fabricated such that the wiring structure includes a partial mesh plane 46, 47, 48, and 49 between the topmost and second topmost layers of the thickfilm. Logic noise is reduced in the multilayer module by maximizing the mutual inductance between adjacent mesh planes.
摘要翻译： PCT No.PCT / EP95 / 02194 Sec。 371日期1997年1月9日 102（e）日期1997年1月9日PCT提交1995年6月7日PCT公布。公开号WO96 / 41376 日期1996年12月19日一种用于封装至少一个电子部件50的多层模块。该模块包括多个厚膜层以及允许模块间电容器连接的布线结构45。制造多层模块使得布线结构在厚膜的最上层和第二最上层之间包括部分网格平面46,47,48和49。通过最大化相邻网格平面之间的互感，多层模块中的逻辑噪声降低。

4. 发明授权

US4545115A Method and apparatus for making ohmic and/or Schottky barrier contacts to semiconductor substrates 失效
标题翻译：用于制造与半导体衬底的欧姆和/或肖特基势垒接触的方法和装置
公开(公告)号：US4545115A
公开(公告)日：1985-10-08
申请号：US565080
申请日：1983-12-23
申请人： Hans J. Bauer , Bernd Garben
发明人： Hans J. Bauer , Bernd Garben
IPC分类号： A62B1/20 , B63C9/28 , B64D25/14 , C23C14/56 , H01L21/28
CPC分类号： C23C14/56 , B64D25/14 , Y10S148/019 , Y10S148/022 , Y10S148/158
摘要： Disclosed is a method of making ohmic and/or Schottky barrier contacts to a silicon semiconductor substrate in which before depositing the metal on silicon semiconductor substrates containing integrated circuits which are covered by a mask having contact windows, the metal is initially deposited on freshly cleaned blank silicon semiconductor substrates mounted in the same vacuum chamber. In this manner any traces of oxygen present in the vacuum chamber are chemisorbed by the blank substrate resulting in deposition of a high quality oxide-free metal contacts on the device substrates.The disclosed apparatus comprises a deposition chamber maintained at a predetermined low pressure, a substrate holder carrying a plurality of blank silicon substrates and silicon substrates containing integrated circuit structures covered by a mask having contact windows, a source of metal placed in the chamber for evaporation or sputtering and a shutter arranged in close proximity with said substrate holder for shielding selected substrates during the initial stages of metal deposition.
摘要翻译：公开了一种制造欧姆和/或肖特基势垒接触到硅半导体衬底的方法，其中在将金属沉积在含有由具有接触窗口的掩模覆盖的集成电路的硅半导体衬底上之后，金属最初沉积在新鲜清洁的空白硅半导体基板安装在相同的真空室中。以这种方式，存在于真空室中的任何痕量氧气被空白衬底化学吸附，导致在器件衬底上沉积高质量无氧化物的金属接触。所公开的装置包括保持在预定低压的沉积室，承载多个空白硅衬底的衬底保持器和含有由具有接触窗口的掩模覆盖的集成电路结构的硅衬底，金属源放置在用于蒸发的腔室中，溅射和与所述衬底保持器紧密配合的快门，用于在金属沉积的初始阶段期间屏蔽所选择的衬底。

5. 发明授权

US07250812B2 Integrated circuit current regulator 失效
标题翻译：集成电路电流调节器
公开(公告)号：US07250812B2
公开(公告)日：2007-07-31
申请号：US10908289
申请日：2005-05-05
申请人： Roland Frech , Bernd Garben
发明人： Roland Frech , Bernd Garben
IPC分类号： G05F1/10
CPC分类号： G06F1/26
摘要： An integrated circuit current regulator that compensates for variation in current required based on the switching activity of the integrated circuit. A first embodiment incorporates a voltage controlled on-chip bypass circuit with a scaling unit to divide an input voltage into n fractional voltages and an on-chip voltage monitor to compare a fraction of the on-chip supply voltage with a reference voltage and control a corresponding on-chip power supply bypass. At least one bypass resistor per comparator is switched between the supply voltage and ground potential according to the output signal of the corresponding comparator to dampen power supply noise. The value of the by-pass resistance R increases with decreasing on-chip supply voltage and decreases with increasing supply voltage. A resistance as a function of supply voltage R(Vdd) characteristic is realized to reduce or eliminate mid-frequency power supply noise, caused by on-chip switching activity variations while minimizing additional on-chip power dissipation.
摘要翻译：集成电路电流调节器，其基于集成电路的开关活动来补偿所需电流的变化。第一实施例包括具有缩放单元的电压控制片上旁路电路，以将输入电压分成n个分数电压，并且片上电压监视器将片上电源电压的一部分与参考电压进行比较，并且控制相应的片上电源旁路。每个比较器至少有一个旁路电阻根据相应比较器的输出信号在电源电压和地电位之间切换，以抑制电源噪声。旁路电阻R的值随着片上电源电压的降低而增加，随着电源电压的增加而减小。实现了作为电源电压R（Vdd）特性的电阻，以减少或消除由片上开关活动变化引起的中频电源噪声，同时最大限度地减少额外的片上功耗。

6. 发明授权

US06967398B2 Module power distribution network 失效
标题翻译：模块配电网络
公开(公告)号：US06967398B2
公开(公告)日：2005-11-22
申请号：US10906152
申请日：2005-02-04
申请人： Roland Frech , Bernd Garben , Erich Klink , Stefano Oggioni
发明人： Roland Frech , Bernd Garben , Erich Klink , Stefano Oggioni
IPC分类号： H01L23/12 , H01L23/498 , H05K1/00 , H05K1/02 , H01L23/52
CPC分类号： H05K1/0216 , H01L23/49822 , H01L2224/16 , H01L2224/16235 , H01L2924/09701 , H01L2924/15192 , H01L2924/19105 , H01L2924/3011 , H05K1/0231 , H05K1/0298 , H05K2201/09327 , H05K2201/10522 , H05K2201/10734
摘要： A multi-layer module for packaging an electronic component comprises an uppermost electrically conductive layer for mounting the component, a plurality of electrically insulative layers, and a plurality of electrically conductive layers disposed between the insulative layers. The electrically conductive layers form staggered placements of at least three voltage and/or ground distribution layers close to the module surface without signal wiring layers in between, and signal distribution layers comprising signal conductors. Vias form conductive paths through the insulative layers and conductive layers; the corresponding signal, voltage and ground distribution layers are electrically connected with each other and with the uppermost layer.
摘要翻译：用于封装电子部件的多层模块包括用于安装部件的最上层的导电层，多个电绝缘层以及设置在绝缘层之间的多个导电层。导电层在靠近模块表面的至少三个电压和/或接地分布层之间形成交错布置，而其间不包括信号布线层，以及包括信号导体的信号分布层。通孔形成穿过绝缘层和导电层的导电路径; 相应的信号，电压和地面分布层彼此电连接并与最上层电连接。

7. 发明申请

US20050248390A1 INTEGRATED CIRCUIT CURRENT REGULATOR 失效
标题翻译：集成电路电流调节器
公开(公告)号：US20050248390A1
公开(公告)日：2005-11-10
申请号：US10908289
申请日：2005-05-05
申请人： Roland Frech , Bernd Garben
发明人： Roland Frech , Bernd Garben
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： An integrated circuit current regulator that compensates for variation in current required based on the switching activity of the integrated circuit. A first embodiment incorporates a voltage controlled on-chip bypass circuit with a scaling unit to divide an input voltage into n fractional voltages and an on-chip voltage monitor to compare a fraction of the on-chip supply voltage with a reference voltage and control a corresponding on-chip power supply bypass. At least one bypass resistor per comparator is switched between the supply voltage and ground potential according to the output signal of the corresponding comparator to dampen power supply noise. The value of the by-pass resistance R increases with decreasing on-chip supply voltage and decreases with increasing supply voltage. A resistance as a function of supply voltage R(Vdd) characteristic is realized to reduce or eliminate mid-frequency power supply noise, caused by on-chip switching activity variations while minimizing additional on-chip power dissipation.
摘要翻译：集成电路电流调节器，其基于集成电路的开关活动来补偿所需电流的变化。第一实施例包括具有缩放单元的电压控制片上旁路电路，以将输入电压分成n个分数电压，并且片上电压监视器将片上电源电压的一部分与参考电压进行比较，并且控制相应的片上电源旁路。每个比较器至少有一个旁路电阻根据相应比较器的输出信号在电源电压和地电位之间切换，以抑制电源噪声。旁路电阻R的值随着片上电源电压的降低而增加，随着电源电压的增加而减小。实现了作为电源电压R（Vdd）特性的电阻，以减少或消除由片上开关活动变化引起的中频电源噪声，同时最大限度地减少额外的片上功耗。

8. 发明授权

US06774836B2 Method for delta-noise reduction 失效
标题翻译：减少降噪的方法
公开(公告)号：US06774836B2
公开(公告)日：2004-08-10
申请号：US10462529
申请日：2003-06-16
申请人： Roland Frech , Bernd Garben , Hubert Harrer , Andreas Huber , Dierk Kaller , Erich Klink , Thomas-Michael Winkel , Wiren Dale Becker
发明人： Roland Frech , Bernd Garben , Hubert Harrer , Andreas Huber , Dierk Kaller , Erich Klink , Thomas-Michael Winkel , Wiren Dale Becker
IPC分类号： H04L1702
CPC分类号： G05F1/46
摘要： A method, digital circuit system and program product for reducing delta-I noise in a plurality of activity units connected to a common DC-supply voltage. In order to smooth the fluctuations (delta-I) of a total current demand I, and a respective resulting fluctuation of the supply voltage, a signalling scheme between said activity units and a supervisor unit which holds a system-specific “database” containing at least the current demand of each activity unit device when operating regularly. Dependent of the quantity of calculated, imminent delta-I a subset of said activity units with a respective current I demand is selected and controlled, for either temporarily delaying their beginning of activity in case of an imminent supply voltage drop, or temporarily continuing their activity with a predetermined, activity-specific NO-OP phase in case of an imminent supply voltage rise.
摘要翻译：一种用于减少连接到公共DC电源电压的多个活动单元中的Δ-I噪声的方法，数字电路系统和程序产品。为了平滑总电流需求I的波动（Δ-I）和相应的电源电压波动，所述活动单元与保持包含在系统特定的“数据库”的管理单元之间的信令方案最小化每个活动单位设备当定期运行时的当前需求。选择和控制所计算的即将来临的Delta-I的量的所述活动单元的一个子集，以便在即将发生的电源电压下降的情况下暂时延迟其开始的活动，或者暂时继续其活动在即将来临的电源电压升高的情况下具有预定的活动特定的NO-OP相。

9. 发明授权

US4158072A Method for making connections between contacts 失效
标题翻译：在联系人之间进行连接的方法
公开(公告)号：US4158072A
公开(公告)日：1979-06-12
申请号：US804676
申请日：1977-06-08
申请人： Armin Bohg , Marian Briska , Bernd Garben
发明人： Armin Bohg , Marian Briska , Bernd Garben
IPC分类号： H01L21/82 , H05K1/00 , B05D5/12 , B41M3/08 , H05K1/04 , H05K3/00
CPC分类号： H05K1/029 , H05K2203/175
摘要： A technique for providing interconnections between pairs of contact points associated with a conductive line pattern by the use of an interconnection defining tool which is selectively alignable with respect to the conductive line. The conductive line pattern comprises at least one conductive line which is either continuous or shows interruptions, and from which lines branch off to the contact points. The tool is adapted to the conductive line and consists of a row of elements, the distance between which is dimensionally related to the distance between the branch-offs. After the tool has been adjusted to the conductive line in accordance with the respective connections, the elements of the tool are used for interrupting or connecting the conductive line at predetermined positions. If a radiation mask is used as a tool, the elements of the tool consist of areas which differ from their surroundings in their radiation transparency, and the conductive line pattern may exist as a latent image on a substrate covered by a photoresist layer sensitive to radiation. The invention serves to provide, in a circuit arrangement with redundant elements, a single circuit, the final wiring of which excludes one or several defective redundant circuit elements.
摘要翻译：一种用于通过使用可相对于导电线选择性对准的互连限定工具来提供与导线图案相关联的接触点对之间的互连的技术。导线图案包括至少一条导线，其连续或显示中断，并且从该线分支到接触点。该工具适用于导线，并由一排元件组成，其间的距离在尺寸上与分支间的距离有关。在根据相应的连接将工具调整到导线之后，工具的元件用于在预定位置上中断或连接导线。如果使用辐射掩模作为工具，则工具的元件由其周围的辐射透明度不同的区域组成，并且导电线图案可以作为潜在图像存在于由辐射敏感的光致抗蚀剂层覆盖的基板上。本发明用于在具有冗余元件的电路布置中提供单个电路，其最终布线排除一个或多个有缺陷的冗余电路元件。

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