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1. 发明申请

US20060219427A1 System and method for increasing wiring channels/density under dense via fields 失效
标题翻译：增加密集通道的布线通道/密度的系统和方法
公开(公告)号：US20060219427A1
公开(公告)日：2006-10-05
申请号：US11095741
申请日：2005-03-31
申请人： Anand Haridass , Dierk Kaller , Erich Klink , Gisbert Thomke
发明人： Anand Haridass , Dierk Kaller , Erich Klink , Gisbert Thomke
IPC分类号： H05K7/06
CPC分类号： G06F17/5077 , H01L21/486 , H01L23/49822 , H01L23/49838 , H01L2924/0002 , H05K1/111 , H05K1/112 , H05K3/0005 , H05K3/429 , H05K2201/09227 , H05K2201/10734 , Y10T29/49156 , H01L2924/00
摘要： A system and method for increasing the wiring channels/density under dense via fields of a circuit board are provided. With the system and method, the power/ground lines for the circuit board are designed to be provided in an orthogonal or diagonal pattern. The land grid array (LGA)/ball grid array (BGA) makes contact only on the surface pads of the printed circuit board with no plated through holes/vias underneath these surface pads. This opens up wiring channels, which previously used to be occupied by plated through holes and anti-pads, that can now be used for maximizing signal line wiring routing.
摘要翻译：提供了一种用于增加电路板密集通孔的布线通道/密度的系统和方法。利用系统和方法，电路板的电源/接地线被设计成以正交或对角线图案提供。栅格阵列（LGA）/球栅阵列（BGA）仅在印刷电路板的表面焊盘上接触，在这些表面焊盘下方没有电镀通孔/通孔。这打开了以前用于通过电镀通孔和防焊盘占用的接线通道，现在可以用于最大化信号线路由布线。

2. 发明授权

US07503111B2 Method for increasing wiring channels/density under dense via fields 失效
标题翻译：增加密集通道的布线通道/密度的方法
公开(公告)号：US07503111B2
公开(公告)日：2009-03-17
申请号：US11095741
申请日：2005-03-31
申请人： Anand Haridass , Dierk Kaller , Erich Klink , Gisbert Gerhard Thomke
发明人： Anand Haridass , Dierk Kaller , Erich Klink , Gisbert Gerhard Thomke
IPC分类号： H05K3/02
CPC分类号： G06F17/5077 , H01L21/486 , H01L23/49822 , H01L23/49838 , H01L2924/0002 , H05K1/111 , H05K1/112 , H05K3/0005 , H05K3/429 , H05K2201/09227 , H05K2201/10734 , Y10T29/49156 , H01L2924/00
摘要： A method for increasing the wiring channels/density under dense via fields of a circuit board are provided. With the method, the power/ground lines for the circuit board are designed to be provided in an orthogonal or diagonal pattern. The land grid array (LGA)/ball grid array (BGA) makes contact only on the surface pads of the printed circuit board with no plated through holes/vias underneath these surface pads. This opens up wiring channels, which previously used to be occupied by plated through holes and anti-pads, that can now be used for maximizing signal line wiring routing.
摘要翻译：提供了一种用于增加电路板密集通孔的布线通道/密度的方法。利用该方法，电路板的电源/接地线被设计成以正交或对角线图案提供。栅格阵列（LGA）/球栅阵列（BGA）仅在印刷电路板的表面焊盘上接触，在这些表面焊盘下方没有电镀通孔/通孔。这打开了以前用于通过电镀通孔和防焊盘占用的接线通道，现在可以用于最大化信号线路由布线。

3. 发明授权

US07742315B2 Circuit on a printed circuit board 失效
标题翻译：印刷电路板上的电路
公开(公告)号：US07742315B2
公开(公告)日：2010-06-22
申请号：US11282041
申请日：2005-11-17
申请人： Wiren D. Becker , Bruce J. Chamberlin , Gerald J. Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
发明人： Wiren D. Becker , Bruce J. Chamberlin , Gerald J. Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
IPC分类号： H05K1/11 , H05K1/14
CPC分类号： H05K1/11 , H01R12/523 , H01R13/6466 , H01R13/6471 , H01R13/6589 , H01R13/6625 , H05K1/0216 , H05K1/162 , H05K3/429 , H05K2201/044 , H05K2201/09309 , H05K2201/09336 , H05K2201/10189
摘要： The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring.In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.
摘要翻译：本发明涉及计算机硬件设计，特别涉及一种包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板组件的布线的印刷电路板（卡）。特别是在卡到卡连接器的引脚进入卡不连续的层结构的位置处，制动给定信号布线的高频信号返回路径。为了封闭从包括连接器的卡到卡的信号路径周围的信号返回路径，并且因此限制信号耦合，同时保持卡设计尽可能简单，建议提供a）附加电容在不连续部分中的给定信号布线，b）其中附加电容由放置在位于给定信号布线旁边的信号层内的电压岛形成。

4. 发明申请

US20070111576A1 Circuit on a printed circuit board 失效
标题翻译：印刷电路板上的电路
公开(公告)号：US20070111576A1
公开(公告)日：2007-05-17
申请号：US11282041
申请日：2005-11-17
申请人： Wiren Becker , Bruce Chamberlin , Gerald Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
发明人： Wiren Becker , Bruce Chamberlin , Gerald Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
IPC分类号： H01R13/15
CPC分类号： H05K1/11 , H01R12/523 , H01R13/6466 , H01R13/6471 , H01R13/6589 , H01R13/6625 , H05K1/0216 , H05K1/162 , H05K3/429 , H05K2201/044 , H05K2201/09309 , H05K2201/09336 , H05K2201/10189
摘要： The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring. In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.
摘要翻译：本发明涉及计算机硬件设计，特别涉及一种包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板组件的布线的印刷电路板（卡）。特别是在卡到卡连接器的引脚进入卡不连续的层结构的位置处，制动给定信号布线的高频信号返回路径。为了封闭从包括连接器的卡到卡的信号路径周围的信号返回路径，并且因此限制信号耦合，同时保持卡设计尽可能简单，建议提供a）附加电容在不连续部分中的给定信号布线，b）其中附加电容由放置在位于给定信号布线旁边的信号层内的电压岛形成。

5. 发明授权

US06774836B2 Method for delta-noise reduction 失效
标题翻译：减少降噪的方法
公开(公告)号：US06774836B2
公开(公告)日：2004-08-10
申请号：US10462529
申请日：2003-06-16
申请人： Roland Frech , Bernd Garben , Hubert Harrer , Andreas Huber , Dierk Kaller , Erich Klink , Thomas-Michael Winkel , Wiren Dale Becker
发明人： Roland Frech , Bernd Garben , Hubert Harrer , Andreas Huber , Dierk Kaller , Erich Klink , Thomas-Michael Winkel , Wiren Dale Becker
IPC分类号： H04L1702
CPC分类号： G05F1/46
摘要： A method, digital circuit system and program product for reducing delta-I noise in a plurality of activity units connected to a common DC-supply voltage. In order to smooth the fluctuations (delta-I) of a total current demand I, and a respective resulting fluctuation of the supply voltage, a signalling scheme between said activity units and a supervisor unit which holds a system-specific “database” containing at least the current demand of each activity unit device when operating regularly. Dependent of the quantity of calculated, imminent delta-I a subset of said activity units with a respective current I demand is selected and controlled, for either temporarily delaying their beginning of activity in case of an imminent supply voltage drop, or temporarily continuing their activity with a predetermined, activity-specific NO-OP phase in case of an imminent supply voltage rise.
摘要翻译：一种用于减少连接到公共DC电源电压的多个活动单元中的Δ-I噪声的方法，数字电路系统和程序产品。为了平滑总电流需求I的波动（Δ-I）和相应的电源电压波动，所述活动单元与保持包含在系统特定的“数据库”的管理单元之间的信令方案最小化每个活动单位设备当定期运行时的当前需求。选择和控制所计算的即将来临的Delta-I的量的所述活动单元的一个子集，以便在即将发生的电源电压下降的情况下暂时延迟其开始的活动，或者暂时继续其活动在即将来临的电源电压升高的情况下具有预定的活动特定的NO-OP相。

6. 发明申请

US20120120577A1 REDUNDANT CLOCK CHANNEL FOR HIGH RELIABILITY CONNECTORS 失效
标题翻译：用于高可靠性连接器的冗余时钟通道
公开(公告)号：US20120120577A1
公开(公告)日：2012-05-17
申请号：US12946328
申请日：2010-11-15
申请人： Sungjun Chun , Daniel M. Dreps , Dierk Kaller , Rohan U. Mandrekar , Lei Shan
发明人： Sungjun Chun , Daniel M. Dreps , Dierk Kaller , Rohan U. Mandrekar , Lei Shan
IPC分类号： G06F1/16
CPC分类号： G06F1/185 , G06F1/10
摘要： A memory module configured to connect to a slot of a data processing system. A set of tabs is connected to the module and configured to electrically connect the module to the slot and to electrically connect the module to a clock of the data processing system. The set of tabs includes a first tab, a second tab, a third tab, and a fourth tab. The first tab and the second tab are opposite the third tab and the fourth tab. The first tab comprises a positive type tab, the second tab comprises a negative type tab, the third tab comprises a positive type tab, and the fourth tab comprises a negative type tab. The first and third tabs are configured to provide a first electrical connection to the clock. The second and fourth tabs are configured to provide a second electrical connection to the clock. Together, the first, second, third, and fourth tabs comprise two dual tabs.
摘要翻译：配置为连接到数据处理系统的时隙的存储器模块。一组标签连接到模块并且被配置为将模块电连接到插槽并且将模块电连接到数据处理系统的时钟。该组标签包括第一标签，第二标签，第三标签和第四标签。第一个选项卡和第二个选项卡与第三个选项卡和第四个选项卡相对。第一标签包括一个正型标签，该第二标签包括一个负型标签，该第三标签包括一个正型标签，该第四标签包括一个负型标签。第一和第三选项卡被配置为提供到时钟的第一电连接。第二和第四选项卡被配置为提供与时钟的第二电连接。一起，第一，第二，第三和第四标签包括两个双标签。

7. 发明授权

US06669488B2 Removable housing for mounting pin grid array 失效
公开(公告)号：US06669488B2
公开(公告)日：2003-12-30
申请号：US10016446
申请日：2001-12-10
申请人： Dierk Kaller , Willi Recktenwald , Gerhard Ruehle
发明人： Dierk Kaller , Willi Recktenwald , Gerhard Ruehle
IPC分类号： H01R1200
CPC分类号： H05K7/1084 , H01R12/57 , H01R13/187
摘要： An assembly for mounting elongated electrical contact elements to an integrated circuit package or printed circuit board. The assembly comprises a a base plate having a first surface and a multiplicity of recesses aligned with each other in the first surface. Each of the recesses is sized and configured to receive a respective one of the contact elements. The assembly also comprises first and second spaced apart supports extending from the base plate. The assembly also comprises first and second rods received by the first and second supports and supported parallel to each other. The first and second rods define an intervening slot aligned with the recesses. The assembly also comprises a multiplicity of the contact elements. One end of each of the contact elements is received in a respective one of the recesses. The contact elements are engaged by the first and second rods, whereby the contact elements are held in their respective recesses. The rods are removable from the first and second supports to permit the contact elements to be removed from the base plate.

8. 发明授权

US08257092B2 Redundant clock channel for high reliability connectors 失效
标题翻译：冗余时钟通道，用于高可靠性连接器
公开(公告)号：US08257092B2
公开(公告)日：2012-09-04
申请号：US12946328
申请日：2010-11-15
申请人： Sungjun Chun , Daniel M. Dreps , Dierk Kaller , Rohan U. Mandrekar , Lei Shan
发明人： Sungjun Chun , Daniel M. Dreps , Dierk Kaller , Rohan U. Mandrekar , Lei Shan
IPC分类号： H01R12/00
CPC分类号： G06F1/185 , G06F1/10
摘要： A memory module configured to connect to a slot of a data processing system. A set of tabs is connected to the module and configured to electrically connect the module to the slot and to electrically connect the module to a clock of the data processing system. The set of tabs includes a first tab, a second tab, a third tab, and a fourth tab. The first tab and the second tab are opposite the third tab and the fourth tab. The first tab comprises a positive type tab, the second tab comprises a negative type tab, the third tab comprises a positive type tab, and the fourth tab comprises a negative type tab. The first and third tabs are configured to provide a first electrical connection to the clock. The second and fourth tabs are configured to provide a second electrical connection to the clock. Together, the first, second, third, and fourth tabs comprise two dual tabs.
摘要翻译：配置为连接到数据处理系统的时隙的存储器模块。一组标签连接到模块并且被配置为将模块电连接到插槽并且将模块电连接到数据处理系统的时钟。该组标签包括第一标签，第二标签，第三标签和第四标签。第一个选项卡和第二个选项卡与第三个选项卡和第四个选项卡相对。第一标签包括一个正型标签，该第二标签包括一个负型标签，该第三标签包括一个正型标签，该第四标签包括一个负型标签。第一和第三选项卡被配置为提供到时钟的第一电连接。第二和第四选项卡被配置为提供与时钟的第二电连接。一起，第一，第二，第三和第四标签包括两个双标签。

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