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1. 发明授权

US07742315B2 Circuit on a printed circuit board 失效
标题翻译：印刷电路板上的电路
公开(公告)号：US07742315B2
公开(公告)日：2010-06-22
申请号：US11282041
申请日：2005-11-17
申请人： Wiren D. Becker , Bruce J. Chamberlin , Gerald J. Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
发明人： Wiren D. Becker , Bruce J. Chamberlin , Gerald J. Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
IPC分类号： H05K1/11 , H05K1/14
CPC分类号： H05K1/11 , H01R12/523 , H01R13/6466 , H01R13/6471 , H01R13/6589 , H01R13/6625 , H05K1/0216 , H05K1/162 , H05K3/429 , H05K2201/044 , H05K2201/09309 , H05K2201/09336 , H05K2201/10189
摘要： The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring.In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.
摘要翻译：本发明涉及计算机硬件设计，特别涉及一种包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板组件的布线的印刷电路板（卡）。特别是在卡到卡连接器的引脚进入卡不连续的层结构的位置处，制动给定信号布线的高频信号返回路径。为了封闭从包括连接器的卡到卡的信号路径周围的信号返回路径，并且因此限制信号耦合，同时保持卡设计尽可能简单，建议提供a）附加电容在不连续部分中的给定信号布线，b）其中附加电容由放置在位于给定信号布线旁边的信号层内的电压岛形成。

2. 发明授权

US08018095B2 Power conversion, control, and distribution system 有权
标题翻译：电力转换，控制和配电系统
公开(公告)号：US08018095B2
公开(公告)日：2011-09-13
申请号：US12425267
申请日：2009-04-16
申请人： Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Robert Covi , Gerald J. Fahr , Daniel James Barus
发明人： Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Robert Covi , Gerald J. Fahr , Daniel James Barus
IPC分类号： H02J3/38
CPC分类号： H02J1/102 , Y10T307/352 , Y10T307/707
摘要： A power conversion, control, and distribution system includes multiple bulk power regulator (BPR) subassemblies, a bulk power distribution (BPD) subassembly, and a bulk power controller and hub (BPCH) subassembly. The BPR subassemblies are each configured to provide regulated DC power from both AC input power and DC input power. The BPD subassembly is configured to distribute the regulated DC power. The BPCH subassembly is coupled to the multiple BPR subassemblies and the BPD subassembly. The BPCH subassembly is configured to monitor and control the BPR assemblies and the BPD assembly.
摘要翻译：电力转换，控制和分配系统包括多个大功率调节器（BPR）子组件，大容量配电（BPD）子组件和大容量功率控制器和集线器（BPCH）子组件。 BPR子组件各自配置为从交流输入功率和直流输入功率提供稳压的直流电源。 BPD子组件被配置为分配调节的直流电力。 BPCH子组件耦合到多个BPR子组件和BPD子组件。 BPCH子组件被配置为监视和控制BPR组件和BPD组件。

3. 发明申请

US20080065786A1 INCREASED PERFORMANCE USING MIXED MEMORY TYPES 有权
标题翻译：使用混合存储器类型提高性能
公开(公告)号：US20080065786A1
公开(公告)日：2008-03-13
申请号：US11530341
申请日：2006-09-08
申请人： Douglas A. Baska , Gerald J. Fahr
发明人： Douglas A. Baska , Gerald J. Fahr
IPC分类号： G06F3/00
CPC分类号： G06F13/1694
摘要： A memory unit includes a system memory controller coupled to a plurality of memory clock oscillators and a plurality of respective voltage controllers, wherein each memory clock oscillator and respective voltage controller are coupled to a memory receptacle and thus provide a plurality of memory receptacles, each receptacle in the plurality of receptacles having a separate power boundary for operation of a memory type. The memory unit provides a computing system with capabilities to operate a variety of memory types. Methods and computer program products of operation of the memory unit are provided.
摘要翻译：存储器单元包括耦合到多个存储器时钟振荡器和多个相应电压控制器的系统存储器控制器，其中每个存储器时钟振荡器和相应的电压控制器耦合到存储器插座，并因此提供多个存储器插座，每个插座在具有用于存储器类型的操作的单独的电源边界的多个插座中。存储器单元为计算系统提供了操作各种存储器类型的能力。提供了存储单元操作的方法和计算机程序产品。

4. 发明授权

US07516293B2 Increased performance using mixed memory types 有权
标题翻译：使用混合内存类型提高性能
公开(公告)号：US07516293B2
公开(公告)日：2009-04-07
申请号：US11530341
申请日：2006-09-08
申请人： Douglas A. Baska , Gerald J. Fahr
发明人： Douglas A. Baska , Gerald J. Fahr
IPC分类号： G06F12/00
CPC分类号： G06F13/1694
摘要： A memory unit includes a system memory controller coupled to a plurality of memory clock oscillators and a plurality of respective voltage controllers, wherein each memory clock oscillator and respective voltage controller are coupled to a memory receptacle and thus provide a plurality of memory receptacles, each receptacle in the plurality of receptacles having a separate power boundary for operation of a memory type. The memory unit provides a computing system with capabilities to operate a variety of memory types. Methods and computer program products of operation of the memory unit are provided.
摘要翻译：存储器单元包括耦合到多个存储器时钟振荡器和多个相应电压控制器的系统存储器控制器，其中每个存储器时钟振荡器和相应的电压控制器耦合到存储器插座，并因此提供多个存储器插座，每个插座在具有用于存储器类型的操作的单独的电源边界的多个插座中。存储器单元为计算系统提供了操作各种存储器类型的能力。提供了存储单元操作的方法和计算机程序产品。

5. 发明授权

US06396286B1 Apparatus and method for testing computer equipment for susceptibility to neutral to ground noise 失效
标题翻译：用于测试计算机设备对中性线对地噪声敏感的装置和方法
公开(公告)号：US06396286B1
公开(公告)日：2002-05-28
申请号：US09454395
申请日：1999-12-03
申请人： King M. Chu , William M. Lorenz , Tuan D. Ngo , Prabjit Singh , Gerald J. Fahr , John P. McConnell
发明人： King M. Chu , William M. Lorenz , Tuan D. Ngo , Prabjit Singh , Gerald J. Fahr , John P. McConnell
IPC分类号： G01R2702
CPC分类号： G01R31/001
摘要： The power supply of equipment being tested for common mode noise problems is connected to a source of power with the power and neutral input terminals of the power supply isolated from the power ground. Recorded common mode noise signals are then inserted between the power supply's neutral input terminal and power ground to produce problem conditions. When the cause of the problem conditions are identified, steps are taken to eliminate the condition.
摘要翻译：正在对共模噪声问题进行测试的设备的电源与电源隔离的电源和中性输入端连接到电源。然后将记录的共模噪声信号插入电源的中性输入端子和电源地之间，以产生问题状况。当确定问题状况的原因时，采取步骤消除条件。

6. 发明授权

US07681073B2 Arbitration system for redundant controllers, with output interlock and automatic switching capabilities 失效
标题翻译：冗余控制器仲裁系统，具有输出互锁和自动切换功能
公开(公告)号：US07681073B2
公开(公告)日：2010-03-16
申请号：US12259447
申请日：2008-10-28
申请人： Gary D. Anderson , Gerald J. Fahr , Raymond J. Harrington
发明人： Gary D. Anderson , Gerald J. Fahr , Raymond J. Harrington
IPC分类号： G06F11/00
CPC分类号： G06F11/20 , G06F11/2017
摘要： An arbitration mechanism is provided for arbitrating between redundant controllers having outputs electrically connected together and provided as input to at least one device under control. The arbitration mechanism includes logic for automatically determining which controller of the redundant controllers is active controller, and a hardware output interlock for the redundant controllers to ensure that output controlled by only the active controller is enabled as input to the at least one device. The arbitration mechanism also includes logic for monitoring the active controller for failure, and upon detection of failure, for automatically switching active control to another controller of the redundant controllers transparent to the at least one device.
摘要翻译：提供仲裁机制用于在具有电连接在一起的输出的冗余控制器之间进行仲裁，并将其作为输入提供给被控制的至少一个设备。仲裁机制包括用于自动确定冗余控制器的哪个控制器是主动控制器的逻辑，以及用于冗余控制器的硬件输出互锁，以确保仅由主动控制器控制的输出被启用为至少一个设备的输入。仲裁机制还包括用于监视主动控制器用于故障的逻辑，以及在检测到故障时，用于将主动控制自动切换到对至少一个设备透明的冗余控制器的另一个控制器。

7. 发明授权

US07643307B2 Fail safe redundant power supply in a multi-node computer system 失效
标题翻译：多节点计算机系统中的故障安全冗余电源
公开(公告)号：US07643307B2
公开(公告)日：2010-01-05
申请号：US11239602
申请日：2005-09-29
申请人： Frank E. Bosco , Douglas A. Baska , Joseph P. Corrado , Gerald J. Fahr , William P. Kostenko , Mitchell L. Zapotoski
发明人： Frank E. Bosco , Douglas A. Baska , Joseph P. Corrado , Gerald J. Fahr , William P. Kostenko , Mitchell L. Zapotoski
IPC分类号： H05K5/00
CPC分类号： G06F1/189 , G06F11/2015 , Y10T307/615
摘要： A data processing system and method providing a jumper which provides standby power from a redundant power supply to one of at least two critical functions in a frame having bays for holding at least two nodes. The redundant power supply supplying power to one of the nodes in the frame and one of the critical functions. A jumper is slidably engageable in the frame in place of one of the nodes. The jumper, when engaged in the frame, transfers power from the redundant power supply to the other of the critical functions. The jumper is included in a jumper book of an airblock which includes passive airblock books. Mechanical keys on the passive airblock books prevent the removal of the jumper book until after the passive airblock books are removed.
摘要翻译：一种提供跳线的数据处理系统和方法，该跳线在具有用于保持至少两个节点的托架的帧中从冗余电源提供待机功率至少两个关键功能中的一个。冗余电源为框架中的一个节点供电，并且是关键功能之一。跳线可滑动地接合在框架中以代替其中一个节点。跳线器在从事框架时将电源从冗余电源传送到另一个关键功能。跳线被包括在一个空气障碍物的跳线书中，其中包括被动空气障碍书籍。被动防风版书籍上的机械钥匙防止了跳线簿的删除，直到被动挡板书籍被移除。

8. 发明授权

US07290170B2 Arbitration method and system for redundant controllers, with output interlock and automatic switching capabilities 失效
标题翻译：冗余控制器的仲裁方法和系统，具有输出互锁和自动切换功能
公开(公告)号：US07290170B2
公开(公告)日：2007-10-30
申请号：US10820177
申请日：2004-04-07
申请人： Gary D. Anderson , Gerald J. Fahr , Raymond J. Harrington
发明人： Gary D. Anderson , Gerald J. Fahr , Raymond J. Harrington
IPC分类号： G06F11/00
CPC分类号： G06F11/20 , G06F11/2017
摘要： An arbitration mechanism is provided for arbitrating between redundant controllers having outputs electrically connected together and provided as input to at least one device under control. The arbitration mechanism includes logic for automatically determining which controller of the redundant controllers is active controller, and a hardware output interlock for the redundant controllers to ensure that output controlled by only the active controller is enabled as input to the at least one device. The arbitration mechanism also includes logic for monitoring the active controller for failure, and upon detection of failure, for automatically switching active control to another controller of the redundant controllers transparent to the at least one device.
摘要翻译：提供仲裁机制用于在具有电连接在一起的输出的冗余控制器之间进行仲裁，并将其作为输入提供给被控制的至少一个设备。仲裁机制包括用于自动确定冗余控制器的哪个控制器是主动控制器的逻辑，以及用于冗余控制器的硬件输出互锁，以确保仅由主动控制器控制的输出被启用为至少一个设备的输入。仲裁机制还包括用于监视主动控制器用于故障的逻辑，以及在检测到故障时，用于将主动控制自动切换到对至少一个设备透明的冗余控制器的另一个控制器。

9. 发明申请

US20100264731A1 POWER CONVERSION, CONTROL, AND DISTRIBUTION SYSTEM 有权
标题翻译：电力转换，控制和分配系统
公开(公告)号：US20100264731A1
公开(公告)日：2010-10-21
申请号：US12425267
申请日：2009-04-16
申请人： Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Covi , Gerald J. Fahr , Daniel James Barus
发明人： Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Covi , Gerald J. Fahr , Daniel James Barus
IPC分类号： H02J4/00
CPC分类号： H02J1/102 , Y10T307/352 , Y10T307/707
摘要： A power conversion, control, and distribution system includes multiple bulk power regulator (BPR) subassemblies, a bulk power distribution (BPD) subassembly, and a bulk power controller and hub (BPCH) subassembly. The BPR subassemblies are each configured to provide regulated DC power from both AC input power and DC input power. The BPD subassembly is configured to distribute the regulated DC power. The BPCH subassembly is coupled to the multiple BPR subassemblies and the BPD subassembly. The BPCH subassembly is configured to monitor and control the BPR assemblies and the BPD assembly.
摘要翻译：电力转换，控制和分配系统包括多个大功率调节器（BPR）子组件，大容量配电（BPD）子组件和大容量功率控制器和集线器（BPCH）子组件。 BPR子组件各自配置为从交流输入功率和直流输入功率提供稳压的直流电源。 BPD子组件被配置为分配调节的直流电力。 BPCH子组件耦合到多个BPR子组件和BPD子组件。 BPCH子组件被配置为监视和控制BPR组件和BPD组件。

10. 发明授权

US07805618B2 Component indicators used during extended power-off service 失效
标题翻译：在延长关机服务期间使用的组件指示器
公开(公告)号：US07805618B2
公开(公告)日：2010-09-28
申请号：US11357147
申请日：2006-02-17
申请人： Kevin R. Covi , Gerald J. Fahr , Raymond J. Harrington , Raymond A. Longhi , Edward J. Seminaro
发明人： Kevin R. Covi , Gerald J. Fahr , Raymond J. Harrington , Raymond A. Longhi , Edward J. Seminaro
IPC分类号： G06F1/00 , G06F15/177
CPC分类号： G06F1/263 , G06F1/30 , G06F11/325
摘要： A method and related apparatus for servicing an electrical/electronic device during power shut offs is provided. The apparatus comprises a service logic having a memory and control component for storing device information during normal device operation and one or more indicators driven by the memory and control component after power shut off to provide service signals. The service logic also includes an auxiliary energy source selectively engageable to provide auxiliary power to the memory and control component during power shut off and to enable providing of service signals through the indicator(s).
摘要翻译：提供了一种用于在电源关闭期间维护电气/电子设备的方法和相关装置。该装置包括具有用于在正常设备操作期间存储设备信息的存储器和控制组件的服务逻辑以及在电源关闭之后由存储器和控制组件驱动以提供服务信号的一个或多个指示器。服务逻辑还包括辅助能量源，其选择性地可接合以在电源切断期间向存储器和控制部件提供辅助电力，并且能够通过指示器提供服务信号。

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