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1. 发明申请

US20140025991A1 CORE DIAGNOSTICS AND REPAIR 有权
标题翻译：核心诊断和修复
公开(公告)号：US20140025991A1
公开(公告)日：2014-01-23
申请号：US13552237
申请日：2012-07-18
申请人： Sreekala Anandavally , Anand Haridass , Gerard M. Salem , Diyanesh B.C. Vidyapoornachary
发明人： Sreekala Anandavally , Anand Haridass , Gerard M. Salem , Diyanesh B.C. Vidyapoornachary
IPC分类号： G06F11/16
CPC分类号： G06F11/0793 , G06F11/0724 , G06F11/079 , G06F11/1428 , G06F11/16 , G06F11/2028 , G06F11/2041
摘要： Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.
摘要翻译：本公开的实施例涉及一种装置，其包括易受错误状况影响的第一核心，以及第二核心，被配置为对第一核心执行诊断以识别错误状况的原因以及纠正错误状况的动作命令恢复第一核心。

2. 发明授权

US08624297B2 Multi-layer circuit substrate fabrication and design methods providing improved transmission line integrity and increased routing density 有权
标题翻译：多层电路衬底制造和设计方法提供改进的传输线完整性和增加的路由密度
公开(公告)号：US08624297B2
公开(公告)日：2014-01-07
申请号：US12579517
申请日：2009-10-15
申请人： Sungjun Chun , Anand Haridass , Roger D. Weekly
发明人： Sungjun Chun , Anand Haridass , Roger D. Weekly
IPC分类号： H01L27/10 , H01L21/4763
CPC分类号： H01L21/76879 , H01L23/66 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/3011 , H05K1/0253 , H05K1/112 , H05K3/4602 , H05K2201/09536 , H05K2201/09627 , H05K2201/0969 , H01L2224/0401
摘要： An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.
摘要翻译：集成电路衬底被设计和制造，具有选择性地施加的传输线参考平面金属层，以实现信号路径屏蔽和隔离，同时避免由于大直径通孔和传输线参考平面金属层之间的电容引起的阻抗下降。传输线参考平面定义穿过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会由于并联电容引起的阻抗失配而降级从信号承载PTH的顶部（或底部）到传输线参考平面。对于电压平面轴承PTH，不引入空隙，使得信号路径导体可以路由在电压平面轴承PTH上方或附近，传输线参考平面防止信号路径导体和PTH之间的分流电容。

3. 发明申请

US20130103927A1 CHARACTERIZATION AND VALIDATION OF PROCESSOR LINKS 有权
标题翻译：处理器链接的特征和验证
公开(公告)号：US20130103927A1
公开(公告)日：2013-04-25
申请号：US13281081
申请日：2011-10-25
申请人： Robert W. Berry, JR. , Anand Haridass , Prasanna Jayaraman
发明人： Robert W. Berry, JR. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F15/00 , G06F9/30
CPC分类号： G06F11/3089 , G01R31/31926 , G06F9/30 , G06F9/30007 , G06F11/22 , G06F11/221 , G06F11/3409 , G06F11/3414 , G06F11/349 , G06F15/00
摘要： A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.
摘要翻译：选择耦合第一处理器和第二处理器的处理器链接用于验证，并且识别与第一处理器和第二处理器相关联的多个通信参数设置。第一和第二处理器依次配置有每个通信参数设置。根据通信参数设置，从第一处理器向第二处理器提供一个或多个测试数据模式。至少部分地基于在第二处理器处接收到的测试数据模式来确定与所选择的处理器链路和通信参数设置相关联的性能测量。选择与最高性能测量值相关联的通信参数设置之一。所选择的通信参数设置被应用于第一和第二处理器，用于经由处理器链路在第一和第二处理器之间进行后续通信。

4. 发明授权

US07920978B2 Method for detecting noise events in systems with time variable operating points 失效
标题翻译：用于检测具有时间可变工作点的系统中的噪声事件的方法
公开(公告)号：US07920978B2
公开(公告)日：2011-04-05
申请号：US12262021
申请日：2008-10-30
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
IPC分类号： G06F1/26 , G06F11/30
CPC分类号： G06F1/305
摘要： A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.
摘要翻译：提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路。将经过时间平均的第一电压与第二电压进行比较。生成信号以指示处理器内的电路以启动动作以使电压进一步下降。

5. 发明授权

US07765504B2 Design method and system for minimizing blind via current loops 有权
标题翻译：通过电流回路最小化设计方法和系统
公开(公告)号：US07765504B2
公开(公告)日：2010-07-27
申请号：US11829179
申请日：2007-07-27
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Roger D. Weekly
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , H05K1/0216 , H05K1/115 , H05K3/0005 , H05K2201/09636
摘要： A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via.
摘要翻译：用于最小化盲通过电流回路的设计方法和系统提供了电互连结构设计的改进，而不需要广泛的电磁分析。检查通过携带关键信号的盲目附近的其他通孔是否适合于进行对应于由两个金属平面之间的层到另一层之间的过渡而被破坏的关键信号的返回电流。检查通过（s）的返回电流的距离，并且如果距离大于指定的阈值，则设计被调整以减小距离。如果盲目通过转换到外部层，合适的通孔将盲通孔内部的参考平面连接到外部端子。如果过渡在内层之间，合适的通孔是连接围绕由盲孔通过的参考平面的两个参考平面的通孔。

6. 发明授权

US07607028B2 Mitigate power supply noise response by throttling execution units based upon voltage sensing 失效
标题翻译：基于电压检测，通过调节执行单元来缓解电源噪声响应
公开(公告)号：US07607028B2
公开(公告)日：2009-10-20
申请号：US11420820
申请日：2006-05-30
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A system for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing in a circuit is provided. A sensing unit senses the voltage of a circuit. The sensing unit determines if the execution of another execution unit will cause the circuit voltage to drop below a threshold level. In response to a determination that the execution of another execution unit will cause the circuit voltage to drop below the threshold level, the execution unit is throttled.
摘要翻译：提供了一种通过基于电路中的电压感测的节流执行单元来减轻电源和配电系统噪声响应的系统。感测单元感测电路的电压。感测单元确定另一个执行单元的执行是否会导致电路电压降至阈值以下。响应于确定另一执行单元的执行将导致电路电压降低到阈值水平以下，执行单元被调节。

7. 发明申请

US20090091378A1 Statistical Switched Capacitor Droop Sensor for Application in Power Distribution Noise Mitigation 有权
标题翻译：统计开关电容下降传感器，用于配电噪声减噪
公开(公告)号：US20090091378A1
公开(公告)日：2009-04-09
申请号：US11869186
申请日：2007-10-09
申请人： Anand Haridass , Colm B. O'Reilly , Roger D. Weekly
发明人： Anand Haridass , Colm B. O'Reilly , Roger D. Weekly
IPC分类号： H04B1/10
CPC分类号： G06F1/28
摘要： A circuit and a method for detecting noise events in a system with time variable operating points is provided. A switched capacitor filter comprising a plurality of capacitor units, samples a first voltage to determine an average of a set of voltage measurements, forming an average voltage. A filter control unit controls the plurality of capacitor units in the switched capacitor filter. A comparing unit compares the average voltage to the first voltage to form a comparison. A signaling unit generates a signal to instruct circuits in a processor to initiate actions to keep the first voltage from drooping below a threshold level in response to the comparison.
摘要翻译：提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路和方法。一种开关电容滤波器，包括多个电容器单元，对第一电压进行采样，以确定一组电压测量的平均值，形成平均电压。滤波器控制单元控制开关电容滤波器中的多个电容器单元。比较单元将平均电压与第一电压进行比较以形成比较。信号单元产生信号以指示处理器中的电路响应于比较而发起动作以使第一电压不会下降到低于阈值水平。

8. 发明授权

US07512183B2 Differential transmitter circuit 有权
标题翻译：差分发射电路
公开(公告)号：US07512183B2
公开(公告)日：2009-03-31
申请号：US11086718
申请日：2005-03-22
申请人： Anand Haridass , Bao G. Truong , Joel D. Ziegelbein
发明人： Anand Haridass , Bao G. Truong , Joel D. Ziegelbein
IPC分类号： H04B3/00
CPC分类号： H04L25/0274 , H03F3/45197 , H03F2200/543 , H03F2203/45488
摘要： A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated.
摘要翻译：驱动器电路被配置为具有耦合到第一数据信号的一个输入和耦合到第二数据信号的第二输入的频率补偿差分放大器。差分放大器的每个级都用电流源偏置。驱动器电路产生耦合到第一传输线的输入的第一输出信号和耦合到第二传输线的输入的第二输出信号。第一和第二输出信号被产生为由补偿增益放大的第一和第二数据信号之间的差。相对于高频分量衰减输入信号的低频分量的补偿网络耦合在偏置差分放大器的电流源之间。第一和第二传输线的输出耦合到差分接收机的输入端，该差分接收机可以被频率补偿也可以不被频率补偿。

9. 发明授权

US07467050B2 Method for detecting noise events in systems with time variable operating points 失效
标题翻译：用于检测具有时间可变工作点的系统中的噪声事件的方法
公开(公告)号：US07467050B2
公开(公告)日：2008-12-16
申请号：US11420825
申请日：2006-05-30
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
IPC分类号： G06F1/26 , G06F11/30
CPC分类号： G06F1/305
摘要： A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.
摘要翻译：提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路。将经过时间平均的第一电压与第二电压进行比较。生成信号以指示处理器内的电路以启动动作以使电压进一步下降。

10. 发明申请

US20080175327A1 SYSTEM FOR REDUCING CROSS-TALK INDUCED SOURCE SYNCHRONOUS BUS CLOCK JITTER 有权
标题翻译：用于减少交叉输入源同步总线时钟抖动器的系统
公开(公告)号：US20080175327A1
公开(公告)日：2008-07-24
申请号：US12058689
申请日：2008-03-29
申请人： Bao G. Truong , Daniel Mark Dreps , Anand Haridass , John C. Schiff , Joel D. Ziegelbein
发明人： Bao G. Truong , Daniel Mark Dreps , Anand Haridass , John C. Schiff , Joel D. Ziegelbein
IPC分类号： H04B3/00
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译：使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以第一个时钟信号的补码。从第一时钟信号产生频率为F / 2的第二时钟信号。第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。在一个实施例中，使用延迟线电路来移位第二时钟。在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。

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