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1. 发明申请

US20230135932A1 THERMALLY ENHANCED ISOLATED POWER CONVERTER PACKAGE 有权
公开(公告)号：US20230135932A1
公开(公告)日：2023-05-04
申请号：US17515150
申请日：2021-10-29
申请人： Texas Instruments Incorporated
发明人： Vijaylaxmi Gumaste Khanolkar
IPC分类号： H01L23/495 , H01L23/31 , H01L23/00 , H01L25/00 , H01L21/56 , H02M3/00
摘要： An isolated power converter package includes a leadframe including a first and second die pad, first and second supports connected to first leads, second leads, at least one downset pad, and at least one downset feature between the supports and downset pad. A first semiconductor die is on the first die pad and a second semiconductor die is on the second die pad. The transformer stack includes a top and bottom side magnetic sheet on respective sides of a laminate substrate including an embedded coil that has coil contacts. Edges of the laminate substrate are on the supports. Bond wires are between the first die bond pads and the second leads, between the second die bond pads and the second leads, between the first die bond pads and coil contacts, and between the second die bond pads and the coil contacts. The downset pad is exposed from a mold compound.

2. 发明申请

US20230134000A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20230134000A1
公开(公告)日：2023-05-04
申请号：US17887094
申请日：2022-08-12
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Hiroaki SEKIKAWA , Yasutaka NAKASHIBA , Hideki SASAKI , Hajime HAYASHIMOTO
IPC分类号： H01L23/495 , H01L23/31 , H01L21/48 , H01L21/56
摘要： Reliability of a semiconductor device is improved. The semiconductor device includes a clip which is electrically connected to a main-transistor source pad via a first silver paste and is connected to a lead via a second silver paste. The clip has a “first part” with which the first silver paste is in contact, a “second part” with which the second silver paste is in contact, and a “third part” positioned between the “first part” and the “second part”. A protruding member is formed on a surface of the main-transistor source pad, and the “first part” is in contact with the protruding member.

3. 发明授权

US11640932B2 Packaged electronic device with film isolated power stack 有权
公开(公告)号：US11640932B2
公开(公告)日：2023-05-02
申请号：US17318974
申请日：2021-05-12
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Tianyi Luo , Jonathan Almeria Noquil , Osvaldo Jorge Lopez
IPC分类号： H01L23/495 , H01L25/07 , H01L23/31 , H01L21/48 , H01L23/00 , H01L25/00 , H01L21/56
摘要： A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

4. 发明申请

US20230131909A1 SEMICONDUCTOR PACKAGE AND METHOD FOR PRODUCING A SEMICONDUCTOR PACKAGE 有权
公开(公告)号：US20230131909A1
公开(公告)日：2023-04-27
申请号：US18045393
申请日：2022-10-10
申请人： Infineon Technologies AG
发明人： Rainald Sander , Lars Eckert , Fortunato Lopez
IPC分类号： H01L25/16 , H01L23/00 , H01L23/495
摘要： A semiconductor package comprises an encapsulation having a first lateral side and an opposite second lateral side, at least one power semiconductor chip having a drain contact region running along the first lateral side, a source contact region running along the second lateral side, and first and second inner contact regions arranged between the drain and source contact regions, a first external terminal which is connected to the drain contact region, is arranged centrally on the first lateral side, and is configured to apply a supply voltage for the at least one power semiconductor chip, a second external terminal which is connected to the source contact region, is arranged centrally on the second lateral side, and is configured to apply a reference voltage for the at least one power semiconductor chip, third and fourth external terminals which are connected to the first inner contact region. are arranged opposite each other at a first end of the first and second lateral sides, respectively, and are configured a first output of the semiconductor package, and fifth and sixth external terminals which are connected to the second inner contact region and are arranged opposite each other at a second end of the first and second lateral sides, respectively, and are configured as a second output of the semiconductor package.

5. 发明申请

US20230126663A1 LAYER STRUCTURE AND CHIP PACKAGE THAT INCLUDES THE LAYER STRUCTURE 有权
公开(公告)号：US20230126663A1
公开(公告)日：2023-04-27
申请号：US18088238
申请日：2022-12-23
申请人： Infineon Technologies AG
发明人： Alexander Heinrich , Alexander Roth , Catharina Wille
IPC分类号： H01L23/00 , B23K35/30 , B23K35/02 , H01L23/495 , H01L23/31 , H01L21/56 , B22F1/052
摘要： A layer structure includes a first layer including at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and an alloy of any of these materials; a third layer including at least one material selected from a second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and an alloy of any of these materials; and a second layer between the first layer and the third layer. The second layer consists of or essentially consists of nickel and tin. The second layer includes an intermetallic phase of nickel and tin.

6. 发明授权

US11637024B2 Method for glob top encapsulation using molding tape with elevated sidewall 有权
公开(公告)号：US11637024B2
公开(公告)日：2023-04-25
申请号：US17072569
申请日：2020-10-16
申请人： NXP B.V.
发明人： Wiwat Tanwongwan , Amornthep Saiyajitara , Nathapop Lappanitpullpol
IPC分类号： H01L21/56 , H01L23/31 , H01L23/495 , G06K19/077 , H01L23/498 , H01L21/48
摘要： A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity.

7. 发明申请

US20230123668A1 METHOD FOR FORMING A SEMICONDUCTOR PACKAGE 有权
公开(公告)号：US20230123668A1
公开(公告)日：2023-04-20
申请号：US18084577
申请日：2022-12-20
申请人： MEDIATEK INC.
发明人： You-Wei Lin , Chih-Feng Fan
IPC分类号： H01L23/495 , H01L21/56 , H01L21/78 , H01L23/31
摘要： A semiconductor package includes a die attach pad; a plurality of lead terminals disposed around the die attach pad; a semiconductor die mounted on the die attach pad; a molding compound encapsulating the plurality of lead terminals, the semiconductor die, and the die attach pad; and a step cut sawn into the molding compound along a perimeter of a bottom surface of the semiconductor package. The step cut penetrates through an entire thickness of each of the plurality of lead terminals, whereby each of the plurality of lead terminals has at least an exposed outer end at the step cut.

8. 发明申请

US20230121777A1 ELECTRONIC DEVICE 有权
公开(公告)号：US20230121777A1
公开(公告)日：2023-04-20
申请号：US17914088
申请日：2021-03-22
申请人： ROHM CO., LTD.
发明人： Yuji ISHIMATSU , Kenji HAMA , Hideo HARA
IPC分类号： H01L23/495 , H01L23/00
摘要： An electronic device includes: a substrate with obverse and reverse surfaces spaced apart in a thickness direction; an electronic element having an obverse surface formed with a first obverse surface electrode; a wiring portion on the substrate obverse surface and configured to transmit a control signal for the electronic element; a conduction member with obverse and reverse surfaces spaced apart in the thickness direction, where the reverse surface is joined to the wiring portion; a conductive first lead on the substrate obverse surface; and a first connecting member joined to the obverse surface of the conduction member and the first obverse surface electrode. The first lead includes a first pad portion spaced apart from the wiring portion and to which the electronic element is joined. The wiring portion and the first obverse surface electrode are electrically connected to each other via the conduction member and the first connecting member.

9. 发明申请

US20230119127A1 ISOLATED SEMICONDUCTOR PACKAGE WITH HV ISOLATOR ON BLOCK 有权
公开(公告)号：US20230119127A1
公开(公告)日：2023-04-20
申请号：US17502706
申请日：2021-10-15
申请人： Texas Instruments Incorporated
发明人： Vivek K. Arora , Woochan Kim
IPC分类号： H01L23/495 , H01L23/00 , H01L23/31 , H01L23/373 , H01L21/56 , H01F27/28
摘要： A power converter package includes a leadframe including first and second die pads, and supports connected to first leads, and second leads. A first semiconductor die including first bond pads is on the first die pad, and a second semiconductor die including second bond pads is on the second die pad. A transformer stack includes a top magnetic sheet and a bottom magnetic sheet on respective sides of a laminate substrate that includes a coil within, and coil contacts. A silicon block is attached to the bottom magnetic sheet and edges of the laminate substrate are attached to the supports. Bond wires are between the first bond pads and the second leads, the second bond pads and the second leads, and the first and second bond pads and the coil contacts. Mold encapsulates the respective semiconductor and the transformer stack. A bottom of the silicon block is exposed from the mold.

10. 发明申请

US20230117260A1 METHODS OF FORMING PACKAGED SEMICONDUCTOR DEVICES AND LEADFRAMES FOR SEMICONDUCTOR DEVICE PACKAGES 有权
公开(公告)号：US20230117260A1
公开(公告)日：2023-04-20
申请号：US17504284
申请日：2021-10-18
申请人： Wolfspeed, Inc.
发明人： Soon Lee Liew , Eng Wah Woo , Alexander Komposch
IPC分类号： H01L23/495 , H01L23/48 , H01L23/31
摘要： A method of forming a packaged semiconductor device according to some embodiments includes providing a leadframe blank including a first package blank, a second package blank and a tie bar between the first package blank and the second package blank, forming a recessed cavity in the tie bar, and separating the first and second package blanks by sawing through the leadframe blank along the tie bar.

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