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1. 发明专利

JP2013197540A Magnetoresistive element and method for writing magnetic memory 有权
标题翻译：用于写入磁记录的磁电元件和方法
公开(公告)号：JP2013197540A
公开(公告)日：2013-09-30
申请号：JP2012066346
申请日：2012-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAI TSUKASA , IZUMIDA TAKASHI , OSEGI JUNICHI , KONDO MASAKI , TODA TOSHIYUKI , AOKI NOBUTOSHI
IPC分类号： H01L21/8246 , G11B5/39 , H01L27/105 , H01L29/82 , H01L43/08 , H01L43/10
CPC分类号： G11C11/161 , G11C11/1675
摘要： PROBLEM TO BE SOLVED: To suppress the occurrence of an erroneous writing caused by overheating by current passage and the degradation of writing speed, by reducing writing current.SOLUTION: The magnetoresistive element includes: a first magnetic layer 11; a second magnetic layer 13; a nonmagnetic layer 12 formed between the first and second magnetic layers; a first insulating layer 14 formed between the second magnetic layer and a charge storage layer; and a second insulating layer 16 formed on a face of the charge storage layer, which is different from the face on which the first insulating layer is formed.
摘要翻译：要解决的问题：通过减少写入电流来抑制由于电流通过的过热而引起的错误写入的发生和写入速度的劣化。解决方案：磁阻元件包括：第一磁性层11; 第二磁性层13; 形成在第一和第二磁性层之间的非磁性层12; 形成在第二磁性层和电荷存储层之间的第一绝缘层14; 以及形成在电荷存储层的与形成有第一绝缘层的面不同的面上的第二绝缘层16。

2. 发明专利

JP2008257781A Data writing method of semiconductor memory device 有权
标题翻译：半导体存储器件的数据写入方法
公开(公告)号：JP2008257781A
公开(公告)日：2008-10-23
申请号：JP2007097507
申请日：2007-04-03
申请人： Toshiba Corp , 株式会社東芝
发明人： EDAHIRO TOSHIAKI , TODA TOSHIYUKI , FUTAYAMA TAKUYA
IPC分类号： G11C16/02 , G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： PROBLEM TO BE SOLVED: To provide a data writing method of a semiconductor memory device, by which high speed writing can be performed while lightening interference effect between adjacent cells. SOLUTION: In the data writing method of the semiconductor memory device having writing sequence in which writing to each target threshold level constituting multi-value data is performed for a plurality of memory cells selected simultaneously, in the writing sequence, write control is performed so that the writing is finished in the order of memory cells whose target threshold levels are high. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供半导体存储器件的数据写入方法，通过该半导体存储器件可以在减轻相邻单元之间的干扰效应的同时进行高速写入。解决方案：在具有写入顺序的半导体存储器件的数据写入方法中，在写入序列中，对于同时选择的多个存储器单元执行对构成多值数据的每个目标阈值电平的写入，写入控制是执行以使得以目标阈值电平为高的存储单元的顺序完成写入。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2005165549A Display device, simulator, simulation method and program 审中-公开
标题翻译：显示设备，模拟器，模拟方法和程序
公开(公告)号：JP2005165549A
公开(公告)日：2005-06-23
申请号：JP2003401804
申请日：2003-12-01
申请人： Toshiba Corp , 株式会社東芝
发明人： TODA TOSHIYUKI
IPC分类号： G06F17/50 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a device allowing acquisition of a user interface allowing a user to quantitatively evaluate temperature characteristics of each part of a semiconductor device.
SOLUTION: This display device has: a temperature distribution information calculation part 120 calculating temperature distribution information about internal temperature of the semiconductor device when simulation of the semiconductor device is performed; at least one of a volume value information calculation part 130 calculating total information about a volume value in a portion inside the semiconductor device corresponding to a prescribed temperature range, a heat capacity value information calculation part 140 calculating total information about a heat capacity value, and a thermal energy value information calculation part 150 calculating total information about a thermal energy value; a temperature scale display part 102 of the calculated internal temperature; and an output part 160 outputting the total information calculated by the volume value information calculation part 130, the heat capacity value information calculation part 140 or the thermal energy value information calculation part 150.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供允许获取用户界面的设备，允许用户定量评估半导体器件的每个部分的温度特性。解决方案：该显示装置具有：温度分布信息计算部120，在进行半导体装置的模拟时，计算关于半导体装置的内部温度的温度分布信息; 体积值信息计算部130中的至少一个计算与规定温度范围对应的半导体装置内部的体积值的总体信息，热容量值信息计算部140，计算热容量值的总体信息，以及热能值信息计算部150计算关于热能值的总体信息; 所计算的内部温度的温度标尺显示部分102; 以及输出部160，其输出由体积值信息计算部130，热容值信息计算部140或热能值信息计算部150计算出的总信息。（C）2005，JPO＆NCIPI

4. 发明专利

JP2008004614A Nonvolatile semiconductor storage device, and its manufacturing method 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2008004614A
公开(公告)日：2008-01-10
申请号：JP2006170121
申请日：2006-06-20
申请人： Toshiba Corp , 株式会社東芝
发明人： KITO TAKASHI , AOKI NOBUTOSHI , KITO MASARU , KATSUMATA RYUTA , KONDO MASAKI , KUSUNOKI NAOKI , TODA TOSHIYUKI , ITO SANAE , TANIMOTO KOKICHI , AOCHI HIDEAKI , NITAYAMA AKIHIRO , SHIRATA RIICHIRO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/42336
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which is superior in short channel characteristic, writing characteristic and retention, and to provide its manufacturing method.
SOLUTION: The nonvolatile semiconductor storage device is provided with a semiconductor area 10, element isolation areas 13 which are arranged in the semiconductor area 10 and is extended in the direction of column, a selective epitaxial growth layer 12 which is arranged on the semiconductor area 10 pinched by the element isolation areas 13 and of which section along the direction of row is like a projected shape, a source/drain area arranged on the selective epitaxial growth layer 12, a gate insulation film 14 which is pinched by the element isolation areas 13 and is arranged on the selective epitaxial growth layer 12 between the source/drain area, a floating gate electrode layer 15 which is pinched by the element isolation areas 13 and is arranged on the gate insulation film 14, a gate-to-gate insulation film 16 which is arranged in the floating gate electrode layer 15 and the upper surface of the element isolation areas 13, and a control gate electrode layer 17 which is arranged on the gate-to-gate insulation film 16 and is extended in the direction of row.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在短通道特性，写入特性和保持性方面优异的非易失性半导体存储装置，并提供其制造方法。解决方案：非易失性半导体存储装置设置有半导体区域10，设置在半导体区域10中并沿列方向延伸的元件隔离区域13，选择性外延生长层12布置在由元件隔离区域13夹持的半导体区域10，沿着行方向的部分类似于投影形状，布置在选择性外延生长层12上的源极/漏极区域，被元件夹持的栅极绝缘膜14 隔离区域13，并且布置在源极/漏极区域之间的选择性外延生长层12上，被元件隔离区域13夹持并布置在栅极绝缘膜14上的浮置栅极电极层15，栅极 - 布置在浮置栅极层15和元件隔离区域13的上表面中的栅极绝缘膜16和布置在栅极绝缘膜16中的控制栅电极层17 在栅极至栅极绝缘膜16上并沿行方向延伸。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2011258776A Nonvolatile semiconductor memory 审中-公开
标题翻译：非易失性半导体存储器
公开(公告)号：JP2011258776A
公开(公告)日：2011-12-22
申请号：JP2010132366
申请日：2010-06-09
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUO KOJI , TODA TOSHIYUKI , AOKI NOBUTOSHI , IINUMA TOSHIHIKO
IPC分类号： H01L27/115 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L29/788 , H01L29/792 , H01L45/00 , H01L49/00
CPC分类号： H01L29/7926 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C2213/18 , G11C2213/71 , G11C2213/75 , H01L27/11565 , H01L27/11568 , H01L27/24
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory developed based on a new concept.SOLUTION: The nonvolatile semiconductor memory comprises a semiconductor layer 12 on a semiconductor substrate 11; multiple control gates CG11-CG17 penetrating the semiconductor layer 12; two first conductive diffusion layers 14 arranged in the semiconductor layer 12 at two ends of a first direction; multiple select gate lines SG1-SG5 extending in the first direction on the semiconductor layer 12; and multiple word lines WL1-WL7 extending in a second direction on the multiple select gate lines SG1-SG5. Each of the multiple select gate lines SG1-SG5 functions as a select gate shared by multiple select transistors connected to between the multiple control gates CG11-CG17 and the multiple word lines WL1-WL7 that line up in the first direction. The semiconductor layer 12 and the multiple control gates CG11-CG17 constitute a memory cell array.
摘要翻译：要解决的问题：提供基于新概念开发的非易失性半导体存储器。解决方案：非易失性半导体存储器包括半导体衬底11上的半导体层12; 穿过半导体层12的多个控制栅极CG11-CG17; 布置在半导体层12中的两个第一导电扩散层14在第一方向的两端; 在半导体层12上沿第一方向延伸的多个选择栅极线SG1-SG5; 以及在多个选择栅极线SG1-SG5上沿第二方向延伸的多个字线WL1-WL7。多个选择栅极线SG1-SG5中的每一个用作连接到多个控制栅极CG11-CG17和在第一方向上排列的多个字线WL1-WL7之间的多个选择晶体管共享的选择栅极。半导体层12和多个控制栅极CG11-CG17构成存储单元阵列。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2007165543A Method for manufacturing semiconductor memory device 审中-公开
标题翻译：制造半导体存储器件的方法
公开(公告)号：JP2007165543A
公开(公告)日：2007-06-28
申请号：JP2005359072
申请日：2005-12-13
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , TODA TOSHIYUKI , TANIMOTO KOKICHI , KUSUNOKI NAOKI , AOKI NOBUTOSHI , SHIRATA RIICHIRO , WATANABE HIROSHI , ISHIHARA TAKAMITSU
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/76 , H01L21/762 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor memory device which reduces the number of process steps.
SOLUTION: On a first conductive semiconductor layer formed on a first conductive semiconductor substrate so as to be isolated by an insulating film by a gate pre-production process, a NAND cell unit is formed to have a memory cell formed by laminating a floating gate and a control gate, and a select gate transistor. On the semiconductor layer, a second conductive layer is formed as a channel area of the select gate transistors by selective ion implantation. Select gate lines exposed to open side walls at a bit line contact position and a source line contact position are covered with an insulating film for ion implantation, and a first conductive diffusion layer is formed for bit line contact and source line contact.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供减少处理步骤数量的半导体存储器件的制造方法。解决方案：在通过栅极预制备工艺由绝缘膜隔离形成在第一导电半导体衬底上的第一导电半导体层上，形成NAND单元，以具有通过层叠浮动栅极和控制栅极以及选择栅极晶体管。在半导体层上，通过选择性离子注入形成第二导电层作为选择栅晶体管的沟道区。选择在位线接触位置和源极线接触位置处暴露于开放侧壁的栅极线被用于离子注入的绝缘膜覆盖，并且形成用于位线接触和源极线接触的第一导电扩散层。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2006294940A Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：JP2006294940A
公开(公告)日：2006-10-26
申请号：JP2005115013
申请日：2005-04-12
申请人： Toshiba Corp , 株式会社東芝
发明人： TANIMOTO KOKICHI , TODA TOSHIYUKI , KUSUNOKI NAOKI , AOKI NOBUTOSHI , SHIRATA RIICHIRO , ARAI FUMITAKA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory wherein the high speed collective erasure of memory signals can be obtained in an NAND-type flash memory having SOI structure. SOLUTION: This nonvolatile semiconductor memory comprises a plurality of memory cell transistors MT 11 -MT 1n which are formed with channel regions 411-41n of a first conductivity type contiguous to a buried insulating layer 2 and are arranged in the column direction, a first selective gate transistor STS1 formed with a channel region 42 of a second conductivity type which is adjacent to one end of the arrangement of the memory cell transistors MT 11 -MT 1n and contiguous to the buried insulating layer 2, a source line contact region 46 of the second conductivity type which is electrically connected to the channel region 42 of the second conductivity type and has impurity density higher than that of the channel region 42, and a source line contact plug 18 which is electrically connected to a source region 43 of the first conductivity type in the first selective gate transistor STS1 and electrically connected to the source line contact region 46. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种非易失性半导体存储器，其中可以在具有SOI结构的NAND型闪速存储器中获得存储信号的高速集合擦除。解决方案：这种非易失性半导体存储器包括由第一导电类型连续的沟道区域411-41n形成的多个存储单元晶体管MT-SB 11-SB 埋入绝缘层2并沿列方向布置，第一选择栅极晶体管STS1形成有第二导电类型的沟道区42，该沟道区42与存储单元晶体管MT11的布置的一端相邻与掩埋绝缘层2邻接的第二导电类型的源极线接触区域46与第二导电类型的沟道区域42电连接，并且具有杂质浓度高于沟道区域42的源极线接触插塞18，与第一选择栅极晶体管STS1中的第一导电类型的源极区43电连接并与源极线接触区域46电连接的源极线接触插塞18。
COPYRI GHT：（C）2007，JPO＆INPIT

8. 发明专利

JP2006294711A Nonvolatile semiconductor memory device and its controlling method 审中-公开
标题翻译：非线性半导体存储器件及其控制方法
公开(公告)号：JP2006294711A
公开(公告)日：2006-10-26
申请号：JP2005110373
申请日：2005-04-06
申请人： Toshiba Corp , 株式会社東芝
发明人： TODA TOSHIYUKI , TANIMOTO KOKICHI , KUSUNOKI NAOKI , AOKI NOBUTOSHI , SHIRATA RIICHIRO , ARAI FUMITAKA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which can perform writing, reading, and erasing operations normally.
SOLUTION: The nonvolatile semiconductor memory device comprises memory cell transistors MT
11 -MT
1n which include source regions 421-42n of the same conductivity n
- -type, drain regions 422-42(n+1) of the same conductivity type, and channel regions 411-41n of the same conductivity type. All of these are formed in contact with a buried insulation layer 2 in a semiconductor layer 3 formed on the buried insulation layer 2 on a support substrate 1. The thickness T
SOI of the channel regions 411-41n is not less than 1 nm nor more than the gate length L of the memory cell transistor MT
11 -MT
1n plus 6 nm.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够正常执行写入，读取和擦除操作的非易失性半导体存储器件。解决方案：非易失性半导体存储器件包括存储单元晶体管，其包括相同电导率的源极区域421-42n n - < / SP>型，相同导电类型的漏区422-42（n + 1）以及相同导电类型的沟道区411-41n。所有这些都形成为与形成在支撑基板1上的掩埋绝缘层2上的半导体层3中的掩埋绝缘层2接触。沟道区域411-41n的厚度T SOI 不小于1nm且不大于存储单元晶体管MT <11> -MT 1n 的栅极长度L加上6nm。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2014175480A Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2014175480A
公开(公告)日：2014-09-22
申请号：JP2013046983
申请日：2013-03-08
申请人： Toshiba Corp , 株式会社東芝
发明人： TOKUHIRA KOKI , NAKAI TSUKASA , TANIMOTO KOKICHI , KONDO MASAKI , TODA TOSHIYUKI , AOKI NOBUTOSHI
IPC分类号： H01L21/336 , G11C16/02 , G11C16/04 , G11C16/06 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0466 , G11C11/22 , G11C16/0483 , H01L27/11524 , H01L29/66825
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which achieves good controllability in a first insulation layer and which can reduce a leakage current from a second insulation layer due to a large coupling ratio, and which enables writing at low voltage.SOLUTION: A nonvolatile semiconductor storage device comprises a plurality of memory cells which can store data of more than binary. The memory cell includes a semiconductor layer 1B, a first insulation layer 2B on the semiconductor layer, a charge storage layer 3B on the first insulation layer, a second insulation layer 4B on the charge storage layer and a control gate electrode 5B on the second insulation layer. The second insulation layer 4B includes a ferroelectric layer. Further, polarized alignment pulse voltage is applied to the control gate electrode 5B before being read out.
摘要翻译：要解决的问题：提供一种非易失性半导体存储装置，其在第一绝缘层中实现良好的可控性，并且由于大的耦合比而能够减少来自第二绝缘层的漏电流，并且能够以低电压进行写入。解决方案：非易失性半导体存储装置包括可存储多于二进制数据的多个存储单元。存储单元包括半导体层1B，半导体层上的第一绝缘层2B，第一绝缘层上的电荷存储层3B，电荷存储层上的第二绝缘层4B和第二绝缘层上的控制栅电极5B 层。第二绝缘层4B包括铁电层。此外，在读出之前，将极化的取向脉冲电压施加到控制栅电极5B。

10. 发明专利

JP2013197546A Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2013197546A
公开(公告)日：2013-09-30
申请号：JP2012066386
申请日：2012-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAI TSUKASA , AOKI NOBUTOSHI , IZUMIDA TAKASHI , KONDO MASAKI , TODA TOSHIYUKI
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L27/28 , H01L29/788 , H01L29/792 , H01L51/05 , H01L51/30
CPC分类号： H01L29/788 , G11C16/0466 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/66825
摘要： PROBLEM TO BE SOLVED: To provide a high-quality nonvolatile semiconductor storage device.SOLUTION: A nonvolatile semiconductor storage device comprises: a substrate 11; a laminate ML having a structure in which a plurality of first insulation layers 21 and a plurality of first electrode layers 22 are alternately stacked one by one in a first direction perpendicular to the substrate 11; a second insulation layer 32 formed along the first direction on an inner wall of a first through hole 28 which pierces the first insulation layers 21 and the first electrode layers 22; an intermediate layer 33 formed on a surface of the second insulation layer 32; a third insulation layer 34 formed on a surface of the intermediate layer 33; and a columnar first semiconductor region 36 which is formed on a surface of the third insulation layer 34 and extends along the first direction. The intermediate layer 33 includes: a charge storage region 33b at a position adjacent to the first electrode layers 22 in a second direction orthogonal to the first direction, which consists primarily of carbon; and an insulation regions 33a for electrically separating the plurality of charge storage regions 33b which are adjacent in the first direction to a position adjacent to the first insulation layer 21 in the second direction.
摘要翻译：要解决的问题：提供高质量的非易失性半导体存储装置。解决方案：非易失性半导体存储装置包括：基板11; 具有多个第一绝缘层21和多个第一电极层22在垂直于基板11的第一方向上交替堆叠的结构的层压体ML; 在穿过第一绝缘层21和第一电极层22的第一通孔28的内壁上沿着第一方向形成的第二绝缘层32; 形成在第二绝缘层32的表面上的中间层33; 形成在中间层33的表面上的第三绝缘层34; 以及形成在第三绝缘层34的表面上并沿着第一方向延伸的柱状的第一半导体区域36。中间层33包括：主要由碳组成的与第一方向正交的第二方向的与第一电极层22相邻的位置处的电荷存储区域33b; 以及绝缘区域33a，用于将在第一方向上相邻的多个电荷存储区域33b沿第二方向电分离到与第一绝缘层21相邻的位置。

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