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1. 发明专利

JP2008078674A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2008078674A
公开(公告)日：2008-04-03
申请号：JP2007269479
申请日：2007-10-16
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIRATA RIICHIRO , ICHIGE MASAYUKI , SATOU ATSUYOSHI , SUGIMAE KIKUKO , HAZAMA HIROAKI
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of reducing the capacity between a resistive element and a substrate in a peripheral circuit of a semiconductor device, especially a non-volatile semiconductor memory, such as a flash memory.
SOLUTION: A flash memory is formed in a semiconductor substrate 1, and an element isolation insulating film 2 dividing an element region, a gate oxide film 4 in an element region 3 isolated from the element isolating region 2, a first gate electrode 5 functioning as a floating gate (FG), a second gate electrode material 7 functioning as a control gate (CG: word line) of a central transistor are formed on a first insulating film 6. In the peripheral circuit section, a resistive element 7a is provided comprising the second gate electrode material via the first insulating film 6 on the element isolation insulating film 2. The impurity concentration of the semiconductor substrate 1 below the resistive element 7a is equal to or lower than that of bulk.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够降低半导体器件的外围电路中的电阻元件和衬底之间的电容的半导体存储器件，特别是诸如闪存的非易失性半导体存储器。解决方案：在半导体衬底1中形成闪存，并且将元件区域分隔开的元件隔离绝缘膜2，与元件隔离区域2隔离的元件区域3中的栅氧化膜4，第一栅电极在第一绝缘膜6上形成用作浮栅（FG）的第五绝缘膜（6），在第一绝缘膜6上形成用作中心晶体管的控制栅极（CG：字线）的第二栅电极材料7.在外围电路部分中，通过元件隔离绝缘膜2上的第一绝缘膜6提供包括第二栅电极材料。电阻元件7a下方的半导体衬底1的杂质浓度等于或低于体积。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2008004614A Nonvolatile semiconductor storage device, and its manufacturing method 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2008004614A
公开(公告)日：2008-01-10
申请号：JP2006170121
申请日：2006-06-20
申请人： Toshiba Corp , 株式会社東芝
发明人： KITO TAKASHI , AOKI NOBUTOSHI , KITO MASARU , KATSUMATA RYUTA , KONDO MASAKI , KUSUNOKI NAOKI , TODA TOSHIYUKI , ITO SANAE , TANIMOTO KOKICHI , AOCHI HIDEAKI , NITAYAMA AKIHIRO , SHIRATA RIICHIRO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/42336
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which is superior in short channel characteristic, writing characteristic and retention, and to provide its manufacturing method.
SOLUTION: The nonvolatile semiconductor storage device is provided with a semiconductor area 10, element isolation areas 13 which are arranged in the semiconductor area 10 and is extended in the direction of column, a selective epitaxial growth layer 12 which is arranged on the semiconductor area 10 pinched by the element isolation areas 13 and of which section along the direction of row is like a projected shape, a source/drain area arranged on the selective epitaxial growth layer 12, a gate insulation film 14 which is pinched by the element isolation areas 13 and is arranged on the selective epitaxial growth layer 12 between the source/drain area, a floating gate electrode layer 15 which is pinched by the element isolation areas 13 and is arranged on the gate insulation film 14, a gate-to-gate insulation film 16 which is arranged in the floating gate electrode layer 15 and the upper surface of the element isolation areas 13, and a control gate electrode layer 17 which is arranged on the gate-to-gate insulation film 16 and is extended in the direction of row.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在短通道特性，写入特性和保持性方面优异的非易失性半导体存储装置，并提供其制造方法。解决方案：非易失性半导体存储装置设置有半导体区域10，设置在半导体区域10中并沿列方向延伸的元件隔离区域13，选择性外延生长层12布置在由元件隔离区域13夹持的半导体区域10，沿着行方向的部分类似于投影形状，布置在选择性外延生长层12上的源极/漏极区域，被元件夹持的栅极绝缘膜14 隔离区域13，并且布置在源极/漏极区域之间的选择性外延生长层12上，被元件隔离区域13夹持并布置在栅极绝缘膜14上的浮置栅极电极层15，栅极 - 布置在浮置栅极层15和元件隔离区域13的上表面中的栅极绝缘膜16和布置在栅极绝缘膜16中的控制栅电极层17 在栅极至栅极绝缘膜16上并沿行方向延伸。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2007043185A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2007043185A
公开(公告)日：2007-02-15
申请号：JP2006253223
申请日：2006-09-19
申请人： Toshiba Corp , 株式会社東芝
发明人： ICHIGE MASAYUKI , SHIRATA RIICHIRO , SUGIMAE KIKUKO
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which has a main memory and a controller for controlling the main memory, and is suitable for an IC card.
SOLUTION: This device comprises a memory circuit 92 having a non-volatile memory cell array and a control circuit 91 for controlling the memory circuit 92. The control circuit 91 has a page buffer 94, and the page buffer 94 includes three transistor cell blocks.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体集成电路装置，其具有主存储器和用于控制主存储器的控制器，并且适用于IC卡。解决方案：该装置包括具有非易失性存储单元阵列的存储器电路92和用于控制存储器电路92的控制电路91.控制电路91具有页缓冲器94，并且页缓冲器94包括三个晶体管单元格块。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2007027776A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2007027776A
公开(公告)日：2007-02-01
申请号：JP2006239550
申请日：2006-09-04
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , SHIRATA RIICHIRO , SHIMIZU AKIRA , MATSUNAGA YASUHIKO , SAKUMA MAKOTO
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To resolve the problem that it is difficult to reduce the parasitic capacity of the periphery of a floating gate and and increase capacity between a control gate and the floating gate and it is difficult to reduce write voltage and carry out high integration and speeding up. SOLUTION: In a nonvolatile semiconductor memory device, a groove is formed in a semiconductor substrate 11. A floating gate FG is formed on the bottom portion of the groove via a gate insulating film GI. A diffusion layer S/D for use as a source or drain region is formed in the semiconductor substrate 11 corresponding to both sides of the floating gate FG. First and second control gates CGs for driving the floating gate FG via the insulating film between the gates IGI are formed on both side walls of the floating gate FG positioned on both diffusion layers S/Ds. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决问题：为了解决难以降低浮置栅极的周边的寄生电容并且增加控制栅极和浮置栅极之间的电容的问题，并且难以降低写入电压并携带高集成度和加速。解决方案：在非易失性半导体存储器件中，在半导体衬底11中形成沟槽。浮栅FG经由栅极绝缘膜GI形成在沟槽的底部。用作源极或漏极区域的扩散层S / D形成在对应于浮置栅极FG两侧的半导体衬底11中。在位于两个扩散层S / Ds上的浮置栅极FG的两个侧壁上形成用于通过栅极IGI之间的绝缘膜驱动浮置栅极FG的第一和第二控制栅极CG。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2005025898A Semiconductor memory device and data write method 有权
标题翻译：半导体存储器件和数据写入方法
公开(公告)号：JP2005025898A
公开(公告)日：2005-01-27
申请号：JP2003192496
申请日：2003-07-04
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKUMA MAKOTO , ARAI FUMITAKA , SHIRATA RIICHIRO , MATSUNAGA YASUHIKO
IPC分类号： G11C16/02 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/34 , H01L27/10 , H01L29/78
CPC分类号： G11C16/10
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of suppressing a fluctuation in a threshold value caused by an interference effect between proximate cells, and of preventing erroneous write. SOLUTION: A first latch 12, a second latch 13, a comparator circuit 11, a bit-line driving circuit 2, a word-line driving circuit 4, a column decoder 3, a word control circuit 4, a row decoder 4 and an address buffer 6 constitute a first write means, second write means, and a threshold value voltage control means. The "first write means" writes data in a first memory column selected from memory cell columns C 2j-1 , C 2j , C 2j+1 , etc., The "second write means" writes data in a second memory column adjacent to the first memory column after the write in the first memory column. The "threshold value voltage control means" controls voltage in which the threshold voltage of a memory cell transistor belonging to the first memory column fluctuates by the amount of the charge of a memory cell transistor belonging to the second memory column. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供能够抑制由邻近单元之间的干扰效应引起的阈值波动并防止错误写入的半导体存储器件。解决方案：第一锁存器12，第二锁存器13，比较器电路11，位线驱动电路2，字线驱动电路4，列解码器3，字控制电路4，行译码器 4和地址缓冲器6构成第一写入装置，第二写入装置和阈值电压控制装置。 “第一写入装置”将数据写入选自存储单元列C 2j-1 ，C 2j ，C 2j + 1 等等。在第一存储器列中的写入之后，“第二写入装置”将数据写入与第一存储器列相邻的第二存储器列。 “阈值电压控制装置”控制属于第一存储器列的存储单元晶体管的阈值电压波动属于第二存储器列的存储单元晶体管的电荷的电压。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2003060093A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2003060093A
公开(公告)日：2003-02-28
申请号：JP2001247401
申请日：2001-08-16
申请人： Toshiba Corp , 株式会社東芝
发明人： ICHIGE MASAYUKI , SHIRATA RIICHIRO , MORI SEIICHI , SUGIMAE KIKUKO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory scalable for fine working and reducing power consumption. SOLUTION: The semiconductor memory is provided with a semiconductor substrate, an element region arranged on an upper part of the semiconductor substrate, an element isolation region arranged between the adjacent element regions, one or more electrically rewritable memory cell transistors arranged in the element region, and two selective transistors holding the memory cell transistor there between arranged in the element region. Also, data inside the memory cell transistor are periodically refreshed.
摘要翻译：要解决的问题：提供可精细加工并降低功耗的可扩展的半导体存储器。解决方案：半导体存储器设置有半导体衬底，布置在半导体衬底的上部的元件区域，布置在相邻元件区域之间的元件隔离区域，布置在元件区域中的一个或多个可重写存储单元晶体管，并且在元件区域中布置有存储单元晶体管的两个选择性晶体管。此外，存储单元晶体管内部的数据被周期性刷新。

7. 发明专利

JP2009278119A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009278119A
公开(公告)日：2009-11-26
申请号：JP2009160810
申请日：2009-07-07
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUI NORIHARU , MORI SEIICHI , SHIRATA RIICHIRO , TAKEUCHI YUJI , KAMIGAICHI TAKESHI
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device wherein the resistance delay in a selective gate region and a peripheral circuit region is avoided while miniaturizing a memory cell array region. SOLUTION: The semiconductor device includes: a first insulating film 12 formed on a semiconductor layer; a first electrode layer 13; a plurality of element isolation regions 15 which are formed to extend up to the inside of the semiconductor layer through the first electrode layer 13 and the first insulating film 12 and are self-aligned with the first electrode layer 13 and separate element regions and comprise an element isolating insulating film; a second insulating film 16 which is formed on the first electrode layer 13 across the element isolation regions 15 and includes an open portion through which a surface of the first electrode layer 13 is exposed; a second electrode layer 18 which is formed on the second insulating film 16 and the exposed surface of the first electrode layer 13 and is electrically connected to the first electrode layer 13 via the open portion and includes a lower resistance than the first electrode layer 13; and a contact hole 20 and upper layer wiring 21 which are located above the element isolation regions 15 and are electrically connected to the second electrode layer 18. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种在小型化存储单元阵列区域的同时避免选择栅极区域和外围电路区域中的电阻延迟的半导体器件。解决方案：半导体器件包括：形成在半导体层上的第一绝缘膜12; 第一电极层13; 多个元件隔离区域15，其形成为通过第一电极层13和第一绝缘膜12延伸到半导体层的内部，并且与第一电极层13和分离的元件区域自对准，并且包括元件隔离绝缘膜; 第二绝缘膜16，其跨过元件隔离区域15形成在第一电极层13上，并且包括第一电极层13的表面露出的开口部分; 形成在第二绝缘膜16上的第二电极层18和第一电极层13的暴露表面，并且经由开口部分电连接到第一电极层13，并且包括比第一电极层13更低的电阻; 以及位于元件隔离区域15上方并与第二电极层18电连接的接触孔20和上层布线21.权利要求（C）2010，JPO＆INPIT

8. 发明专利

JP2007207993A Non-volatile semiconductor storage device and method of manufacturing same 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：JP2007207993A
公开(公告)日：2007-08-16
申请号：JP2006024884
申请日：2006-02-01
申请人： Toshiba Corp , 株式会社東芝
发明人： KINOSHITA ATSUHIRO , SHIRATA RIICHIRO , WATANABE HIROSHI , MUROOKA KENICHI , KOGA JUNJI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11556 , H01L27/11568
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device in which an occupied area of a memory cell is reduced.
SOLUTION: The non-volatile semiconductor device is provided with: a semiconductor substrate; a plurality of semiconductor columns arrayed into a matrix shape on the semiconductor substrate; a plurality of first conduction regions formed into a belt shape in a row direction on the semiconductor substrate between the semiconductor columns so as to function as a word line; a plurality of second conduction regions respectively formed at each top of the semiconductor columns; a plurality of bit lines connecting the second conduction regions in a line direction; a plurality of channel regions respectively formed between the first/second conduction regions of the semiconductor column so as to be in contact with the first/second conduction regions; a plurality of third conduction regions insulatingly and continuously formed in the row direction between the semiconductor columns at the upper part of the semiconductor substrate while being arranged oppositely to the channel regions so as to function as a control gate; and a plurality of charge build-up regions respectively insulatingly formed at the upper part of the channel regions in a position higher than the third conduction regions.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种其中存储单元的占用面积减小的非易失性半导体存储装置。解决方案：非易失性半导体器件设置有：半导体衬底; 在半导体衬底上排列成矩阵形状的多个半导体柱; 多个第一导电区域，在半导体柱之间的半导体衬底上沿行方向形成带状，以起到字线的作用; 分别形成在所述半导体柱的每个顶部的多个第二导电区域; 在线方向上连接所述第二导电区域的多个位线; 分别形成在所述半导体柱的所述第一/第二导电区域之间以与所述第一/第二导电区域接触的多个沟道区域; 在所述半导体衬底的上部的所述半导体柱之间的行方向上绝缘地且连续地形成多个第三导电区域，同时与所述沟道区域相对布置以用作控制栅极; 以及分别绝缘地形成在高于第三导电区域的位置处的沟道区的上部的多个电荷积聚区。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2007180389A Semiconductor memory device, and method of manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2007180389A
公开(公告)日：2007-07-12
申请号：JP2005379017
申请日：2005-12-28
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , SHIRATA RIICHIRO , MIZUKAMI MAKOTO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/4234 , H01L29/66833 , H01L29/7926
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device having a NAND cell unit in which a vertical memory cells are vertically stacked, and to provide a method of manufacturing the same. SOLUTION: The semiconductor memory device is provided with a semiconductor substrate; a plurality of gate wiring stacks formed so that a plurality of layers of gate wiring arrayed with an oblong pattern in one direction on the substrate are stacked so as to be separately from each other by an insulation film, and having a side surface in which the gate wirings and the insulation films are alternately exposed; a gate insulation film including an insulative charge accumulating layer formed on the surface of each of the gate wiring stacks in its inside; a plurality of pillar-like semiconductors opposite to the side surface of each of the gate wiring stacks via the gate insulation film, and arranged with a predetermined pitch in the longitudinal direction of the gate wiring; and a data line contacting the upper surface of each of the pillar-like semiconductors and formed so as to be orthogonal to the gate wiring. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有垂直存储单元垂直堆叠的NAND单元单元的半导体存储器件，并提供其制造方法。解决方案：半导体存储器件设置有半导体衬底; 形成多个栅极布线堆叠，使得在基板上沿一个方向排列有长方形图形的多个栅极布线层被层叠，以便通过绝缘膜彼此分开，并且具有侧表面，其中，栅极布线和绝缘膜交替暴露; 栅极绝缘膜，包括在其内部的每个栅极布线堆叠的表面上形成的绝缘电荷累积层; 多个柱状半导体，经由栅极绝缘膜与每个栅极布线层的侧表面相对，并且在栅极布线的纵向方向上以预定的间距布置; 以及与柱状半导体的上表面接触并与栅极布线正交地形成的数据线。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2006059532A Nonvolatile semiconductor memory device and data erasing method of the same 有权
标题翻译：非易失性半导体存储器件及其数据擦除方法
公开(公告)号：JP2006059532A
公开(公告)日：2006-03-02
申请号：JP2005327555
申请日：2005-11-11
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIRATA RIICHIRO , ARAI FUMITAKA , FUJIMURA SUSUMU , TANAKA TOMOHARU
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device, in which an over-erased condition is not left after batch erasing, and memory cells are put into an erasing condition having a desired threshold-value range to prevent malfunction. SOLUTION: The nonvolatile semiconductor memory device has a memory cell array 1 using electrically rewritable NAND cells, a column decoder 4, a bit line control circuit 2, a word line control circuit 6, and a data input/output buffer 4, wherein previous writing and confirmation reading are performed after batch erasing of data to put erased memory cells into a desired threshold-value range. Erasing condition determination using output of the confirmation reading is performed by using a column scan determination circuit 9 that scans the output of the confirmation reading and a circuit 7 for generating a control signal and control voltage, and the previous writing is finished when determining a fact that threshold values of at least two memory cells reaches a predetermined threshold value. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种非易失性半导体存储器件，其中在批量擦除之后不留下过擦除状态，并且存储器单元被置于具有期望阈值范围的擦除状态以防止故障。解决方案：非易失性半导体存储器件具有使用电可重写NAND单元的存储单元阵列1，列解码器4，位线控制电路2，字线控制电路6和数据输入/输出缓冲器4，其中在批量擦除数据之后执行先前的写入和确认读取，以将擦除的存储器单元放入期望的阈值范围。通过使用扫描确认读取的输出的列扫描确定电路9和用于产生控制信号和控制电压的电路7执行使用确认读取的输出的擦除条件确定，并且在确定事实时完成先前的写入至少两个存储单元的阈值达到预定阈值。版权所有（C）2006，JPO＆NCIPI

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