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1. 发明专利

JP2013197215A Magnetic memory device 审中-公开
标题翻译：磁记忆装置
公开(公告)号：JP2013197215A
公开(公告)日：2013-09-30
申请号：JP2012061174
申请日：2012-03-16
申请人： Toshiba Corp , 株式会社東芝
发明人： OSEGI JUNICHI , AOKI NOBUTOSHI
IPC分类号： H01L21/8246 , H01L27/105 , H01L29/82 , H01L43/08
CPC分类号： G11C11/161 , G11C11/1659
摘要： PROBLEM TO BE SOLVED: To cancel a leakage magnetic field from the reference layer of a magnetoresistance effect element, and to enhance thermal stability by reducing an inversion current level required for writing.SOLUTION: The magnetic memory device includes a magnetoresistance effect element 30 having a ferromagnetic memory layer 32 the direction of magnetization of which is changed by a spin polarization current, and a ferromagnetic reference layer 34 having a fixed direction of magnetization, where the resistance of the magnetoresistance effect element 30 is changed by the magnetization state of the memory layer 32, and a selection transistor 10 connected with the magnetoresistance effect element 30. The gate electrode 16 of the selection transistor 10 has a ferromagnetic layer at least partially, and is magnetized in a direction opposite from the reference layer 34.
摘要翻译：要解决的问题：消除来自磁阻效应元件的参考层的泄漏磁场，并通过降低写入所需的反转电流电平来提高热稳定性。解决方案：磁存储器件包括具有铁磁存储层32的磁化方向由自旋极化电流改变，铁磁参考层34具有固定的磁化方向，其中磁阻效应元件30的电阻由存储层的磁化状态改变 32，以及与磁阻效应元件30连接的选择晶体管10.选择晶体管10的栅电极16至少部分地具有铁磁层，并且在与参考层34相反的方向上被磁化。

2. 发明专利

JP2013069734A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013069734A
公开(公告)日：2013-04-18
申请号：JP2011205452
申请日：2011-09-21
申请人： Toshiba Corp , 株式会社東芝
发明人： IZUMIDA TAKASHI , AOKI NOBUTOSHI
IPC分类号： H01L21/336 , H01L21/28 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/28061 , H01L27/10876 , H01L29/4236 , H01L29/42368 , H01L29/66621
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can inhibit a short channel effect and an off-leak current.SOLUTION: A semiconductor device of an embodiment comprises: an element region partitioned by element isolation regions on a semiconductor substrate; and a source region and a drain region formed in a surface layer of the element region, which are isolated by a gate trench provided in the surface layer of the element region along a predetermined direction crossing the element region. Further, the semiconductor device of the embodiment comprises a gate electrode at least a part of which is buried in the gate trench via a gate insulation film and formed to a depth deeper than the source region and the drain region. A boundary face contacting the gate insulation film in the drain region includes a salient protruding on the gate electrode side.
摘要翻译：解决的问题：提供一种抑制短路效应和漏电流的半导体装置。解决方案：一个实施例的半导体器件包括：由半导体衬底上的元件隔离区分隔的元件区域; 以及源极区域和漏极区域，形成在元件区域的表面层中，所述源极区域和漏极区域沿着与元件区域交叉的预定方向设置在元件区域的表面层中的栅极沟槽隔离。此外，本实施例的半导体器件包括栅极电极，其至少一部分经由栅极绝缘膜被掩埋在栅极沟槽中，并且形成为比源极区域和漏极区域更深的深度。与漏极区域中的栅极绝缘膜接触的边界面包括在栅电极侧突出的突出部。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2010123684A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2010123684A
公开(公告)日：2010-06-03
申请号：JP2008294786
申请日：2008-11-18
申请人： Toshiba Corp , 株式会社東芝
发明人： IZUMIDA TAKASHI , AOKI NOBUTOSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/0688 , H01L27/11578 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a charge trap type nonvolatile semiconductor memory device in which a memory cell transistor and a select transistor having gate electrodes differing in work function from each other can be constituted.
SOLUTION: The nonvolatile semiconductor memory device includes: a semiconductor substrate 10 which has diffusion regions 21, provided apart from one another and each forming a source or drain, on a surface; the memory cell transistor 5, which sequentially has a gate insulating film 18 having a tunnel insulating film 13, a charge storage insulating film 14, and a blocking insulating film 15, and also has a gate electrode 19 having a silicide film 17a with a width L1 arranged on the gate insulating film 18, on the surface of the semiconductor substrate 10 between the diffusion regions 21; and the select transistor 6, which has a gate insulating film 28 arranged on the surface of the semiconductor substrate 10 between the diffusion regions 21 and also has a gate electrode 29 sequentially having a polysilicon film 16a with a width L2 larger than the first width and a silicide film 17a, arranged on the gate insulating film 28.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决方案的问题：为了提供一种电荷阱型非易失性半导体存储器件，其中可以构成存储单元晶体管和具有彼此功函数不同的栅电极的选择晶体管。解决方案：非易失性半导体存储器件包括：半导体衬底10，其具有在表面上彼此分开设置并各自形成源极或漏极的扩散区域21; 存储单元晶体管5依次具有具有隧道绝缘膜13的栅极绝缘膜18，电荷存储绝缘膜14和阻挡绝缘膜15，并且还具有栅极电极19，栅极电极19具有宽度为 L1，布置在栅极绝缘膜18上，在半导体衬底10的表面上，在扩散区21之间; 以及选择晶体管6，其具有配置在扩散区域21之间的半导体衬底10的表面上的栅极绝缘膜28，并且还具有依次具有宽度L2大于第一宽度的多晶硅膜16a的栅电极29，以及设置在栅极绝缘膜28上的硅化物膜17a。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2009094313A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2009094313A
公开(公告)日：2009-04-30
申请号：JP2007263985
申请日：2007-10-10
申请人： Toshiba Corp , 株式会社東芝
发明人： AOKI NOBUTOSHI , IZUMIDA TAKASHI , KONDO MASAKI , ARAI FUMITAKA
IPC分类号： H01L21/8247 , H01L21/76 , H01L21/762 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11529 , H01L27/11524 , H01L27/11526
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which the depth of an element isolation region is adjusted for each of different element formation regions such as a contact region, selective gate region, and memory cell region, for easy embedding of an insulating film for each element isolation region, resulting in improved reliability in electrical characteristics of element isolation regions.
SOLUTION: The semiconductor memory device includes a semiconductor substrate having a contact region, selective gate region, and memory cell region, a first element isolation region which has a first width and a first depth and is provided in the contact region, a second element isolation region which has a second width and a second depth and is provided in the selective gate region, and a third element isolation region which has a third width and a third depth being shallower than the first depth and the second depth in the memory cell region.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储器件，其中针对接触区域，选择栅极区域和存储单元区域等不同元件形成区域中的每个元件隔离区域的深度进行调整，以便于嵌入的每个元件隔离区域的绝缘膜，从而提高元件隔离区域的电气特性的可靠性。解决方案：半导体存储器件包括具有接触区域，选择栅极区域和存储单元区域的半导体衬底，具有第一宽度和第一深度并设置在接触区域中的第一元件隔离区域，具有第二宽度和第二深度并且设置在选择栅极区域中的第二元件隔离区域和具有比第一深度浅的第三宽度和第三深度以及存储器中的第二深度的第三元件隔离区域细胞区域。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008258462A Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2008258462A
公开(公告)日：2008-10-23
申请号：JP2007100124
申请日：2007-04-06
申请人： Toshiba Corp , 株式会社東芝
发明人： KONDO MASAKI , IZUMIDA TAKASHI , AOKI NOBUTOSHI , WATANABE TOSHIHARU
IPC分类号： H01L21/8247 , G11C16/02 , G11C16/04 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To suppress the miswriting to a memory cell adjacent to a selection transistor. SOLUTION: This nonvolatile semiconductor storage device comprises a memory cell column wherein a plurality of memory cells MC each having a structure wherein a floating gate 13 and a control gate 15 being laminated on a silicon substrate 11 via an insulating film 12 are connected in series, and the selection transistors ST1 and ST2 connected between both ends of this memory cell column and the common source line and the bit line BL respectively. A recess 19 is formed in the surface of the silicon substrate between the selection transistor ST1 and the memory cell MC0 adjacent thereto, and the edge of the recess 19 on the selection transistor ST1 side is contiguous to the end portion of the selection transistor ST1 on the memory cell MC0 side. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：抑制与选择晶体管相邻的存储单元的错误写入。解决方案：该非易失性半导体存储装置包括存储单元列，其中多个存储单元MC具有通过绝缘膜12层压在硅基板11上的浮栅13和控制栅15的结构并且分别连接在该存储单元列的两端和公共源极线和位线BL之间的选择晶体管ST1和ST2。在选择晶体管ST1和与其相邻的存储单元MC0之间的硅衬底的表面中形成有凹槽19，并且选择晶体管ST1侧的凹部19的边缘与选择晶体管ST1的端部相邻存储单元MC0侧。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2008084975A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008084975A
公开(公告)日：2008-04-10
申请号：JP2006261238
申请日：2006-09-26
申请人： Toshiba Corp , 株式会社東芝
发明人： AOKI NOBUTOSHI , AKAHORI HIROSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/115 , H01L27/11521
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which suppresses the generation of a bird's beak in a floating gate, and its manufacturing method.
SOLUTION: The semiconductor device is equipped with a semiconductor substrate 2; element separating structures 8 formed in a groove formed on the semiconductor substrate 2 through a semiconductor oxide film 7; a floating gate 4 formed on the semiconductor substrate 2 between the element separating structures 8 through an insulating film 3; a gate oxidation preventing film 6 formed on the side surface of the element separating structure 8 for the floating gate 4 so that a part of the side surface and a bottom surface are contacted with the insulating film 3; a control gate 10 formed on the floating gate 4 through the intergate insulating film 9.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供抑制在浮动门中产生鸟嘴的半导体器件及其制造方法。解决方案：半导体器件配备有半导体衬底2; 通过半导体氧化膜7形成在形成在半导体衬底2上的沟槽中的元件分离结构8; 通过绝缘膜3形成在元件分离结构8之间的半导体衬底2上的浮栅4; 形成在浮动栅极4的元件分离结构8的侧面上的栅极氧化防止膜6，使得侧面的一部分和底面与绝缘膜3接触; 通过隔间绝缘膜9形成在浮动栅极4上的控制栅极10.版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2007329366A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2007329366A
公开(公告)日：2007-12-20
申请号：JP2006160500
申请日：2006-06-09
申请人： Toshiba Corp , 株式会社東芝
发明人： TANIMOTO KOKICHI , TODA TOSHIYUKI , AOKI NOBUTOSHI , SHIRATA RIICHIRO , ARAI FUMITAKA , MIZUKAMI MAKOTO , MIYANO KIYOTAKA , MIZUSHIMA ICHIRO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device including a NAND cell unit formed on a partial SOI substrate.
SOLUTION: The semiconductor memory device comprises a semiconductor substrate 1, a semiconductor layer 3 formed on the semiconductor substrate 1 separated from the semiconductor substrate 1 via an insulating film 2, and the NAND cell unit formed on the semiconductor layer 3 and including a plurality of series connected electrically rewritable nonvolatile memory cells. The insulating film 2 has openings 4 at positions corresponding to a source region and a drain region of the memory cell in the NAND cell unit, and the semiconductor layer 3 makes contact with the semiconductor substrate 1 via the openings 4.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种包括形成在部分SOI衬底上的NAND单元单元的半导体存储器件。解决方案：半导体存储器件包括半导体衬底1，形成在半导体衬底1上的半导体层3，半导体衬底1经由绝缘膜2与半导体衬底1分离，并且形成在半导体层3上的NAND单元单元包括多个串联连接的电可重写非易失性存储单元。绝缘膜2在对应于NAND单元单元中的存储单元的源极区域和漏极区域的位置处具有开口4，并且半导体层3经由开口4与半导体衬底1接触。版权所有：（C）2008，JPO＆INPIT

8. 发明专利

JP2014165427A Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2014165427A
公开(公告)日：2014-09-08
申请号：JP2013036948
申请日：2013-02-27
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAI TSUKASA , KONDO MASAKI , TANIMOTO KOKICHI , AOKI NOBUTOSHI
IPC分类号： H01L27/105 , H01L45/00
CPC分类号： H01L45/06 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/72 , G11C2213/73 , G11C2213/74 , G11C2213/79 , H01L27/2409 , H01L27/2481 , H01L45/12 , H01L45/126 , H01L45/144
摘要： PROBLEM TO BE SOLVED: To achieve a multi-value memory which has a high recording density and a high ON/OFF ratio, and allows a low current operation, and which is excellent in rewriting durability and data retention characteristics.SOLUTION: A nonvolatile semiconductor device according to an embodiment comprises memory cells capable of storing data of at least binary, in which the memory cell includes a structure in which a first electrode layer, a first semiconductor layer, a phase change film layer, an electrical insulator layer, a second semiconductor layer and a second electrode layer are arranged in this order. Polarities of carriers in the first electrode layer and the second electrode layer are different from each other.
摘要翻译：要解决的问题：实现具有高记录密度和高ON / OFF比率的多值存储器，并且允许低电流操作，并且具有优异的重写耐久性和数据保持特性。解决方案：非易失性半导体根据实施例的装置包括能够存储至少二进制数据的存储器单元，其中存储单元包括其中第一电极层，第一半导体层，相变膜层，电绝缘层，第二层半导体层和第二电极层按此顺序排列。第一电极层和第二电极层中的载流子的极性彼此不同。

9. 发明专利

JP2014063883A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2014063883A
公开(公告)日：2014-04-10
申请号：JP2012208265
申请日：2012-09-21
申请人： Toshiba Corp , 株式会社東芝
发明人： AOKI NOBUTOSHI , KONDO MASAKI , IZUMIDA TAKASHI
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , G11C16/0441 , H01L21/28273 , H01L21/28282 , H01L27/11524 , H01L27/1157 , H01L29/7883
摘要： PROBLEM TO BE SOLVED: To improve writing characteristics and erasing characteristics while ensuring charge-holding characteristics.SOLUTION: A semiconductor memory device includes: a first insulating film formed on a substrate and functioning as an FN (Fowler-Nordheim) tunnel film; a first floating gate formed on the first insulating film; an inter-electrode insulating layer formed on the first floating gate and functioning as an FN tunnel film; a second floating gate formed on the inter-electrode insulating layer; a second insulating film formed on the second floating gate; and a control gate formed on the second insulating film. The inter-electrode insulating layer includes a third insulating film and a fourth insulating film having charge trapping properties that are stacked.
摘要翻译：要解决的问题：提高写入特性和擦除特性，同时确保电荷保持特性。解决方案：半导体存储器件包括：形成在基板上并用作FN（Fowler-Nordheim）隧道膜的第一绝缘膜; 形成在第一绝缘膜上的第一浮栅; 形成在第一浮栅上并用作FN隧道膜的电极间绝缘层; 形成在所述电极间绝缘层上的第二浮栅; 形成在第二浮栅上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制栅极。电极间绝缘层包括第三绝缘膜和层叠有电荷捕获性的第四绝缘膜。

10. 发明专利

JP2013115329A Nonvolatile semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2013115329A
公开(公告)日：2013-06-10
申请号：JP2011261995
申请日：2011-11-30
申请人： Toshiba Corp , 株式会社東芝
发明人： KUSAKA TOMOMI , KONDO MASAKI , AOKI NOBUTOSHI , IZUMIDA TAKASHI
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/788 , H01L21/28273 , H01L27/11521 , H01L29/4916 , H01L29/66825 , H01L29/7883
摘要： PROBLEM TO BE SOLVED: To improve both characteristics of writing operation and erasing operation.SOLUTION: A nonvolatile semiconductor memory device includes: a semiconductor substrate 11; a gate insulating film 12 that is formed on the semiconductor substrate; a floating gate electrode 13 that is formed on the gate insulating film, is composed of polysilicon containing a p-type impurity that is a group 13 element, and has a lower film 13a and an upper film 13b stacked on the lower film; an inter-electrode insulating film 16 that is formed on the floating gate electrode; and a control gate electrode 17 that is formed on the inter-electrode insulating film. The impurity concentration or the activation concentration of the p-type impurity in the upper film is higher than the impurity concentration or the activation concentration of the p-type impurity in the lower film.
摘要翻译：要解决的问题：提高写入操作和擦除操作的特性。解决方案：非易失性半导体存储器件包括：半导体衬底11; 形成在半导体基板上的栅极绝缘膜12; 形成在栅极绝缘膜上的浮栅电极13由包含作为13族元素的p型杂质的多晶硅构成，并且具有层叠在下膜上的下膜13a和上膜13b; 形成在浮栅上的电极间绝缘膜16; 以及形成在电极间绝缘膜上的控制栅电极17。上层膜中p型杂质的杂质浓度或活化浓度高于下层膜中p型杂质的杂质浓度或活化浓度。版权所有（C）2013，JPO＆INPIT

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