专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2014175480A Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2014175480A
公开(公告)日：2014-09-22
申请号：JP2013046983
申请日：2013-03-08
申请人： Toshiba Corp , 株式会社東芝
发明人： TOKUHIRA KOKI , NAKAI TSUKASA , TANIMOTO KOKICHI , KONDO MASAKI , TODA TOSHIYUKI , AOKI NOBUTOSHI
IPC分类号： H01L21/336 , G11C16/02 , G11C16/04 , G11C16/06 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0466 , G11C11/22 , G11C16/0483 , H01L27/11524 , H01L29/66825
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which achieves good controllability in a first insulation layer and which can reduce a leakage current from a second insulation layer due to a large coupling ratio, and which enables writing at low voltage.SOLUTION: A nonvolatile semiconductor storage device comprises a plurality of memory cells which can store data of more than binary. The memory cell includes a semiconductor layer 1B, a first insulation layer 2B on the semiconductor layer, a charge storage layer 3B on the first insulation layer, a second insulation layer 4B on the charge storage layer and a control gate electrode 5B on the second insulation layer. The second insulation layer 4B includes a ferroelectric layer. Further, polarized alignment pulse voltage is applied to the control gate electrode 5B before being read out.
摘要翻译：要解决的问题：提供一种非易失性半导体存储装置，其在第一绝缘层中实现良好的可控性，并且由于大的耦合比而能够减少来自第二绝缘层的漏电流，并且能够以低电压进行写入。解决方案：非易失性半导体存储装置包括可存储多于二进制数据的多个存储单元。存储单元包括半导体层1B，半导体层上的第一绝缘层2B，第一绝缘层上的电荷存储层3B，电荷存储层上的第二绝缘层4B和第二绝缘层上的控制栅电极5B 层。第二绝缘层4B包括铁电层。此外，在读出之前，将极化的取向脉冲电压施加到控制栅电极5B。

2. 发明专利

JP2014165372A Nonvolatile semiconductor storage device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2014165372A
公开(公告)日：2014-09-08
申请号：JP2013035909
申请日：2013-02-26
申请人： Toshiba Corp , 株式会社東芝
发明人： IZUMIDA TAKASHI , KONDO MASAKI , AKAHORI HIROSHI , AOKI NOBUTOSHI
IPC分类号： H01L27/115 , G11C16/04 , H01L21/336 , H01L21/76 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L29/045 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which improves data retention characteristics and enables high-speed data writing.SOLUTION: According to the present embodiment, a nonvolatile semiconductor storage device comprises: a silicon substrate having an active region isolated by an element isolation insulation film; a tunnel insulation film formed on the active region; a floating gate formed on the tunnel insulation film; an inter-gate insulation film formed on the floating gate; and a control gate formed on the inter-gate insulation film. A plane orientation of a plane of the active region, which contacts the element isolation insulation film, is (100).
摘要翻译：要解决的问题：提供一种提高数据保持特性并实现高速数据写入的非易失性半导体存储装置。解决方案：根据本实施例，非易失性半导体存储装置包括：具有由元件隔离绝缘膜; 形成在有源区上的隧道绝缘膜; 形成在隧道绝缘膜上的浮动栅; 形成在浮动栅极上的栅极间绝缘膜; 以及形成在栅极间绝缘膜上的控制栅极。与元件隔离绝缘膜接触的有源区域的平面的平面取向为（100）。

3. 发明专利

JP2013197546A Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2013197546A
公开(公告)日：2013-09-30
申请号：JP2012066386
申请日：2012-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAI TSUKASA , AOKI NOBUTOSHI , IZUMIDA TAKASHI , KONDO MASAKI , TODA TOSHIYUKI
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L27/28 , H01L29/788 , H01L29/792 , H01L51/05 , H01L51/30
CPC分类号： H01L29/788 , G11C16/0466 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/66825
摘要： PROBLEM TO BE SOLVED: To provide a high-quality nonvolatile semiconductor storage device.SOLUTION: A nonvolatile semiconductor storage device comprises: a substrate 11; a laminate ML having a structure in which a plurality of first insulation layers 21 and a plurality of first electrode layers 22 are alternately stacked one by one in a first direction perpendicular to the substrate 11; a second insulation layer 32 formed along the first direction on an inner wall of a first through hole 28 which pierces the first insulation layers 21 and the first electrode layers 22; an intermediate layer 33 formed on a surface of the second insulation layer 32; a third insulation layer 34 formed on a surface of the intermediate layer 33; and a columnar first semiconductor region 36 which is formed on a surface of the third insulation layer 34 and extends along the first direction. The intermediate layer 33 includes: a charge storage region 33b at a position adjacent to the first electrode layers 22 in a second direction orthogonal to the first direction, which consists primarily of carbon; and an insulation regions 33a for electrically separating the plurality of charge storage regions 33b which are adjacent in the first direction to a position adjacent to the first insulation layer 21 in the second direction.
摘要翻译：要解决的问题：提供高质量的非易失性半导体存储装置。解决方案：非易失性半导体存储装置包括：基板11; 具有多个第一绝缘层21和多个第一电极层22在垂直于基板11的第一方向上交替堆叠的结构的层压体ML; 在穿过第一绝缘层21和第一电极层22的第一通孔28的内壁上沿着第一方向形成的第二绝缘层32; 形成在第二绝缘层32的表面上的中间层33; 形成在中间层33的表面上的第三绝缘层34; 以及形成在第三绝缘层34的表面上并沿着第一方向延伸的柱状的第一半导体区域36。中间层33包括：主要由碳组成的与第一方向正交的第二方向的与第一电极层22相邻的位置处的电荷存储区域33b; 以及绝缘区域33a，用于将在第一方向上相邻的多个电荷存储区域33b沿第二方向电分离到与第一绝缘层21相邻的位置。

4. 发明专利

JP2011114034A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2011114034A
公开(公告)日：2011-06-09
申请号：JP2009266591
申请日：2009-11-24
申请人： Toshiba Corp , 株式会社東芝
发明人： IZUMIDA TAKASHI , KUSAKA TOMOMI , KONDO MASAKI , AOKI NOBUTOSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , G11C16/0408 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11531 , H01L29/42332 , H01L29/7887
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which miniaturizes each memory cell while suppressing degradation of a characteristic of the semiconductor memory device.
SOLUTION: The semiconductor memory device includes: a substrate 101; gate insulating films 111 formed on the substrate and each functioning as an FN (Fowler-Nordheim) tunneling film; first floating gates 112 formed on the gate insulating films; first inter-gate insulating films 113 formed on the first floating gates and each functioning as an FN tunneling film; second floating gates 114 formed on the first inter-gate insulating films; a second inter-gate insulating film 115 formed on the second floating gates and functioning as a charge blocking film; and a control gate 116 formed on the second inter-gate insulating film.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种能够抑制半导体存储装置的特性劣化的各存储单元的小型化的半导体存储装置。解决方案：半导体存储器件包括：衬底101; 栅极绝缘膜111，其形成在基板上并且各自用作FN（Fowler-Nordheim）隧穿膜; 形成在栅绝缘膜上的第一浮栅112; 第一栅极绝缘膜113，其形成在第一浮栅上并且各自用作FN隧道膜; 形成在第一栅极间绝缘膜上的第二浮栅114; 形成在第二浮动栅极上并用作电荷阻挡膜的第二栅极间绝缘膜115; 以及形成在第二栅极间绝缘膜上的控制栅极116。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2011035268A Semiconductor memory device, and method of manufacturing the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2011035268A
公开(公告)日：2011-02-17
申请号：JP2009181798
申请日：2009-08-04
申请人： Toshiba Corp , 株式会社東芝
发明人： KONDO MASAKI , ISOBE KAZUAKI
IPC分类号： H01L29/792 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device that increases the coupling ratio of a control gate to a floating gate without increasing a chip size, and to provide a method of manufacturing the same.
SOLUTION: The semiconductor memory device includes: a plurality of active areas formed on the surface of a semiconductor substrate; an element isolation part provided between the adjacent active areas; a tunnel insulating film provided on the active areas; a floating gate including a lower gate part which is opposed to each active area through the tunnel insulating film and an upper gate part having a width larger than that of the lower gate part and provided on the lower gate part; an intermediate insulating film provided on the upper surface and the side face of the floating gate; and a control gate provided on the upper surface and the side face of the floating gate through the intermediate insulating film. The lower end of the control gate is closer to the semiconductor substrate than the boundary between the upper gate part and the lower gate part.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种在不增加芯片尺寸的情况下增加控制栅极与浮动栅极的耦合比的半导体存储器件，并提供其制造方法。解决方案：半导体存储器件包括：形成在半导体衬底的表面上的多个有源区; 元件隔离部分，设置在相邻的有效区域之间; 设置在活动区域上的隧道绝缘膜; 包括通过隧道绝缘膜与每个有源区相对的下栅极部的浮栅，以及设置在下栅极部上的宽度大于下栅极部的宽度的上栅极部; 设置在所述浮动栅极的上表面和所述侧面上的中间绝缘膜; 以及通过中间绝缘膜设置在浮置栅极的上表面和侧面上的控制栅极。控制栅极的下端比上部栅极部分和下部栅极部分之间的边界更靠近半导体衬底。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2010272675A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2010272675A
公开(公告)日：2010-12-02
申请号：JP2009122926
申请日：2009-05-21
申请人： Toshiba Corp , 株式会社東芝
发明人： IZUMIDA TAKASHI , AOKI NOBUTOSHI , KONDO MASAKI , KANEMURA TAKAEI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： PROBLEM TO BE SOLVED: To reduce capacitance with an adjacent cell, and to improve a coupling ratio.
SOLUTION: This semiconductor storage device includes: a semiconductor substrate 101; a plurality of first insulation films 103 formed on the semiconductor substrate at predetermined intervals; element isolation regions 102 formed along a bit-line direction between the first insulation films; charge storage layers 104 each having a first charge storage film 104a formed on the first insulation film, a second charge storage film 104b formed on the first charge storage film and having a width in a word-line direction smaller than that of the first charge storage film, and a third charge storage film 104c formed on the second charge storage film and having a width in the word-line direction larger than that of the second charge storage film; second insulation films 107 each formed between the second charge storage film and the element isolation region; a third insulation film 105 formed along a second direction on the charge storage layers and the element isolation regions; and a control gate electrode 106 formed on the third insulation film.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：减少与相邻电池的电容，并提高耦合比。解决方案：该半导体存储装置包括：半导体衬底101; 以预定间隔形成在半导体衬底上的多个第一绝缘膜103; 元件隔离区域102沿第一绝缘膜之间的位线方向形成; 每个具有形成在第一绝缘膜上的第一电荷存储膜104a的电荷存储层104，形成在第一电荷存储膜上并且具有比第一电荷存储器的字线方向小的字线宽度的第二电荷存储膜104b 形成在第二电荷存储膜上并具有大于第二电荷存储膜的字线宽度的第三电荷存储膜104c; 每个形成在第二电荷存储膜和元件隔离区之间的第二绝缘膜107; 在电荷存储层和元件隔离区上沿着第二方向形成的第三绝缘膜105; 以及形成在第三绝缘膜上的控制栅电极106。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2010192734A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2010192734A
公开(公告)日：2010-09-02
申请号：JP2009036271
申请日：2009-02-19
申请人： Toshiba Corp , 株式会社東芝
发明人： AOKI NOBUTOSHI , KONDO MASAKI , IZUMIDA TAKASHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L21/28273
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device improved in write-in characteristics and retention characteristics through use of FG formed of a metal film.
SOLUTION: A nonvolatile semiconductor memory device is equipped with a memory cell having: a first gate insulating layer formed on a semiconductor substrate; a floating gate formed on the semiconductor substrate via the first gate insulating layer; a second gate insulating layer formed on the floating gate; and a control gate formed on the floating gate via the second gate insulating layer. The floating gate is formed of: a first semiconductor film in contact with the first gate insulating film; and a metal film laminated on the semiconductor film.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供通过使用由金属膜形成的FG来提高写入特性和保持特性的非易失性半导体存储器件。解决方案：非易失性半导体存储器件配备有存储单元，该存储单元具有形成在半导体衬底上的第一栅绝缘层; 通过所述第一栅极绝缘层在所述半导体衬底上形成的浮置栅极; 形成在所述浮动栅极上的第二栅极绝缘层; 以及通过第二栅极绝缘层形成在浮置栅极上的控制栅极。浮置栅极由与第一栅极绝缘膜接触的第一半导体膜形成; 和层叠在半导体膜上的金属膜。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2010177560A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2010177560A
公开(公告)日：2010-08-12
申请号：JP2009020385
申请日：2009-01-30
申请人： Toshiba Corp , 株式会社東芝
发明人： KONDO MASAKI , MATSUNAGA YASUHIKO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To enhance the writing or erasing speed of a charge-trap flash memory, and to suppress the erroneous writing thereof.
SOLUTION: In this semiconductor memory device 70, an N
+ layer 6 to be a source or a drain of a memory cell transistor is provided, and a plurality of gates of memory cell transistors and N+ layers 6 are alternately arranged and formed on a first principal plane (front surface) of a semiconductor substrate 1. A side wall film 7 with a dielectric constant of 15 is provided on both ends of an electric charge accumulation layer 3, a current shielding layer 4, and a control electrode 5 to be formed by lamination. A gap part 9 whose bottom is separated from the surroundings by a tunnel oxide film 2, whose side face is separated from the surroundings by the side wall film 7, whose upper part is separated from the surroundings by an insulating film 8, and in which the air is filled is provided at the side part of the gate of the memory cell transistor. The insulating film 8 is provided on the control electrode 5, the side wall film 7, and the gap part 9.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提高充电陷阱闪存的写入或擦除速度，并且抑制其错误写入。解决方案：在该半导体存储器件70中，提供作为存储单元晶体管的源极或漏极的N

9. 发明专利

JP2010009733A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2010009733A
公开(公告)日：2010-01-14
申请号：JP2008171491
申请日：2008-06-30
申请人： Toshiba Corp , 株式会社東芝
发明人： FUTAYAMA TAKUYA , EDAHIRO TOSHIAKI , FUJITA NORIHIRO , ARAI FUMITAKA , MARUYAMA TORU , KONDO MASAKI
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
CPC分类号： G11C16/3454 , G11C16/0483
摘要： PROBLEM TO BE SOLVED: To improve reliability of data written in a memory cell. SOLUTION: The nonvolatile semiconductor memory device includes a memory cell MC which stores data prescribed by threshold voltage and which can be electrically rewritten, a bit line BL electrically connected to one end of a current path of the memory cell MC, a control circuit 8 performing a verify operation for confirming the data after data is written in the memory cell MC, and a voltage setting circuit 41 setting charging voltage of the bit line BL in a verify operation and a read operation and making the charging voltage during the read operation higher than the charging voltage during the verify operation. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提高写入存储单元的数据的可靠性。解决方案：非易失性半导体存储器件包括：存储单元MC，其存储由阈值电压规定的并且可以被电重写的数据;电连接到存储单元MC的电流路径的一端的位线BL;控制电路8执行将数据写入存储单元MC之后确认数据的验证操作;以及电压设定电路41，在验证操作和读取操作中设定位线BL的充电电压，并在读取期间使充电电压在验证操作期间高于充电电压的操作。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2009212216A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009212216A
公开(公告)日：2009-09-17
申请号：JP2008052167
申请日：2008-03-03
申请人： Toshiba Corp , 株式会社東芝
发明人： TAKEUCHI WAKAKO , AKAHORI HIROSHI , KONDO MASAKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , H01L21/823462 , H01L27/105 , H01L27/11573 , H01L29/4234 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To suppress a damage to the edge of a first gate insulation film.
SOLUTION: The device includes a substrate, a first gate insulation film formed on the substrate, a charge storage layer formed on the first gate insulation film, a second gate insulation film formed on the charge storage layer, and a gate electrode formed on the second gate insulation film. The width between side surfaces of the second gate insulation film is smaller than the width between side surfaces of the gate electrode.
COPYRIGHT: (C)2009,JPO&INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式