专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2012044071A Electronic component mounting device and electronic component mounting method 有权
标题翻译：电子元件安装设备和电子元件安装方法
公开(公告)号：JP2012044071A
公开(公告)日：2012-03-01
申请号：JP2010185610
申请日：2010-08-20
申请人： Fujitsu Ltd , Shinko Electric Ind Co Ltd , 富士通株式会社 , 新光電気工業株式会社
发明人： YAMAGAMI TAKATOYO , KIRA HIDEHIKO , KUBOTA TAKASHI , OI ATSUSHI , IIDA KIYOAKI , KURIHARA TAKASHI
IPC分类号： H01L21/60 , H05K13/04
CPC分类号： H01L24/83 , H01L24/75 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/75 , H01L2224/75743 , H01L2224/81001 , H01L2224/83001 , H01L2224/83101 , H01L2224/83192 , H01L2224/838 , H01L2924/01006 , H01L2924/01033 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/3512
摘要： PROBLEM TO BE SOLVED: To prevent occurrence of creases on the upper surface of an underfill material.SOLUTION: A bonding tool 10 sucks a chip 41 while interposing an anti-adhesive tape 30 therebetween. The bonding tool 10 has an electronic component suction hole 11 through which the chip 41 is sucked, and a groove 13 provided on the periphery of the electronic component suction hole 11 in order to suck the anti-adhesive tape 30. When the chip 41 is pressed against an underfill material 70 and heated, and the mounting surface of an upper stage chip is formed by making the underfill material 70 protrude from the chip 41, thermally expanded portion of the anti-adhesive tape 30 enters the groove 13 and thereby creases do not occur on the upper surface of the underfill material.
摘要翻译：要解决的问题：为了防止在底部填充材料的上表面上产生折痕。解决方案：接合工具10吸附芯片41，同时在其间插入防粘带30。接合工具10具有吸引芯片41的电子部件吸入孔11和设置在电子部件吸入孔11的周围的槽13，以吸引防粘带30.当芯片41为压在底部填充材料70上并被加热，并且通过使底部填充材料70从芯片41突出而形成上层芯片的安装表面，防粘带30的热膨胀部分进入凹槽13，从而产生折痕不会发生在底部填充材料的上表面上。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2009117767A Manufacturing method of semiconductor device, and semiconductor device manufacture by same 审中-公开
标题翻译：半导体器件的制造方法及其半导体器件制造
公开(公告)号：JP2009117767A
公开(公告)日：2009-05-28
申请号：JP2007292142
申请日：2007-11-09
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： OI ATSUSHI , HARUHARA MASAHIRO , FUJII TOMOJI
IPC分类号： H01L23/12
CPC分类号： H01L23/3128 , H01L21/563 , H01L21/6835 , H01L23/4334 , H01L23/49816 , H01L23/552 , H01L23/562 , H01L24/16 , H01L24/81 , H01L25/0655 , H01L2221/68345 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2224/81001 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/15311 , H01L2924/18161 , H01L2924/19041 , H01L2924/19043 , H01L2924/3025 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device, that can provide the semiconductor device having a semiconductor chip and a wiring substrate connected with solder at a pitch of ≤100 μm.
SOLUTION: A required number of wiring layers 32 are formed on a temporary substrate 31 of which the thermal expansion coefficient differs from that of a semiconductor chip 38 by 2×10
-6 /°C or less and a part of the wiring layer of the uppermost layer is exposed to an opening part of an insulating layer 36 of the uppermost layer as a pad 34 and a wiring substrate is fabricated and a solder bonding member of the semiconductor chip 38 is brought into contact with the pad 34 of the wiring substrate and reflow is performed and the semiconductor chip 38 is attached to the wiring substrate 36. Thereafter, an outer peripheral part of the attached semiconductor chip 38 is sealed while exposing an upper surface of the semiconductor chip and removing the temporary substrate 31 and then a terminal for external connection is formed on the wiring substrate. A heat spreader 41 may be fitted to the exposed surface of the semiconductor chip 38.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供半导体器件的制造方法，其可以以≤100μm的间距提供具有半导体芯片和与焊料连接的布线基板的半导体器件。解决方案：在半导体芯片38的热膨胀系数与半导体芯片38的热膨胀系数不同的临时基板31上形成所需数量的布线层32，2×10 -6 -6 /℃/℃，最上层的布线层的一部分暴露于作为焊盘34的最上层的绝缘层36的开口部，并且制造布线基板，并且将半导体芯片38的焊接部件进入与布线基板的焊盘34接触并进行回流，并且将半导体芯片38安装到布线基板36上。然后，将半导体芯片38的外周部分暴露于半导体芯片的上表面并密封，移除临时基板31，然后在布线基板上形成用于外部连接的端子。散热器41可以装配到半导体芯片38的暴露表面。版权所有：（C）2009，JPO＆INPIT

3. 发明专利

JP2008306128A Semiconductor device and its production process 审中-公开
标题翻译：半导体器件及其生产工艺
公开(公告)号：JP2008306128A
公开(公告)日：2008-12-18
申请号：JP2007154126
申请日：2007-06-11
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： OI ATSUSHI , HIZUME TORU , CHINO TERUAKI
IPC分类号： H01L23/12 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/105 , H01L21/563 , H01L21/565 , H01L21/6835 , H01L23/3107 , H01L23/49811 , H01L23/49816 , H01L24/11 , H01L24/16 , H01L24/18 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L2221/68345 , H01L2224/1134 , H01L2224/1308 , H01L2224/13144 , H01L2224/16 , H01L2224/16245 , H01L2224/18 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/81005 , H01L2224/81801 , H01L2225/06562 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12041 , H01L2924/181 , H01L2924/18165 , H01L2924/19107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/01049
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its suitable production process for miniaturizing the semiconductor device and making it possible to assemble easily a product of semiconductor devices, in which semiconductor devices are accumulated.
SOLUTION: In the semiconductor device 100, a semiconductor device 14 is integrated in a resin molding part 12, which was formed in a flat plate shape. On one face of the resin molding part 12, the inner face side of wiring 16 connected electrically to the semiconductor element 12 is sealed by the resin molding part 12, and the outer face thereof is exposed flush with the resin molding part 12. In exterior of the plane region of the semiconductor element 14, a projection electrode 20 passing through the resin molding part 12 in its thickness direction is formed on the wiring 16, and an tip part 20a of the projection electrode 20 is projected from the other face of the resin molding part 12.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：为了提供一种用于使半导体器件小型化的半导体器件及其合适的制造工艺，并且使得可以容易地组装半导体器件的积聚半导体器件的产品。解决方案：在半导体器件100中，将半导体器件14集成在形成为平板形状的树脂成型部12中。在树脂成型部12的一个面上，与半导体元件12电连接的布线16的内表面侧被树脂成型部12密封，其外表面与树脂成形部12齐平。在外部在半导体元件14的平面区域中，在布线16上形成有通过树脂成型体12的厚度方向的突起电极20，突起电极20的前端部20a从树脂成型部件12.版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2007134458A Manufacturing method of wiring board and manufacturing method of semiconductor device 有权
标题翻译：接线板的制造方法和半导体器件的制造方法
公开(公告)号：JP2007134458A
公开(公告)日：2007-05-31
申请号：JP2005325090
申请日：2005-11-09
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： OI ATSUSHI
IPC分类号： H01L21/60
CPC分类号： H01L21/4857 , H01L21/4814 , H01L21/4846 , H01L24/16 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H05K3/243 , H05K3/28 , H05K3/4007 , H05K3/4644 , H05K2201/0367 , H05K2203/0361 , H05K2203/054
摘要： PROBLEM TO BE SOLVED: To provide a wiring circuit board ensuring reliability of mounting and enabling loading of semiconductor chips with fine connecting pitches, and also to provide a semiconductor device ensuring reliability of mounting and loading semiconductor chips to the wiring circuit board with fine connecting pitches. SOLUTION: A manufacturing method of a wiring circuit board for mounting semiconductor chips including connecting points connected to semiconductor chips and pattern wires connected to the semiconductor chips via connecting points. The method comprises a power feeding layer forming step to form a power feeding layer in view of forming connecting points with an electrolytic plating method, a masking step to form a mask pattern on the power feeding layer, an etching step for etching the power feeding layer exposed from the mask pattern, and an electrolytic plating step to form the connecting points with the electrolytic plating method on the pattern wires exposed from the mask pattern. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种布线电路板，其确保安装的可靠性并且能够以精细的连接间距加载半导体芯片，并且还提供确保将半导体芯片安装和加载到布线电路板的可靠性的半导体器件，精细连接节距。解决方案：一种用于安装半导体芯片的布线电路板的制造方法，包括通过连接点连接到半导体芯片的连接点和连接到半导体芯片的图案线。该方法包括供电层形成步骤，以形成电镀层的方式，以电解镀覆方法形成连接点，在供电层上形成掩模图案的掩模步骤，用于蚀刻供电层的蚀刻步骤从掩模图案露出的电解电镀步骤，以及从掩模图案露出的图案布线上以电解电镀法形成连接点。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2004128333A Thin-film capacitor, mounting module and manufacturing method therefor 审中-公开
公开(公告)号：JP2004128333A
公开(公告)日：2004-04-22
申请号：JP2002292562
申请日：2002-10-04
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： YAMAZAKI TOMOO , OI ATSUSHI , MUTSUKAWA AKIO
IPC分类号： H01G4/33 , H01G4/228 , H01L21/84 , H01L21/86 , H01L23/64 , H01L23/66 , H01L27/13
CPC分类号： H01G4/228 , H01G4/33 , H01L21/84 , H01L21/86 , H01L23/642 , H01L23/66 , H01L27/13 , H01L2224/16 , H01L2924/00014 , H01L2924/01078 , H01L2924/15311 , H01L2924/15312 , H01L2924/19011 , H01L2924/3011 , H01L2224/0401
摘要： PROBLEM TO BE SOLVED: To provide a thin-film capacitor that is mounted as a capacitor for bypass on a printed wiring board together with an LSI, and wherein the generation of parasitic inductance is prevented by making a core substrate smaller in thickness and size and its packaging characteristic is improved. SOLUTION: Grooves 21a-21e are formed in the core substrate 20, and a first conductor film 24 is formed and the grooves are filled with a first conductor. After a metallic film 25 is formed on the first conductor film, the metallic film is selectively anodized to genrate a dielectric film 26. A second conductor film 29 is formed on the dielectric film, and electrodes 33a-33e connecting with the second conductor film are formed. The rear portion of the core substrate is removed to each groove, and then electrodes 35a-35e connecting with the first conductor within each groove are formed. Thus, the capacitor is formed by the first conductor film and the second conductor film pinching the dielectric film. COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2004104017A Wiring board and semiconductor device having the wiring board 审中-公开
公开(公告)号：JP2004104017A
公开(公告)日：2004-04-02
申请号：JP2002267074
申请日：2002-09-12
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： OI ATSUSHI , HORIKAWA YASUYOSHI
IPC分类号： H01L23/12
CPC分类号： H01L2224/16225 , H01L2224/73204
摘要： PROBLEM TO BE SOLVED: To improve electric characteristics and electromigration when fine wiring patterns are formed on a wiring board for a semiconductor device.
SOLUTION: An insulating layer 23, an inter-layer insulating layer 24 and an outer layer insulating layer 25 are laminated on the upper surface of a resin-made core plate 22 through which vias 21 are formed and the wiring board is provided also with inner wiring patterns 26, vias 27, surface wiring patterns 28, and pads 29. The outer layer insulating layer 25 is made of polymethyl phenyl silane and has a low dielectric constant, a low dielectric tangent and high insulation.
COPYRIGHT: (C)2004,JPO

7. 发明专利

JP2012186511A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2012186511A
公开(公告)日：2012-09-27
申请号：JP2012150328
申请日：2012-07-04
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： OI ATSUSHI , KURIHARA TAKASHI
IPC分类号： H01L21/60
CPC分类号： H01L2224/16225 , H01L2224/27013 , H01L2224/73204 , H01L2224/83192
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device provided with a wiring board to which a semiconductor chip is flip-chip connected and an underfill resin encapsulating a gap between the semiconductor chip and the wiring board, which can inhibit occurrence of voids to improve yield.SOLUTION: A semi-cured film underfill resin 31 is applied to a top face 21A of a substrate body 21 under a vacuum atmosphere by using a diaphragm-type laminate device so as not to form a gap with the top face 21A, pads 22 and solders 23. Subsequently, a semiconductor chip 12 is pressed to the film underfill resin 31 to flip-chip connect the semiconductor chip 12 to the pads 22.
摘要翻译：解决的问题：提供一种半导体器件的制造方法，该半导体器件具有倒装芯片连接的半导体芯片的布线基板和在半导体芯片与布线基板之间封装间隙的底部填充树脂，其可以抑制空隙的发生以提高产量。解决方案：通过使用隔膜式层压装置，在真空环境下将半固化膜底部填充树脂31施加到基板主体21的顶面21A上，以便不与顶面21A形成间隙，焊盘22和焊料23.随后，将半导体芯片12压到膜底部填充树脂31上，以将半导体芯片12倒装芯片连接到焊盘22.版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2011054486A Wound-shape spring member, socket for semiconductor package, and method of manufacturing the same 有权
标题翻译：绕线弹簧构件，半导体封装用插座及其制造方法
公开(公告)号：JP2011054486A
公开(公告)日：2011-03-17
申请号：JP2009203885
申请日：2009-09-03
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： OI ATSUSHI , TANAKA MASATO , IHARA YOSHIHIRO , MOCHIZUKI KENJI
IPC分类号： H01R13/24 , H01R33/76 , H01R43/18
摘要： PROBLEM TO BE SOLVED: To provide a spring with high performance, a thinned and downsized semiconductor package with high efficiency, and further, to improve productivity of the spring with high performance and its applied products. SOLUTION: Two end parts 31, 32 of a wound-shape spring member 20 are positioned at a central part of the wound shape, and there is no overlapping area of the wound-shape spring member 20 having two end parts 31, 32 when viewed from the spring in its expanding direction. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供高性能的弹簧，具有高效率的薄型和小型化半导体封装，并且进一步提高具有高性能的弹簧的生产率及其应用产品。解决方案：缠绕形弹簧构件20的两个端部31,32位于缠绕形状的中心部分，并且没有具有两个端部31的缠绕形弹簧构件20的重叠区域，当从弹簧向其膨胀方向观察时。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2010232333A Semiconductor device, method of manufacturing the same, and electronic device 有权
标题翻译：半导体器件，其制造方法和电子器件
公开(公告)号：JP2010232333A
公开(公告)日：2010-10-14
申请号：JP2009077033
申请日：2009-03-26
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： OI ATSUSHI
IPC分类号： H01L23/12
CPC分类号： H01L23/49827 , H01L21/568 , H01L21/6835 , H01L23/13 , H01L23/49816 , H01L23/5389 , H01L24/16 , H01L24/19 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/82 , H01L25/105 , H01L2221/68345 , H01L2224/0401 , H01L2224/04105 , H01L2224/05147 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48647 , H01L2224/73204 , H01L2224/73265 , H01L2224/73267 , H01L2224/82001 , H01L2224/85447 , H01L2225/1035 , H01L2225/1058 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of being downsized in the thickness direction thereof, to provide a method of manufacturing the semiconductor device, and to provide an electronic device. SOLUTION: The semiconductor device includes: a multilayer wiring structure 31 having a through part 35; and a through electrode 33 provided in the multilayer wiring structure 31 and having first and second connection faces 41A and 42A exposed from faces 31A and 31B of the multilayer wiring structure 31. An electronic component 22 is housed in the through part 35 so as not to project from the first and second connection faces 41A and 42A, and the electronic component 22 and the through electrode 33 are electrically connected through a wiring pattern 25 directly connected to an electrode pad 45 of the electronic component 22 and the first connection face 41A of the through electrode. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供能够在其厚度方向上减小尺寸的半导体器件，以提供半导体器件的制造方法，并提供电子器件。解决方案：半导体器件包括：具有通孔部分35的多层布线结构31; 以及设置在多层布线结构31中并且具有从多层布线结构31的面31A和31B露出的第一和第二连接面41A和42A的贯通电极33.电子部件22容纳在贯通部35中，从第一和第二连接面41A和42A突出并且电子部件22和贯通电极33通过直接连接到电子部件22的电极焊盘45的布线图案25和第二连接面41A电连接通过电极。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2009117699A Component for semiconductor package, and manufacturing method of component for semiconductor package 审中-公开
标题翻译：半导体封装的组件和半导体封装组件的制造方法
公开(公告)号：JP2009117699A
公开(公告)日：2009-05-28
申请号：JP2007290706
申请日：2007-11-08
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： OI ATSUSHI , CHINO TERUAKI
IPC分类号： H01L23/12
CPC分类号： H01L21/4867 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/15311 , H05K3/28 , H05K2203/0582 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a component for semiconductor package which is manufactured employing a protective insulating material (non-photosensitive protective insulating material) containing no photosensitivity developing material, and has a protective insulating layer with a highly precise fine pattern which can not be formed by a printing method, and to provide a manufacturing method of such a component for semiconductor package. SOLUTION: The component for semiconductor package which has a protective insulating layer 5a on at least one surface of a component body 1 and exposes a conductive material 2 of the component body 1 to an opening part of the protective insulating layer 5a is manufactured by a method including the steps of (a) forming a mask 3 on at least one surface of the component body 1, (b) forming the protective insulating layer 5a by filling the opening part 4 of the mask with a protective insulating material 5 by a molding method using a metal mold having a mold release film 6, and (c) opening the metal mold and removing the mask 3. A typical component is a substrate for the semiconductor package or a lead frame. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种使用不含感光性显影材料的保护绝缘材料（非感光保护绝缘材料）制造的半导体封装的部件，并且具有高精度精细图案的保护绝缘层，不能通过印刷方法形成，并且提供这种半导体封装用部件的制造方法。解决方案：制造在组件主体1的至少一个表面上具有保护绝缘层5a并将组件主体1的导电材料2暴露于保护绝缘层5a的开口部分的半导体封装的部件通过包括以下步骤的方法：（a）在构件主体1的至少一个表面上形成掩模3，（b）通过用保护绝缘材料5填充掩模的开口部分4来形成保护绝缘层5a，使用具有脱模膜6的金属模具的成型方法，（c）打开金属模具并除去掩模3.典型的部件是用于半导体封装或引线框架的基板。版权所有（C）2009，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式