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1. 发明专利

JP2014107427A Wiring board, semiconductor device and wiring board manufacturing method 有权
标题翻译：接线板，半导体器件和接线板制造方法
公开(公告)号：JP2014107427A
公开(公告)日：2014-06-09
申请号：JP2012259682
申请日：2012-11-28
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： CHINO TERUAKI
IPC分类号： H01L23/12 , H01L21/60
CPC分类号： H05K3/4007 , H01L21/4853 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H05K3/3436 , H05K3/3473 , H05K2201/0338 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a wiring board which can inhibit a short circuit between adjacent solder bumps.SOLUTION: A wiring board 10 comprises: a wiring pattern 30 in an outermost layer; a solder resist layer 50 having openings 50X each of which exposes a part of the wiring pattern 30 as a connection pad 30P; and solder bumps 40 formed on the connection pads 30P, respectively. The solder bump 40 includes a solder layer 41 formed on the connection pad 30P and a columnar metal post 42 wholly covered with the solder layer 41.
摘要翻译：要解决的问题：提供一种可以抑制相邻焊料凸块之间短路的布线板。解决方案：布线板10包括：最外层的布线图案30; 具有开口50X的阻焊层50，每个开口50X暴露作为连接焊盘30P的布线图案30的一部分; 以及分别形成在连接焊盘30P上的焊料凸块40。焊料凸块40包括形成在连接焊盘30P上的焊料层41和完全被焊料层41覆盖的柱状金属柱42。

2. 发明专利

JP2008306128A Semiconductor device and its production process 审中-公开
标题翻译：半导体器件及其生产工艺
公开(公告)号：JP2008306128A
公开(公告)日：2008-12-18
申请号：JP2007154126
申请日：2007-06-11
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： OI ATSUSHI , HIZUME TORU , CHINO TERUAKI
IPC分类号： H01L23/12 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/105 , H01L21/563 , H01L21/565 , H01L21/6835 , H01L23/3107 , H01L23/49811 , H01L23/49816 , H01L24/11 , H01L24/16 , H01L24/18 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L2221/68345 , H01L2224/1134 , H01L2224/1308 , H01L2224/13144 , H01L2224/16 , H01L2224/16245 , H01L2224/18 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/81005 , H01L2224/81801 , H01L2225/06562 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12041 , H01L2924/181 , H01L2924/18165 , H01L2924/19107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/01049
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its suitable production process for miniaturizing the semiconductor device and making it possible to assemble easily a product of semiconductor devices, in which semiconductor devices are accumulated.
SOLUTION: In the semiconductor device 100, a semiconductor device 14 is integrated in a resin molding part 12, which was formed in a flat plate shape. On one face of the resin molding part 12, the inner face side of wiring 16 connected electrically to the semiconductor element 12 is sealed by the resin molding part 12, and the outer face thereof is exposed flush with the resin molding part 12. In exterior of the plane region of the semiconductor element 14, a projection electrode 20 passing through the resin molding part 12 in its thickness direction is formed on the wiring 16, and an tip part 20a of the projection electrode 20 is projected from the other face of the resin molding part 12.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：为了提供一种用于使半导体器件小型化的半导体器件及其合适的制造工艺，并且使得可以容易地组装半导体器件的积聚半导体器件的产品。解决方案：在半导体器件100中，将半导体器件14集成在形成为平板形状的树脂成型部12中。在树脂成型部12的一个面上，与半导体元件12电连接的布线16的内表面侧被树脂成型部12密封，其外表面与树脂成形部12齐平。在外部在半导体元件14的平面区域中，在布线16上形成有通过树脂成型体12的厚度方向的突起电极20，突起电极20的前端部20a从树脂成型部件12.版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2011238767A Semiconductor package and method of manufacturing the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：JP2011238767A
公开(公告)日：2011-11-24
申请号：JP2010108688
申请日：2010-05-10
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： CHINO TERUAKI
IPC分类号： H01L21/56 , H01L23/12 , H01L23/29 , H01L23/31
CPC分类号： H01L24/96 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/49816 , H01L23/5389 , H01L24/97 , H01L2223/5448 , H01L2223/54486 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/24227 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15174 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/18162 , H01L2224/82 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor package in which displacement of a semiconductor chip can be prevented when it is sealed with resin, and to provide a method of manufacturing the same.SOLUTION: A method of manufacturing a semiconductor package comprises a first step for arranging a semiconductor chip in a recess provided in one surface of a support such that a portion of the semiconductor chip protrudes therefrom, a second step for forming a resin part which seals the protrusion of the semiconductor chip on one surface of the support, a third step for removing the support, and a fourth step for forming a wiring structure which is connected with the semiconductor chip electrically by using the resin part as a part of the substrate.
摘要翻译：解决的问题：提供一种半导体封装，其中当用树脂密封时可以防止半导体芯片的位移，并提供其制造方法。解决方案：制造半导体封装的方法包括：第一步骤，用于将半导体芯片布置在设置在支撑体的一个表面中的凹部中，使得半导体芯片的一部分从其突出;第二步骤，用于形成树脂部分其密封了支撑体的一个表面上的半导体芯片的突起，用于去除支撑件的第三步骤，以及用于形成通过使用树脂部件作为半导体芯片的一部分而与半导体芯片电连接的布线结构的第四步骤基质。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2011082287A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011082287A
公开(公告)日：2011-04-21
申请号：JP2009232163
申请日：2009-10-06
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： CHINO TERUAKI
IPC分类号： H01L21/56 , H01L23/12 , H01L23/29 , H01L23/31
CPC分类号： H01L23/5389 , H01L21/561 , H01L21/568 , H01L23/3121 , H01L23/3135 , H01L24/19 , H01L24/96 , H01L2221/68359 , H01L2224/04105 , H01L2224/20 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/18162 , H01L2924/351 , H01L2924/3511 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device such that a periphery and a back surface side of a semiconductor chip can be sealed with a resin substrate without causing any trouble.
SOLUTION: The method of manufacturing the semiconductor device, includes temporarily fixing the semiconductor chip 20 to a supporting member 10 to direct a connection electrode 20a toward the supporting member side 10, forming an insulating layer 30 for preventing resin-permeation covering the semiconductor chip 20, on the supporting member 10 and the semiconductor chip 20, forming the resin substrate 50 sealing the periphery and back surface side of the semiconductor chip 20, on the insulating layer 30 for preventing resin-permeation, and removing the supporting member 10 to expose the connection electrode 20a of the semiconductor chip 20. A build-up wiring BW is connected directly to the connection electrode 20a of the semiconductor chip 20.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，使得半导体芯片的周边和背面侧可以用树脂基板密封而不会造成任何麻烦。解决方案：制造半导体器件的方法包括将半导体芯片20临时固定到支撑构件10以将连接电极20a引向支撑构件侧10，形成用于防止树脂渗透的绝缘层30 半导体芯片20，在支撑构件10和半导体芯片20上，形成树脂基板50，密封半导体芯片20的周边和背面侧，在绝缘层30上防止树脂渗透，并且移除支撑构件10 露出半导体芯片20的连接电极20a。积聚布线BW直接连接到半导体芯片20的连接电极20a。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2009130088A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009130088A
公开(公告)日：2009-06-11
申请号：JP2007302719
申请日：2007-11-22
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： IHARA YOSHIHIRO , OI ATSUSHI , CHINO TERUAKI
IPC分类号： H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L2224/73204
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device wherein upper and lower substrates are stacked for precise alignment, with thickness being reduced.
SOLUTION: In a semiconductor device 32, a plurality of substrates 10 are electrically connected and stacked, where a semiconductor chip 18 is electrically connected and mounted on a wiring pattern 14, and the semiconductor chip 18 and the wiring pattern 14 are sealed up with a resin 22. In each substrate 10, grooves 24 where an external connection terminal 14b of the wiring pattern 14 is exposed are opened, on both sides, in required numbers on a pair of parallel sidewall surfaces. In the groove 24, a lead part 30 formed by working with a metal plate is electrically connected and fixed to the exposed external connection terminal 14b of each substrate 10.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其中上下基板被堆叠以精确对准，其厚度减小。解决方案：在半导体器件32中，多个基板10电连接并堆叠，其中半导体芯片18电连接并安装在布线图案14上，并且半导体芯片18和布线图案14被密封在每个基板10中，布线图案14的外部连接端子14b露出的凹槽24在两侧以所需数量在一对平行的侧壁表面上打开。在凹槽24中，通过与金属板一起工作形成的引线部分30电连接并固定到每个基板10的暴露的外部连接端子14b上。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2011082404A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2011082404A
公开(公告)日：2011-04-21
申请号：JP2009234752
申请日：2009-10-09
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： CHINO TERUAKI
IPC分类号： H01L23/12
CPC分类号： H01L24/96 , H01L21/568 , H01L2224/04105 , H01L2224/19 , H01L2924/351 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device such that a periphery and a back side of a semiconductor chip can be sealed with a resin substrate without any trouble. SOLUTION: The method of manufacturing the semiconductor device includes the processes of: forming an adhesive layer 12 having an opening 12a on a support 10; sticking and temporarily fixing a peripheral edge of a surface of the semiconductor chip 20 on an outer peripheral part of the opening 12a of the adhesive layer 12 with a connection electrode 20a on a surface side of the semiconductor chip 20 down; forming the resin substrate 50 for sealing the periphery and back side of the semiconductor chip 20; and exposing the connection electrode 20a of the semiconductor chip 20 by removing the support 10 and the adhesive layer 12. Build-up wiring BW is connected directly to the connection electrode 20a of the semiconductor chip 20. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，使得半导体芯片的周边和背面可以用树脂基板密封而没有任何麻烦。解决方案：制造半导体器件的方法包括以下过程：在支撑体10上形成具有开口12a的粘合剂层12; 在半导体芯片20的表面侧上的连接电极20a向下粘附并临时固定半导体芯片20的表面的外围边缘在粘合剂层12的开口12a的外周部上; 形成用于密封半导体芯片20的周边和背面的树脂基板50; 并通过去除支撑体10和粘合剂层12来暴露半导体芯片20的连接电极20a。积层布线BW直接连接到半导体芯片20的连接电极20a。版权所有（C）2011 ，JPO＆INPIT

7. 发明专利

JP2011061116A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011061116A
公开(公告)日：2011-03-24
申请号：JP2009211414
申请日：2009-09-14
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： KATAGIRI FUMIMASA , CHINO TERUAKI , TATEIWA AKIHIKO
IPC分类号： H01L23/28 , H01L21/56
CPC分类号： H01L23/4334 , H01L21/6835 , H01L23/3121 , H01L24/19 , H01L24/97 , H01L2221/68345 , H01L2221/68359 , H01L2224/04105 , H01L2224/20 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/15747 , H01L2924/18162 , H01L2924/30107 , H01L2924/3511 , H01L2224/19 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent the occurrence of warping of a resin substrate in a semiconductor device having a structure wherein the periphery of a semiconductor chip is sealed by the resin substrate.
SOLUTION: The semiconductor device includes the semiconductor chip 20 having a connection electrode 20a on the surface side, and the resin substrate 30 that seals the periphery of the semiconductor chip 20 and has a thickness T on the underside from the backside of the semiconductor chip 20 and has its lower surface located below the backside of the semiconductor chip. An interconnection layer 50 is directly connected to the connection electrode 20a of the semiconductor chip 20 without involving solder.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：为了防止在半导体芯片的周围被树脂基板密封的半导体器件中树脂基板发生翘曲。解决方案：半导体器件包括在表面侧具有连接电极20a的半导体芯片20和从半导体芯片20的背面密封半导体芯片20的周边并具有厚度T的树脂基板30。半导体芯片20，并且其下表面位于半导体芯片的背面下方。互连层50直接连接到半导体芯片20的连接电极20a而不涉及焊料。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2009117699A Component for semiconductor package, and manufacturing method of component for semiconductor package 审中-公开
标题翻译：半导体封装的组件和半导体封装组件的制造方法
公开(公告)号：JP2009117699A
公开(公告)日：2009-05-28
申请号：JP2007290706
申请日：2007-11-08
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： OI ATSUSHI , CHINO TERUAKI
IPC分类号： H01L23/12
CPC分类号： H01L21/4867 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/15311 , H05K3/28 , H05K2203/0582 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a component for semiconductor package which is manufactured employing a protective insulating material (non-photosensitive protective insulating material) containing no photosensitivity developing material, and has a protective insulating layer with a highly precise fine pattern which can not be formed by a printing method, and to provide a manufacturing method of such a component for semiconductor package. SOLUTION: The component for semiconductor package which has a protective insulating layer 5a on at least one surface of a component body 1 and exposes a conductive material 2 of the component body 1 to an opening part of the protective insulating layer 5a is manufactured by a method including the steps of (a) forming a mask 3 on at least one surface of the component body 1, (b) forming the protective insulating layer 5a by filling the opening part 4 of the mask with a protective insulating material 5 by a molding method using a metal mold having a mold release film 6, and (c) opening the metal mold and removing the mask 3. A typical component is a substrate for the semiconductor package or a lead frame. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种使用不含感光性显影材料的保护绝缘材料（非感光保护绝缘材料）制造的半导体封装的部件，并且具有高精度精细图案的保护绝缘层，不能通过印刷方法形成，并且提供这种半导体封装用部件的制造方法。解决方案：制造在组件主体1的至少一个表面上具有保护绝缘层5a并将组件主体1的导电材料2暴露于保护绝缘层5a的开口部分的半导体封装的部件通过包括以下步骤的方法：（a）在构件主体1的至少一个表面上形成掩模3，（b）通过用保护绝缘材料5填充掩模的开口部分4来形成保护绝缘层5a，使用具有脱模膜6的金属模具的成型方法，（c）打开金属模具并除去掩模3.典型的部件是用于半导体封装或引线框架的基板。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2009099782A Semiconductor-chip laminating structure, and semiconductor apparatus 有权
标题翻译：半导体芯片层叠结构和半导体器件
公开(公告)号：JP2009099782A
公开(公告)日：2009-05-07
申请号：JP2007270165
申请日：2007-10-17
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： CHINO TERUAKI , OI ATSUSHI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/73204
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor-chip laminating structure having a plurality of semiconductor chips, which improves its yield and is miniaturized, and to provide a semiconductor apparatus. SOLUTION: The semiconductor-chip laminating structure has a first semiconductor chip 12, wiring patterns 11 electrically connected to the first semiconductor chip 12, a first sealing resin 14 for sealing the first semiconductor chip 12 so as to expose a surface 11B of each wiring pattern 11 to the external which positions on the opposite side of an opposite surface 11A of each wiring pattern 11 to the first semiconductor chip 12, and a second semiconductor chip 18 disposed opposite the surfaces 11B of the wiring patterns 11 and electrically connected to the wiring patterns 11. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供具有多个半导体芯片的半导体芯片层叠结构，其提高其产量并且小型化并提供半导体装置。解决方案：半导体芯片层压结构具有第一半导体芯片12，与第一半导体芯片12电连接的布线图案11，用于密封第一半导体芯片12以暴露第一半导体芯片12的表面11B的第一密封树脂14 每个布线图案11到位于与每个布线图案11相对的第一半导体芯片12的相对表面11A的相对侧的外部，以及与布线图案11的表面11B相对设置并电连接到布线图案11.版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2015026722A バンプ構造、配線基板及び半導体装置並びにバンプ構造の製造方法有权
标题翻译： BUMP结构，接线板，半导体器件和BUMP结构的制造方法
公开(公告)号：JP2015026722A
公开(公告)日：2015-02-05
申请号：JP2013155615
申请日：2013-07-26
申请人：新光電気工業株式会社 , Shinko Electric Ind Co Ltd
发明人： KONDO KATSURA , YAMAZAKI KATSUMI , KATAGIRI NORITAKA , CHINO TERUAKI
IPC分类号： H01L21/60 , H01L23/12
CPC分类号： H05K1/111 , H01L2224/16225 , H05K1/181 , H05K3/3426 , H05K3/4007 , H05K2201/09427 , H05K2201/09745 , H05K2201/09827 , H05K2201/10704 , Y02P70/611 , Y02P70/613
摘要：【課題】バンプ間にブリッジが発生するのを防止し得るバンプ構造を提供する。【解決手段】絶縁樹脂層14のテーパー状の開口15内の側壁上に、シード層18を介して金属層20が形成されている。シード層18と金属層20とは、絶縁樹脂層14上方に突出している。金属層20は、底部20aと、底部20aと一体に形成され、上部が拡がった筒状部20bとを有している。金属層20の筒状部20bの内側にはんだが充填されてはんだ材22が形成されている。金属層20は、はんだ材22よりも融点の高い金属により形成されている。【選択図】図1
摘要翻译：要解决的问题：提供一种防止凸块之间的桥的发生的凸块结构。解决方案：金属层20通过种子层18形成在绝缘树脂层14的每个锥形开口15的侧壁上。种子层18和金属层20突出到绝缘树脂层14上方的区域。每个金属层20包括：底部20a; 以及与底部20a一体形成并在上部膨胀的圆筒部20b。焊料填充每个金属层20的圆柱形部分20b的内侧以形成焊料22。金属层20由熔点高于焊料22的熔点形成。

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