专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP0108664A3 Floating point microprocessor 失效
标题翻译：浮点微处理器
公开(公告)号：EP0108664A3
公开(公告)日：1987-10-28
申请号：EP83401935
申请日：1983-10-04
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Ayalew Melesse , Burke, Gary , Dante III, Edward , Dao, Tich , Davidesko, Itzhak , Kayruz, Camille , Mor, Yeshayahu
IPC分类号： G06F09/22 , G06F07/48 , G06F09/26
CPC分类号： G06F9/26 , G06F7/483
摘要： A microprocessor integrated circuit (50) includes a control, timing and interface section (52) connected by control signal lines (54) to each of the other functional elements shown. Section (52) is further connected to a 16-bit wide internal information bus (56) by bus (58). Bus (60) also connects the section (52) to a 16-bit wide external information bus (62). Buffer circuit (64) connects the external information bus (62) to the internal information bus (56). The internal information bus (56) is connected by bus (66) to a programmable shifter and unpacker section (68). The section (68) is connected to a Mantissa processor (70) by a 64-bit wide bus (72) and by two 32-bit wide buses (74) and (76). The shifter (68) is connected to an exponent processor (78) by 16-bit wide buses (80) and (82). The Mantissa processor (70) is also connected to the internal information bus (56) by bus (84). The sign logic circuits (86) are connected to the programmable shifter and unpacker section (68) by line (88). Mantissa processor (70) includes a 32-bit arithmetic and logic unit (ALU), a variable width register file, working registers and flipflops, control PLAs, detection logic and bus buffers. The exponent and sign processor (78) includes a 16-bit wide ALU, variable width register file, working registers, control and constants PLAs detection logic and sign logic and flipflops. The programmable shifter and unpacker (68) is a 64-bit wide shifter capable of shifting in one machine cycle from 0 to 8 positions to the left or 0 to 24 positions to the right. The control timing and interface section (52) is based on a two-level microprogramming scheme to save microcode and to optimize execution times on a dynamic microcycle.
摘要翻译：微处理器集成电路（50）包括通过控制信号线（54）连接到所示其它功能元件的控制，定时和接口部分（52）。部分（52）还通过总线（58）连接到16位宽的内部信息总线（56）。总线（60）还将部分（52）连接到16位宽的外部信息总线（62）。缓冲电路（64）将外部信息总线（62）连接到内部信息总线（56）。内部信息总线（56）通过总线（66）连接到可编程移位器和解包器部分（68）。部分（68）通过64位宽总线（72）和两个32位宽总线（74）和（76）连接到尾数处理器（70）。移位器（68）通过16位宽的总线（80）和（82）连接到指数处理器（78）。尾数处理器（70）也通过总线（84）连接到内部信息总线（56）。符号逻辑电路（86）通过线路（88）连接到可编程移位器和解包器部分（68）。尾数处理器（70）包括32位算术和逻辑单元（ALU），可变宽度寄存器文件，工作寄存器和触发器，控制PLA，检测逻辑和总线缓冲器。指数和符号处理器（78）包括16位宽的ALU，可变宽度寄存器文件，工作寄存器，控制和常数PLA检测逻辑和符号逻辑和触发器。可编程移位器和解包器（68）是一个64位宽移位器，能够在一个机器周期中从0到8个位置向左移位或0到24个位置向右移位。控制定时和接口部分（52）基于两级微程序方案来保存微代码以优化在动态微循环上的执行时间。

2. 发明公开

EP0140515A3 Flexible computer control unit 有权
标题翻译：柔性计算机控制单元
公开(公告)号：EP0140515A3
公开(公告)日：1987-04-29
申请号：EP84305693
申请日：1984-08-21
申请人： AMDAHL CORPORATION
发明人： Lee, Hsiao-Peng Sherman , Spannagel, Ulrich
IPC分类号： G06F09/22
CPC分类号： G06F9/223 , G06F9/226
摘要： Disclosed is a control unit including a flexible decoder unit providing control patterns for controlling functional units in data processing equipment. The control unit includes hardwired decoder logic which decodes a multi-bit key to provide primary decoded outputs as control patterns. The decoder unit also decodes one or more alternate decoded outputs for future use. The decoder includes a plurality of flexibility inputs which, when connected to an alternate decoded output, provide new control patterns and thus provides flexibility to the hardwired decoder. Because of the flexibility, the control patterns formed by the hardwired decoder can be readily changed. The flexible hardwired decoder is of great value, therefore, when design changes are desired in a computer.

3. 发明公开

EP0110227A3 Control memory organization 失效
标题翻译：控制存储器组织
公开(公告)号：EP0110227A3
公开(公告)日：1984-07-25
申请号：EP83111360
申请日：1983-11-14
申请人： HONEYWELL INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Maccianti, Tiziano , Balasini, Flavio
IPC分类号： G06F09/22
CPC分类号： G06F9/30145 , G06F9/226 , G06F9/267 , G06F9/268 , G06F9/30167
摘要： in a microprogrammed data processing system wherein the execution of a microinstruction sequence may be interrupted at any time for the execution of a more prioritary microinstruction sequence, the control memory is organized in such a way as to provide microinstructions of variable length. The basic length of the microinstructions is defined by the parallelism of a first control memory (1). With regard to a first range of addresses of the first control memory, a second control memory (17), read in parallel to the first one, provides a microinstruction field which is added to the basic field of the first memory and increases the microinstruction length. With regard to the remaining field of addresses of the first control memory, a first microinstruction may load with one of its bit fields a register (22). Then such bit field is associated to the subsequent microinstruction for increasing the length of it. In this case, in order to avoid that the execution of such longer subsequent microinstruction be affected by a microprogram interruption occurring within the execution of the first microinstruction and the reading out of the subsequent one, some logic circuits (25, 26, 27, 28, 29, 30) defers, in case of interruption, the association of the bit field to the subsequent microinstruction till the return to the interrupted microprogram.

4. 发明公开

EP0232797A3 Pseudo-microprogramming in microprocessor with compressed control ROM and with strip layout of busses, alu and registers 失效
标题翻译：在带有压缩控制ROM的微处理器中进行伪微编程，并带有总线，alu和寄存器的带状布局
公开(公告)号：EP0232797A3
公开(公告)日：1988-02-03
申请号：EP87101127
申请日：1981-11-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： McDonough, Kevin C. , Guttag, Karl M. , Laws, Gerald E.
IPC分类号： G06F15/06 , G06F09/22 , G06F09/46 , G06F09/30 , G11C17/00
CPC分类号： G06F9/30156 , G06F9/223 , G06F15/7839 , G11C17/12
摘要： A single-chip microprocessor device of the MOS/LSI type contains an ALU, several interal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. The ALU, registers and busses along with the control ROM are constructed in an interrelated layout whereby minimum space is needed on the chip. Like bits in all registers and the ALU are aligned and in a regular pattern. The busses are metal lines overlying each of the strips of ALU/register bits. Controls are polysilicon lines perpendicular to the busses and aligned with columns of the control ROM. The control ROM is an array of rows and columns of potential MOS transistors, compressed by eliminating column lines which contain no transistors. The number of bits per column is a minimum to enhance compressability producing a wide configuration (long row lines) which allows the columns for control signals to align with the part of the ALU/register strip where the signal is to be used. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM) is provided which allows execution of instruction sequences to emulate complex instructions are indistinguishable from "native" instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. This on-chip memory does not affect the off-chip main memory map. Microprocessors are thus made more versatile and can be customized with little design effort. Also, off-chip access of another memory separate from the main memory allows emulator functions or special instructions.
摘要翻译： MOS / LSI型单芯片微处理器包含一个ALU，若干内部总线，多个地址/数据寄存器以及一个带有相关控制解码或微控制器电路的指令寄存器。该器件通过双向多路复用地址/数据总线和多条控制线与外部存储器和外设通信。 ALU，寄存器和总线与控制ROM一起构成相互关联的布局，因此芯片上需要最小的空间。像所有寄存器中的位一样，ALU按照规则模式对齐。总线是覆盖每个ALU /寄存器位条的金属线。控件是垂直于总线的多晶硅线，并与控制ROM的列对齐。控制ROM是可能的MOS晶体管的行和列的阵列，通过消除不包含晶体管的列线进行压缩。为了增强可压缩性，每列的位数是最小的，从而产生宽配置（长行线），这允许控制信号的列与要使用信号的ALU /寄存器条的部分对齐。除了主要的片外存储器外，还提供了一个较小的片上存储器（包括ROM和RAM），允许指令序列的执行仿真复杂的指令，与“本地”指令无法区分，因为所有的存储器读取等都是以完全相同的方式生成，长指令序列可中断。该片内存储器不影响片外主存储器映射。因此，微处理器的功能更加丰富，可以通过少量设计来定制。另外，与主存储器分开的另一个存储器的片外访问允许模拟器功能或特殊指令。

5. 发明公开

EP0081034A3 Control unit for a functional processor 失效
标题翻译：功能处理器控制单元
公开(公告)号：EP0081034A3
公开(公告)日：1986-10-01
申请号：EP82107101
申请日：1982-08-06
申请人： International Business Machines Corporation
发明人： Demuth, Gordon L. , Hinkle, John E. , Moran, Thomas J.
IPC分类号： G06F09/22
CPC分类号： G06F9/264 , G06F9/226 , G06F9/262
摘要： A control unit for a functional processor is disclosed which minimizes programming complexity by eliminating data transfers and the transfer control associated with two level memory systems and which improves flexibility in program task changeovers in pipelined arithmetic architectures. This is accomplished by employing common page addressing for accessing memory address stacks for storing either main memory addresses or address increments, coefficient address stacks for storing coefficient memory addresses or address increments, and microinstruction sequencing control branch stacks for storing branch and loop control parameters. This permits chaining of long sequences of signal processing subroutines without external control and the associated execution time overhead. An additional feature is a revolving buffer operation in which a plurality of main memory modules are cyclically connected to each of a plurality of scratch pad buffers in the arithmetic unit in a synchronous manner so as to maximize the throughput of the combined operation of memory transfers, arithmetic processing and I/O transfers. In another feature, the controller employs a dual clocking arrangement whereby scratch pad storage elements and arithmetic elements can be selectively controlled to operate at twice the rate at which microinstructions are accessed from the microprogram store. The resulting controller for a pipelined arithmetic architecture provides a closely coupled control of looping and branching control operations with storage accessing operations and pipelined arithmetic operations to provide for immediate and flexible responses to changes in programming tasks.

6. 发明公开

EP0092610A3 Methods for partitioning mainframe instruction sets to implement microprocessor based emulation thereof 失效
标题翻译：用于实施基于微处理器的仿真的MAINFRAME指令集的分类方法
公开(公告)号：EP0092610A3
公开(公告)日：1985-05-29
申请号：EP82111813
申请日：1982-12-20
申请人： International Business Machines Corporation
发明人： Kellerman, Anne Sheila , Losinger, Raymond Ellison , Valashinas, James William , Agnew, Palmer Wright , Buonomo, Joseph Patrick , Houghtalen, Steven Ray
IPC分类号： G06F09/38 , G06F09/22
CPC分类号： G06F9/223 , G06F9/26 , G06F9/3017 , G06F9/30174 , G06F9/3877 , G06F9/3879
摘要： Methods of applying LSI and microprocessors to the design of microprocessor-based LSI implementation of mainframe processors are described. The mainframe instruction set is partitioned into two or more subsets, each of which can be implemented by a microprocessor having special on-chip microcode or by a standard off-the-shelf microprocessor running programs written for that purpose. Alternatively, one or more of the subsets can be implemented by a single microprocessor. In addition, a subset of the partitioned instruction set can be implemented by emulating software, by off-chip vertical or horizontal microcode, or by primitives. But, however partitioning is implemented, the end result thereof is to keep the critical flow paths, associated with the most frequently used instruction subset, as short as possible by constraining them to a single chip. For each subset of the instructions that requires high performance, the corresponding microprocessor chip contains the data flow path and all elements, including registers, necessary for the execution of that subset as well as the microcode that controls execution. In some applications, a subset of the instructions that does not require high performance is implemented with a critical path that crosses several chip boundaries and is, therefore, considerably slower. The application of this method requires partitioning that makes each identified high performance subset executable on one microprocessor in the current state of technology, a way to quickly pass control back and forth between all of the microprocessors, a suitable way to pass data back and forth between all of the microprocessors, and a technology in which it is ecomonically feasible to have several copies of a complex data flow and control store mechanism.
摘要翻译：描述了将LSI和微处理器应用于基于微处理器的LSI实现主机处理器的方法。大型机指令集被划分为两个或更多个子集，每个子集可以由具有特殊片上微码的微处理器或由运行用于该目的而编写的程序的标准现成的微处理器来实现。或者，一个或多个子集可以由单个微处理器来实现。此外，分割指令集的子集可以通过模拟软件，片外垂直或水平微代码，或者由原语来实现。但是，然而，实现分区，其最终结果是将与最常用的指令子集相关联的关键流程路径尽可能短地限制到单个芯片。该方法的应用需要分区，这使得每个识别的高性能子集在当前技术状态下在一个微处理器上可执行，这是在所有微处理器之间来回快速传递控制的一种方式，所有这些微处理器，以及在经济上具有复制数据流和控制存储机制的多个拷贝的技术。

7. 发明公开

EP0028437A3 A high-speed time share processor for use in a data processing system 失效
标题翻译：用于数据处理系统的高速时间分配处理器
公开(公告)号：EP0028437A3
公开(公告)日：1981-12-02
申请号：EP80301381
申请日：1980-04-28
申请人： Frederick Electronics Corporation
发明人： Woodell, Jack L.
IPC分类号： G06F15/16 , G06F09/22 , H04L11/00 , H04Q03/54
CPC分类号： G06F13/22 , G06F13/124 , H04L12/50
摘要： A microcoded processor (10) for use in a distributed processing telex exchange to time share process each termination connected to the processor is disclosed. The processor [10) executes selected signaling routines for each termination. The processor contains a sequence file (60) that outputs the address of the next termination to be time share processed; a constant (64) and a variable (66) data file which contains data needed to execute the selected signaling routine for each termination; and a program re-entry file (62) to control the time share execution of each signaling routine. At the end of each time share interval, the program counter contents are stored in the re-entry file (62) location associated with the termination just processed. To enable high-speed processing, two high-speed cache memories (72, 74). one for the data from the constant file (64) and one for the data from the variable file (66). are also used. Program execution continues uninterrupted at the end of each time share interval.

8. 发明公开

EP0025511A3 Control device for executing instructions 失效
标题翻译：用于执行指令的控制装置
公开(公告)号：EP0025511A3
公开(公告)日：1981-09-09
申请号：EP80104759
申请日：1980-08-12
申请人： International Business Machines Corporation
发明人： Bazlen, Dieter, Dr. , Bock, Dietrich , Getzlaff, Klaus J. , Hajdu, Johann , Painke, Helmut
IPC分类号： G06F09/22 , G06F09/30
CPC分类号： G06F9/3001 , G06F9/223 , G06F9/26 , G06F9/3869
摘要： In den Mikroinstrukionssätzen von elektronischen Datenverarbeitungsanlagen gibt es eine Reihe von Mikro instruktionen, die hinsichtlich ihres Operationsablaufs gleich sind und sich nur in der Länge des Datenpfades, über den die zu einer Instruktionen gehörenden Daten übertragen werden, unterscheiden. So gibt es beispiels weise eine Reihe von Instruktionen, mit denen Daten aus einem Speicher abgerufen und zur Verarbeitung zu einer anderen Systemkomponente übertragen werden. Auf dem Weg zu der anderen Systemkomponente, beispielsweise einem Register oder einem Arbeitsspeicher, können die Daten gegebenenfalls auch noch über eine weitere System komponente, die beispielsweise nur eine Dezimalumwand lung der Daten vornimmt, übertragen werden.
Auf die Datenfluß-Steuerlogik wirkt sich das so aus, daß ein Schreibimpuls, der zum Einschreiben dieser Daten in den Arbeitsspeicher benötigt wird, wegen der längeren Laufzeit über den längeren Datenpfad, erst eine Instruk tionszykluszeit später erzeugt werden darf, um Informa tionsverlust zu vermeiden.
Wird nun ein in der Figur dargestellter Instruktions zykluszähler verwendet, dann kann die Struktur der Da tenflußsteuerlogik für Instruktionen der eingangs erwähn ten Art sowohl für kürzere als auch für längere Datenpfade den gleichen Aufbau haben. Eine Steuerlogik 51 bis 54 im Instruktionszykluszähler sorgt dafür, daß dieser Instruk tionszykluszahler so viele Leerzyklen der Dauer jeweils einer Zykluszeit ausführt, als in Zykluszeiten gerechnet, der Datenpfad länger ist. Auf diese Weise wird erreicht, daß der Schreibimpuls für den Arbeitsspeicher stets zeit gerecht erzeugt wird.
摘要翻译：一种改进的数据处理器控制子系统，其中具有多个级联连接级的循环计数器还包括一个或多个补充或虚拟级，其可以从级联连接级链中选择性地插入或移除，以改变子周期，从而降低了相关解码电路的复杂度。

9. 发明公开

EP0129006A3 Detection and correction of multi-chip synchronization errors 失效
标题翻译：多芯片同步错误的检测和校正
公开(公告)号：EP0129006A3
公开(公告)日：1988-01-20
申请号：EP84103513
申请日：1984-03-30
申请人： International Business Machines Corporation
发明人： Oman, Price Ward , Rinaldi, Mark Anthony , Russo, Vito William , Salyer, Gregory
IPC分类号： G06F09/22 , G06F03/04
CPC分类号： G06F13/4217 , G06F9/223 , G06F9/28
摘要： A uniprocessor is formed on plural independently controlled chips (26, 28,30) each including a primary instruction driven controller (84) and a secondary error driven self-sequencing controller (102). Each instruction is supplied in parallel to each primary controller which generates an EXIT signal, as it completes execution, to a common external EXIT line (62). Hardware (116) monitors the local EXIT signal and the common EXIT line state and activates the secondary controller, when a mismatch is detected, to set an on-chip reset predominant error latch (124) driving a common external ERROR line (64), an ERROR-state on which also sets the latches and activates any inactive secondary controller to drive its chip to a first predetermined state and to reset its latch. When no ERROR signal remains, the secondary controllers cycle in synchronism through an ERROR routine, exiting to instruction control.

10. 发明公开

EP0121225A3 Microprogramme control arrangement 失效
标题翻译： FIRMWARE控制设备
公开(公告)号：EP0121225A3
公开(公告)日：1987-10-14
申请号：EP84103395
申请日：1984-03-27
申请人： Siemens Aktiengesellschaft
发明人： Schulte, Franz, Dr.
IPC分类号： G06F09/26 , G06F09/22
CPC分类号： G06F9/262

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式