会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明公开
    • Interprocessor data transfer system and method
    • 系统和Verfahren zurDatenübertragungzwischen Prozessoren。
    • EP0382699A2
    • 1990-08-16
    • EP90850052.3
    • 1990-02-06
    • International Business Machines Corporation
    • Nuechterlein, David WilliamRinaldi, Mark Anthony
    • G06F15/16G06F5/06
    • G06F5/10G06F15/167
    • A system and method for managing a FIFO queue to allow tentative enqueuing of data entities. Additional memory pointers and control logic are provided to allow data entries to be added to a FIFO queue conditionally. Combinatorial logic allows the FIFO queue to be managed so that the tenta­tive or conditional data entries may be purged as a group, committed or made permanent as a group. This system allows an increase in pipeline processor information transfer when several data entities to be transferred are related and the commitment to transfer the group cannot be made until after one or more of the group of data entities have been processed. Selector control are provided so that a system developer can implement management schemes to ensure that the desired function is implemented.
    • 一种用于管理FIFO队列以允许暂时排入数据实体的系统和方法。 提供了附加的存储器指针和控制逻辑以允许有条件地将数据条目添加到FIFO队列中。 组合逻辑允许对FIFO队列进行管理,以使临时条件或条件数据条目可以被清除为一组,被提交或作为一个组成永久的组。 当要传送的几个数据实体相关时,该系统允许流水线处理器信息传送的增加,并且直到一组或多个数据实体被处理之后才能进行转移的承诺。 提供选择器控制,使得系统开发人员可以实现管理方案,以确保实现所需的功能。
    • 5. 发明公开
    • Parallel pipelined computer processor
    • 平行的Pipelinerechner。
    • EP0314342A2
    • 1989-05-03
    • EP88309574.7
    • 1988-10-13
    • International Business Machines Corporation
    • Nuechterlein, David WilliamRinaldi, Mark Anthony
    • G06F15/76
    • G06F15/8092G06F15/8007
    • A processor adapted for parallel and/or pipelined interconnection with other like processors. An arithmetic logic unit has associated with it an output FIFO register stack having output data lines capable of parallel connection with the output data lines of other such processors, such output stack being loadable with a predetermined neutral value such that when said neutral value is present at their output data lines it permits the data present at the output lines of another such processor connected in parallel therewith to control the output data bus. The invention eliminates the need to have control over several such processors connected in parallel and/or pipelined configuration by way of external arbitration logic.
    • 适于与其他类似处理器并行和/或流水线互连的处理器。 算术逻辑单元与其相关联,具有能够与其他这样的处理器的输出数据线并联的输出数据线的输出FIFO寄存器堆栈,这样的输出堆栈可以预定的中性值加载,使得当所述中性值存在于 它们的输出数据线允许存在于并行连接的另一个这样的处理器的输出线上的数据来控制输出数据总线。 本发明消除了通过外部仲裁逻辑控制并联和/或流水线配置的几个这样的处理器的需要。