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1. 发明公开

EP0382699A2 Interprocessor data transfer system and method 失效
标题翻译：系统和Verfahren zurDatenübertragungzwischen Prozessoren。
公开(公告)号：EP0382699A2
公开(公告)日：1990-08-16
申请号：EP90850052.3
申请日：1990-02-06
申请人： International Business Machines Corporation
发明人： Nuechterlein, David William , Rinaldi, Mark Anthony
IPC分类号： G06F15/16 , G06F5/06
CPC分类号： G06F5/10 , G06F15/167
摘要： A system and method for managing a FIFO queue to allow tentative enqueuing of data entities. Additional memory pointers and control logic are provided to allow data entries to be added to a FIFO queue conditionally. Combinatorial logic allows the FIFO queue to be managed so that the tentative or conditional data entries may be purged as a group, committed or made permanent as a group. This system allows an increase in pipeline processor information transfer when several data entities to be transferred are related and the commitment to transfer the group cannot be made until after one or more of the group of data entities have been processed. Selector control are provided so that a system developer can implement management schemes to ensure that the desired function is implemented.
摘要翻译：一种用于管理FIFO队列以允许暂时排入数据实体的系统和方法。提供了附加的存储器指针和控制逻辑以允许有条件地将数据条目添加到FIFO队列中。组合逻辑允许对FIFO队列进行管理，以使临时条件或条件数据条目可以被清除为一组，被提交或作为一个组成永久的组。当要传送的几个数据实体相关时，该系统允许流水线处理器信息传送的增加，并且直到一组或多个数据实体被处理之后才能进行转移的承诺。提供选择器控制，使得系统开发人员可以实现管理方案，以确保实现所需的功能。

2. 发明公开

EP0129006A2 Detection and correction of multi-chip synchronization errors 失效
标题翻译：多芯片同步误差检测和校正。
公开(公告)号：EP0129006A2
公开(公告)日：1984-12-27
申请号：EP84103513.2
申请日：1984-03-30
申请人： International Business Machines Corporation
发明人： Oman, Price Ward , Rinaldi, Mark Anthony , Russo, Vito William , Salyer, Gregory
IPC分类号： G06F13/42 , G06F9/22
CPC分类号： G06F13/4217 , G06F9/223 , G06F9/28
摘要： A uniprocessor is formed on plural independently controlled chips (26, 28,30) each including a primary instruction driven controller (84) and a secondary error driven self-sequencing controller (102). Each instruction is supplied in parallel to each primary controller which generates an EXIT signal, as it completes execution, to a common external EXIT line (62). Hardware (116) monitors the local EXIT signal and the common EXIT line state and activates the secondary controller, when a mismatch is detected, to set an on-chip reset predominant error latch (124) driving a common external ERROR line (64), an ERROR-state on which also sets the latches and activates any inactive secondary controller to drive its chip to a first predetermined state and to reset its latch. When no ERROR signal remains, the secondary controllers cycle in synchronism through an ERROR routine, exiting to instruction control.

3. 发明授权

EP0129006B1 Detection and correction of multi-chip synchronization errors 失效
标题翻译：多芯片同步错误的检测和校正
公开(公告)号：EP0129006B1
公开(公告)日：1991-03-20
申请号：EP84103513.2
申请日：1984-03-30
申请人： International Business Machines Corporation
发明人： Oman, Price Ward , Rinaldi, Mark Anthony , Russo, Vito William , Salyer, Gregory
IPC分类号： G06F13/42 , G06F9/22
CPC分类号： G06F13/4217 , G06F9/223 , G06F9/28

4. 发明公开

EP0382699A3 Interprocessor data transfer system and method 失效
标题翻译：交互式数据传输系统和方法
公开(公告)号：EP0382699A3
公开(公告)日：1992-07-15
申请号：EP90850052.3
申请日：1990-02-06
申请人： International Business Machines Corporation
发明人： Nuechterlein, David William , Rinaldi, Mark Anthony
IPC分类号： G06F15/16 , G06F5/06
CPC分类号： G06F5/10 , G06F15/167
摘要： A system and method for managing a FIFO queue to allow tentative enqueuing of data entities. Additional memory pointers and control logic are provided to allow data entries to be added to a FIFO queue conditionally. Combinatorial logic allows the FIFO queue to be managed so that the tentative or conditional data entries may be purged as a group, committed or made permanent as a group. This system allows an increase in pipeline processor information transfer when several data entities to be transferred are related and the commitment to transfer the group cannot be made until after one or more of the group of data entities have been processed. Selector control are provided so that a system developer can implement management schemes to ensure that the desired function is implemented.

5. 发明公开

EP0314342A2 Parallel pipelined computer processor 失效
标题翻译：平行的Pipelinerechner。
公开(公告)号：EP0314342A2
公开(公告)日：1989-05-03
申请号：EP88309574.7
申请日：1988-10-13
申请人： International Business Machines Corporation
发明人： Nuechterlein, David William , Rinaldi, Mark Anthony
IPC分类号： G06F15/76
CPC分类号： G06F15/8092 , G06F15/8007
摘要： A processor adapted for parallel and/or pipelined interconnection with other like processors. An arithmetic logic unit has associated with it an output FIFO register stack having output data lines capable of parallel connection with the output data lines of other such processors, such output stack being loadable with a predetermined neutral value such that when said neutral value is present at their output data lines it permits the data present at the output lines of another such processor connected in parallel therewith to control the output data bus. The invention eliminates the need to have control over several such processors connected in parallel and/or pipelined configuration by way of external arbitration logic.
摘要翻译：适于与其他类似处理器并行和/或流水线互连的处理器。算术逻辑单元与其相关联，具有能够与其他这样的处理器的输出数据线并联的输出数据线的输出FIFO寄存器堆栈，这样的输出堆栈可以预定的中性值加载，使得当所述中性值存在于它们的输出数据线允许存在于并行连接的另一个这样的处理器的输出线上的数据来控制输出数据总线。本发明消除了通过外部仲裁逻辑控制并联和/或流水线配置的几个这样的处理器的需要。

6. 发明授权

EP0314342B1 Parallel pipelined computer processor 失效
标题翻译：并行流水线计算机。
公开(公告)号：EP0314342B1
公开(公告)日：1995-03-08
申请号：EP88309574.7
申请日：1988-10-13
申请人： International Business Machines Corporation
发明人： Nuechterlein, David William , Rinaldi, Mark Anthony
IPC分类号： G06F15/76
CPC分类号： G06F15/8092 , G06F15/8007

7. 发明公开

EP0314342A3 Parallel pipelined computer processor 失效
标题翻译：并行管道计算机处理器
公开(公告)号：EP0314342A3
公开(公告)日：1990-10-17
申请号：EP88309574.7
申请日：1988-10-13
申请人： International Business Machines Corporation
发明人： Nuechterlein, David William , Rinaldi, Mark Anthony
IPC分类号： G06F15/76
CPC分类号： G06F15/8092 , G06F15/8007
摘要： A processor adapted for parallel and/or pipelined interconnection with other like processors. An arithmetic logic unit has associated with it an output FIFO register stack having output data lines capable of parallel connection with the output data lines of other such processors, such output stack being loadable with a predetermined neutral value such that when said neutral value is present at their output data lines it permits the data present at the output lines of another such processor connected in parallel therewith to control the output data bus. The invention eliminates the need to have control over several such processors connected in parallel and/or pipelined configuration by way of external arbitration logic.

8. 发明公开

EP0129006A3 Detection and correction of multi-chip synchronization errors 失效
标题翻译：多芯片同步错误的检测和校正
公开(公告)号：EP0129006A3
公开(公告)日：1988-01-20
申请号：EP84103513
申请日：1984-03-30
申请人： International Business Machines Corporation
发明人： Oman, Price Ward , Rinaldi, Mark Anthony , Russo, Vito William , Salyer, Gregory
IPC分类号： G06F09/22 , G06F03/04
CPC分类号： G06F13/4217 , G06F9/223 , G06F9/28
摘要： A uniprocessor is formed on plural independently controlled chips (26, 28,30) each including a primary instruction driven controller (84) and a secondary error driven self-sequencing controller (102). Each instruction is supplied in parallel to each primary controller which generates an EXIT signal, as it completes execution, to a common external EXIT line (62). Hardware (116) monitors the local EXIT signal and the common EXIT line state and activates the secondary controller, when a mismatch is detected, to set an on-chip reset predominant error latch (124) driving a common external ERROR line (64), an ERROR-state on which also sets the latches and activates any inactive secondary controller to drive its chip to a first predetermined state and to reset its latch. When no ERROR signal remains, the secondary controllers cycle in synchronism through an ERROR routine, exiting to instruction control.

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