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1. 发明公开

EP0178671A3 Distributed control store architecture 有权转让
标题翻译：分布式控制存储架构
公开(公告)号：EP0178671A3
公开(公告)日：1988-08-17
申请号：EP85113207
申请日：1985-10-17
申请人： Honeywell Bull Inc.
发明人： Kelly, Richard P. , Joyce, Thomas F.
IPC分类号： G06F09/26
CPC分类号： G06F9/26 , G06F9/268 , G06F9/28
摘要： A method and apparatus for a microinstruction controi- led unit having multiple subunits which are controlled bv microoperations encoded within microinstructions from a control store. One master subunit controls the order in which the microinstructions are executea by generating the address of the next microinstruction to be read from the control store. The method provides for the overlapping of the execution of a current microinstruction while the next microinstruction is being addressed and read from the control store. The control store is divided into control substores with each control substore iocated near the subunit which executes the microcperations stored in its associated control substore. Subunits can atrect the order of microinstruction execution by causing a trad in the master subunit which will cause the next microinstruction to be read from a predefined address within the control store If required, the master subunit can read in status information from the subunits in order to determine the condition within the subunits that caused tne trap to occur. A means is provided for storing a return address which aliows to execution to continue at the next microinstruction that wot have executed had a trap not occurred.

2. 发明公开

EP0111113A3 Device for the preparation of a continual address for a micro-progamme-controlled sequencer, and method for its operation 有权
标题翻译：用于准备微控制序列的连续地址的设备及其操作方法
公开(公告)号：EP0111113A3
公开(公告)日：1984-09-26
申请号：EP83110381
申请日：1983-10-18
申请人： Siemens Aktiengesellschaft
发明人： Stadlmeier, Hans, Dipl.-Ing.
IPC分类号： G06F09/26
CPC分类号： G06F9/268

3. 发明公开

EP0037935A3 Sequence control circuit for a computer 失效
标题翻译：计算机的序列控制电路
公开(公告)号：EP0037935A3
公开(公告)日：1982-10-13
申请号：EP81102234
申请日：1981-03-25
申请人： NORTHERN TELECOM LIMITED
发明人： Johnson, Courtenay Philip
IPC分类号： G06F09/26 , G06F09/28
CPC分类号： G06F9/262
摘要： Wait and skip commands in a digital computer are controlled by logic circuitry which performs the following functions in response to a skip command.
(a) One of the computer's clocks is halted, (b) data bits in the microinstruction word are inhibited and predetermined data bits are substituted therefor. The logic circuitry performs the following functions in response to a wait command. (a) One of the computer's clocks is halted until the operation that is being waited upon is completed.

4. 发明公开

EP0172493A3 Information processing system 失效
标题翻译：信息处理系统
公开(公告)号：EP0172493A3
公开(公告)日：1988-02-10
申请号：EP85109933
申请日：1981-03-12
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kinoshita, Tsuneo , Sato, Fumitaka , Yamazaki, Isamu
IPC分类号： G06F09/26
CPC分类号： G06F13/4018 , G06F13/4217 , G06F15/7832
摘要： The invention relates to an information processing system comprising an arithmetic control unit (101) fabricated on one chip including means for receiving the op code of a user instruction. An instruction system comprises a first control memory (102) in which can be stored a plurality of microprograms each comprising a plurality of microinstructions for controlling said arithmetic control unit (101) in response to op codes in user instructions, said first control memory being externally coupled to said arithmetic control unit (101), and a second control memory disposed in said one-chip arithmetic control unit (1019) in which can be stored identifier information indicating one of the following: that the op code in a user instruction can be executed in one step; that the op code in a user instruction is an illegal instruction; and that the op code in a user instruction requires two or more steps for execution in which case the identifier information includes address information for the second step of the two or more steps. Each microinstruction stored In said first control memory (102) designates a memory location in said second control memory in response to the op code of a respective user instruction. Reading means reads a microinstruction from said first control memory and an identifier Information from said second control memory designated by that microinstruction in response to op codes of user instructions. The information processing system further comprises means for enabling and disabling the second control memory in response to a signal externally coupled to said arithmetic control unit (101), whereby said information processing system is operable with said instruction system in which identifier information in the second control memory is accessed when the second control memory is enabled, and with another instruction system when the second control memory is disabled.

5. 发明公开

EP0121225A3 Microprogramme control arrangement 失效
标题翻译： FIRMWARE控制设备
公开(公告)号：EP0121225A3
公开(公告)日：1987-10-14
申请号：EP84103395
申请日：1984-03-27
申请人： Siemens Aktiengesellschaft
发明人： Schulte, Franz, Dr.
IPC分类号： G06F09/26 , G06F09/22
CPC分类号： G06F9/262

6. 发明公开

EP0080901A3 Data processing apparatus 有权转让
标题翻译：数据处理设备
公开(公告)号：EP0080901A3
公开(公告)日：1986-04-02
申请号：EP82306383
申请日：1982-12-01
申请人： Honeywell Information Systems Inc.
发明人： Woods, William E. , Stanley, Philip E.
IPC分类号： G06F09/30 , G06F09/26
CPC分类号： G06F9/30192 , G06F9/26 , G06F9/268
摘要： A data processing system includes a microprogram controlled central processing unit that executes instructions. The instruction words include a data type field for identifying the type of operand processed during the execution of the instruction. The data type field signals and a number of control signals are applied to the address terminals of a read only memory. The read only memory output signals are tested by microwords of a microprogram to branch to firmware routines to process the operand type.

7. 发明公开

EP0087005A3 Microword control mechanism utilizing a programmable logic array and a sequence counter 失效
标题翻译：使用可编程逻辑阵列和序列计数器的MICROWORD控制机制
公开(公告)号：EP0087005A3
公开(公告)日：1983-11-16
申请号：EP83100908
申请日：1983-02-01
申请人： International Business Machines Corporation
发明人： Leininger, Joel Calvin , Moore, Victor Stewart , Stahl, William L., Jr.
IPC分类号： G06F09/26
CPC分类号： G06F9/262
摘要： A microword control mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed data processor. This microword control mechanism includes circuitry (15, 20) responsive to a processor instruction to be executed for providing an instruction dependent signal uniquely representative of such instruction. This microword control mechanism also includes sequence counter circuitry (18) for supplying a sequence of -number signals. This microword control mechanism further includes a programmable logic array (17) responsive to the instruction dependent signal and to the sequence of number signals for producing a sequence of microwords needed to execute the processor instruction.

8. 发明公开

EP0073004A3 Method for the operation of a CPU of a digital multibit computer system and the CPU for carrying out this method of operation 有权
标题翻译：用于数字多计算机系统的CPU的操作的方法和用于执行该操作方法的CPU
公开(公告)号：EP0073004A3
公开(公告)日：1983-07-06
申请号：EP82107477
申请日：1982-08-17
申请人： Müller, Otto
发明人： Müller, Otto
IPC分类号： G06F09/26
CPC分类号： G06F9/265 , G06F9/223

9. 发明公开

EP0019392A3 Instruction register sequence decoder for microprogrammed data processor and method 失效
标题翻译：微处理数据处理器和方法的指令寄存器序列解码器
公开(公告)号：EP0019392A3
公开(公告)日：1981-06-10
申请号：EP80301418
申请日：1980-04-30
申请人： MOTOROLA, INC.
发明人： Tredennick, Harry Leslie , Gunter, Thomas Glen
IPC分类号： G06F09/26
CPC分类号： G06F9/30094 , G06F9/262 , G06F9/264 , G06F9/268 , G06F9/30 , G06F9/30061 , G06F9/30145 , G06F9/30167
摘要： A data processor using microprogrammed control to execute a plurality of macroinstructions and including an instruction register (10) for storing a macroinstruction, received from a program memory, a control store including a micro control store (18) and a nano control store (20) and for storing a plurality of microinstruction routines, each including one or more microinstructions for controlling operations performed by the data processor, and each of the microinstruction routines being associated with a corresponding starting address and an instruction register sequence decoder (14) coupled to an address selection block (16) which is coupled via a line (17) to the control store (18, 20), the decoder (14) being responsive to the macroinstruction stored by the Instruction register (10) for providing a plurality of starting addresses associated with the stored macroinstruction, the decoder (14) effectively causing the data processor to perform each of the microinstruction routines associated with the starting addresses provided by the decoder (14) in order to execute the macroinstruction stored in the instruction register (10).

10. 发明公开

EP0159699A3 A data processor executing microprograms according to a plurality of system architectures 失效
标题翻译：数据处理器根据多种系统架构执行微处理器
公开(公告)号：EP0159699A3
公开(公告)日：1988-09-28
申请号：EP85104935
申请日：1985-04-23
申请人： NEC CORPORATION
发明人： Iwata, Jun
IPC分类号： G06F09/44 , G06F09/30 , G06F09/26
CPC分类号： G06F9/30145 , G06F9/268 , G06F9/3017
摘要： A data processor controlled by microprograms which can run a desired program in a selected one of multiple system architectural modes. In the data processor, the operation code of the instruction is used as an address for a decoding information storage which stores a plurality of pairs of a microinstruction start address and an editing format control word. A selector selects a pair of a start microinstruction address and an editing format control word. The microinstruction start address is used for accessing a microcode control storage storing a plurality of microprograms in microinstruction form. The editing format control is used as a editing designation signal for editing the operand of the instruction according to the selected mode.

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