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1. 发明公开

EP0178671A3 Distributed control store architecture 失效
标题翻译：分布式控制存储架构
公开(公告)号：EP0178671A3
公开(公告)日：1988-08-17
申请号：EP85113207
申请日：1985-10-17
申请人： Honeywell Bull Inc.
发明人： Kelly, Richard P. , Joyce, Thomas F.
IPC分类号： G06F09/26
CPC分类号： G06F9/26 , G06F9/268 , G06F9/28
摘要： A method and apparatus for a microinstruction controi- led unit having multiple subunits which are controlled bv microoperations encoded within microinstructions from a control store. One master subunit controls the order in which the microinstructions are executea by generating the address of the next microinstruction to be read from the control store. The method provides for the overlapping of the execution of a current microinstruction while the next microinstruction is being addressed and read from the control store. The control store is divided into control substores with each control substore iocated near the subunit which executes the microcperations stored in its associated control substore. Subunits can atrect the order of microinstruction execution by causing a trad in the master subunit which will cause the next microinstruction to be read from a predefined address within the control store If required, the master subunit can read in status information from the subunits in order to determine the condition within the subunits that caused tne trap to occur. A means is provided for storing a return address which aliows to execution to continue at the next microinstruction that wot have executed had a trap not occurred.

2. 发明公开

EP0111113A3 Device for the preparation of a continual address for a micro-progamme-controlled sequencer, and method for its operation 失效
标题翻译：用于准备微控制序列的连续地址的设备及其操作方法
公开(公告)号：EP0111113A3
公开(公告)日：1984-09-26
申请号：EP83110381
申请日：1983-10-18
申请人： Siemens Aktiengesellschaft
发明人： Stadlmeier, Hans, Dipl.-Ing.
IPC分类号： G06F09/26
CPC分类号： G06F9/268

3. 发明公开

EP0037935A3 Sequence control circuit for a computer 失效
标题翻译：计算机的序列控制电路
公开(公告)号：EP0037935A3
公开(公告)日：1982-10-13
申请号：EP81102234
申请日：1981-03-25
申请人： NORTHERN TELECOM LIMITED
发明人： Johnson, Courtenay Philip
IPC分类号： G06F09/26 , G06F09/28
CPC分类号： G06F9/262
摘要： Wait and skip commands in a digital computer are controlled by logic circuitry which performs the following functions in response to a skip command.
(a) One of the computer's clocks is halted, (b) data bits in the microinstruction word are inhibited and predetermined data bits are substituted therefor. The logic circuitry performs the following functions in response to a wait command. (a) One of the computer's clocks is halted until the operation that is being waited upon is completed.

4. 发明公开

EP0180476A3 Microprogramme sequence controller 失效
标题翻译：微控制器序列控制器
公开(公告)号：EP0180476A3
公开(公告)日：1988-11-09
申请号：EP85307899
申请日：1985-10-31
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Moller, Ole
IPC分类号： G06F09/26
CPC分类号： G06F9/268 , G06F13/24
摘要： A single-chip microprogram sequence controller which can be selectively operated in either an interrupt mode or a trapped mode. In the interrupt mode, the microprogram sequencer allows the currently-executing microinstruction to finish execution before beginning the interrupt routine which services the asynchronous event which requested the interruption of the presently-executing microinstruction stream. In the trap mode, the sequencer aborts the currently-executing microinstruction to avoid an irreversible error which would result if the microinstruction were to finish execution before beginning the routine which services the event which requested trapping of the presently-executing microinstruction. Depending on the mode selected, the sequencer stores the address on a last-in, first-out stack of either the next-following microinstruction or the currently-executing microinstruction for return to the proper point in the microinstruction stream upon completion of the routine which requested the interrupt or the trap.

5. 发明公开

EP0138352A3 Method of operating a data processing system via depictor-linked microcode and logic circuitry 失效
标题翻译：通过连接的微处理器和逻辑电路操作数据处理系统的方法
公开(公告)号：EP0138352A3
公开(公告)日：1988-03-16
申请号：EP84305968
申请日：1984-08-31
申请人： UNISYS CORPORATION
发明人： Green, Howard Hunt , Tomlinson, Christopher Jerome
IPC分类号： G06F09/42 , G06F09/26
CPC分类号： G06F9/4486
摘要： © A method of operating a data processing system includes the steps of: executing one high level language software program until an instruction is encountered which calls and activity; sensing whether said encountered instruction is linked to the activity which it calls by a first type or a second type depictor; executing another high level language software program for performing the called activity if the sensing step detects the first type depictor; and activating a low level language microcode program or hardware logic circuit for performing the called activity if the sensing step detects the second type depictor.

6. 发明公开

EP0111161A3 Device for initiating microinstructions for at least two independently working function units in an integrated microprogrammed electronic module, and method for its operation 失效
标题翻译：一体化微电脑电子模块中的至少两个独立工作功能单元启动微指令的设备及其操作方法
公开(公告)号：EP0111161A3
公开(公告)日：1986-11-26
申请号：EP83111105
申请日：1983-11-07
申请人： Siemens Aktiengesellschaft
发明人： Stadlmeier, Hans, Dipl.-Ing. , Schönberger, Franz, Dipl.-Ing.
IPC分类号： G06F09/26 , G06F13/28 , G06F13/12
CPC分类号： G06F9/268 , G06F13/28

7. 发明公开

EP0087008A3 Operation code decoding device with a plurality of programmable logic arrays 失效
标题翻译：操作码解码器具有多个可编程逻辑阵列
公开(公告)号：EP0087008A3
公开(公告)日：1983-11-16
申请号：EP83100913
申请日：1983-02-01
申请人： International Business Machines Corporation
发明人： Thoma, Nandor G. , Moore, Victor Stewart , Kraft, Wayne Richard
IPC分类号： G06F09/26
CPC分类号： G06F9/267
摘要： The decoding device comprises a plurality of programmable logic arrays (20-24) operating in parallel, each to decode an operation code (OP code) of a given instruction class. A portion of the OP code is decoded by a decode multiplexer (40) to select one of the PLA's, and the decoded OP code from the selected PLA is gated through a N-way multiplexer (42) to provide the control code corresponding to the OP code.

8. 发明公开

EP0035334A3 Data processing system with two level microprogramming and frequency synthesisers 失效
标题翻译：具有两级微控制和频率合成器的数据处理系统
公开(公告)号：EP0035334A3
公开(公告)日：1981-12-09
申请号：EP81300560
申请日：1981-02-11
申请人： DATA GENERAL CORPORATION
发明人： Bernstein, David H. , Carberry, Richard A. , Druke, Michael B. , Gusowski, Ronald I. , Buckley, Edward M. , March, Roger W.
IPC分类号： G06F09/26 , G06F03/04 , H03K05/156
CPC分类号： H03K23/667 , G06F9/26 , G06F9/268 , G06F13/22 , G06F13/36 , G06F13/4027 , G06F13/42 , G06F13/4217
摘要： The central processing unit of a data processing system employs a decoder 40 to decode macroinstructions held in an instruction register 19 under the control of a program counter 20. Each decoded macroinstruction provides a sequence of first microinstructions on an 18-bit bus 39. Each first microinstruction comprises a 4-bit address field applied to a sequencer 33 which also receives bits from the decoder 40 and addresses a ROM 31 which provides the first microinstructions. A 6-bit field of each first microinstruction addresses another ROM 32 which provides one of 64 second microinstructions of 33 bits each, HORM O-32. Fields of the second microinstructions are modified in accordance with two 4-bit modifier fields V1 and V2 from the first microinstruction in a modification circuit 34 which provides 35-bit output microinstructions HCOMT 0-34. These output microinstructions are applied to a decoder 35 whose outputs control the machine states of the CPU. A system bustiming system and a frequency synthesizer are also provided.
摘要翻译：数据处理系统的中央处理单元采用解码器40在程序计数器20的控制下解码保存在指令寄存器19中的宏指令。每个解码的宏指令在18位总线39上提供一系列第一微指令。微指令包括应用于定序器33的4位地址字段，其也从解码器40接收位，并寻址提供第一微指令的ROM 31。每个第一微指令的6位字段寻址另一个ROM 32，其提供64位每个33位的第二微指令之一，HORM O-32。根据提供35位输出微指令HCOMT 0-34的修改电路34，根据来自第一微指令的两个4位修改器字段V1和V2修改第二微指令的字段。这些输出微指令被应用于其输出控制CPU的机器状态的解码器35。还提供了系统稳定系统和频率合成器。

9. 发明公开

EP0031743A3 Control device for micro-instructions recorded in a memory of an information processing unit 失效
标题翻译：用于在信息处理单元的存储器中记录的微指令的控制装置
公开(公告)号：EP0031743A3
公开(公告)日：1981-07-15
申请号：EP80401740
申请日：1980-12-05
申请人： COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII - HONEYWELL BULL (dite CII-HB)
发明人： Cassonnet, Jean-Claude Marcel , Lamarche, Marie-Odile née Lechevin
IPC分类号： G06F09/26
CPC分类号： G06F9/261

10. 发明公开

EP0159699A3 A data processor executing microprograms according to a plurality of system architectures 失效
标题翻译：数据处理器根据多种系统架构执行微处理器
公开(公告)号：EP0159699A3
公开(公告)日：1988-09-28
申请号：EP85104935
申请日：1985-04-23
申请人： NEC CORPORATION
发明人： Iwata, Jun
IPC分类号： G06F09/44 , G06F09/30 , G06F09/26
CPC分类号： G06F9/30145 , G06F9/268 , G06F9/3017
摘要： A data processor controlled by microprograms which can run a desired program in a selected one of multiple system architectural modes. In the data processor, the operation code of the instruction is used as an address for a decoding information storage which stores a plurality of pairs of a microinstruction start address and an editing format control word. A selector selects a pair of a start microinstruction address and an editing format control word. The microinstruction start address is used for accessing a microcode control storage storing a plurality of microprograms in microinstruction form. The editing format control is used as a editing designation signal for editing the operand of the instruction according to the selected mode.

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