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1. 发明公开

EP0124402A2 Microprocessor 失效
标题翻译：微处理器。
公开(公告)号：EP0124402A2
公开(公告)日：1984-11-07
申请号：EP84400629.6
申请日：1984-03-28
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Damouny, Nabil G. , Huang, Min-Siu , Mor, Yeshayahu , Lynn, Henry C. , Wilnai, Dan , Mladejovsky, Michael G. , Pilzer, Yeffi
IPC分类号： G06F9/26 , G06F9/28 , G06F9/30 , G06F3/04 , G06F7/52
CPC分类号： G06F7/5338 , G06F7/4991 , G06F9/261 , G06F9/265 , G06F9/268 , G06F9/3861 , G06F13/26 , G06F13/364
摘要： A microprocessor data processing system (1700) includes system units (50,1704) connected to a bus (1702), with a bus arbiter (1712) and a protocol for assigning bus access to the system units (50, 1704). The microprocessor (50) executes both arithmetic operations and floating point operations. A microcontrol store (162) stores common instructions usable in different floating point operations. A PLA (180) supplies addresses to microcontrol store (162) and provides a signal indicating floating point instruction type. The microprocessor (50) includes a pending interrupt register (250) connected to mask and enable logic (268). The mask and enable logic (268) is connected to a priority encoder (278), which is connected to an interrupt latch (282). The latch (282) supplies outputs to generate a current state storage address. Branch control logic (1938) receives branch conditions inputs and branch control information and generates control signals for a next microaddress multiplexer (1934) in a pipelined instruction path. Microinstructions for the microprocessor (50) are stored for different operations in a microcontrol store (16) with common usage of identical microinstructions for the different operations. A 17th bit auxiliary ALU (1062) in combination with a 16 bith ALU (62) Booth encoder (1074) and overflow logic (1152) implements the modified Booth two shift multiply algorithm. A reduced size constants ROM (120) is provided by generating 28 required constants in the microprocessor with only 5 stored constants through use of a shifter (1066) and a mask (1068). Latches (632) and (634) may be made transparent to reduce execution times in restarts and sequential single microcycle instructions. ALU (62) modifies addresses in instruction counter (200) by subtracting an identifying portion of an aborted microinstruction. Microcode addresses for different types of operations are stored in a mapping PLA (150) by utilizing unused portions of one type of operation address for storing another type of operation address.

2. 发明公开

EP0108664A3 Floating point microprocessor 失效
标题翻译：浮点微处理器
公开(公告)号：EP0108664A3
公开(公告)日：1987-10-28
申请号：EP83401935
申请日：1983-10-04
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Ayalew Melesse , Burke, Gary , Dante III, Edward , Dao, Tich , Davidesko, Itzhak , Kayruz, Camille , Mor, Yeshayahu
IPC分类号： G06F09/22 , G06F07/48 , G06F09/26
CPC分类号： G06F9/26 , G06F7/483
摘要： A microprocessor integrated circuit (50) includes a control, timing and interface section (52) connected by control signal lines (54) to each of the other functional elements shown. Section (52) is further connected to a 16-bit wide internal information bus (56) by bus (58). Bus (60) also connects the section (52) to a 16-bit wide external information bus (62). Buffer circuit (64) connects the external information bus (62) to the internal information bus (56). The internal information bus (56) is connected by bus (66) to a programmable shifter and unpacker section (68). The section (68) is connected to a Mantissa processor (70) by a 64-bit wide bus (72) and by two 32-bit wide buses (74) and (76). The shifter (68) is connected to an exponent processor (78) by 16-bit wide buses (80) and (82). The Mantissa processor (70) is also connected to the internal information bus (56) by bus (84). The sign logic circuits (86) are connected to the programmable shifter and unpacker section (68) by line (88). Mantissa processor (70) includes a 32-bit arithmetic and logic unit (ALU), a variable width register file, working registers and flipflops, control PLAs, detection logic and bus buffers. The exponent and sign processor (78) includes a 16-bit wide ALU, variable width register file, working registers, control and constants PLAs detection logic and sign logic and flipflops. The programmable shifter and unpacker (68) is a 64-bit wide shifter capable of shifting in one machine cycle from 0 to 8 positions to the left or 0 to 24 positions to the right. The control timing and interface section (52) is based on a two-level microprogramming scheme to save microcode and to optimize execution times on a dynamic microcycle.
摘要翻译：微处理器集成电路（50）包括通过控制信号线（54）连接到所示其它功能元件的控制，定时和接口部分（52）。部分（52）还通过总线（58）连接到16位宽的内部信息总线（56）。总线（60）还将部分（52）连接到16位宽的外部信息总线（62）。缓冲电路（64）将外部信息总线（62）连接到内部信息总线（56）。内部信息总线（56）通过总线（66）连接到可编程移位器和解包器部分（68）。部分（68）通过64位宽总线（72）和两个32位宽总线（74）和（76）连接到尾数处理器（70）。移位器（68）通过16位宽的总线（80）和（82）连接到指数处理器（78）。尾数处理器（70）也通过总线（84）连接到内部信息总线（56）。符号逻辑电路（86）通过线路（88）连接到可编程移位器和解包器部分（68）。尾数处理器（70）包括32位算术和逻辑单元（ALU），可变宽度寄存器文件，工作寄存器和触发器，控制PLA，检测逻辑和总线缓冲器。指数和符号处理器（78）包括16位宽的ALU，可变宽度寄存器文件，工作寄存器，控制和常数PLA检测逻辑和符号逻辑和触发器。可编程移位器和解包器（68）是一个64位宽移位器，能够在一个机器周期中从0到8个位置向左移位或0到24个位置向右移位。控制定时和接口部分（52）基于两级微程序方案来保存微代码以优化在动态微循环上的执行时间。

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