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1. 发明授权

EP0110227B1 Control memory organization 失效
标题翻译：控制存储器组织
公开(公告)号：EP0110227B1
公开(公告)日：1986-07-16
申请号：EP83111360.0
申请日：1983-11-14
申请人： HONEYWELL INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Maccianti, Tiziano , Balasini, Flavio
IPC分类号： G06F9/22
CPC分类号： G06F9/30145 , G06F9/226 , G06F9/267 , G06F9/268 , G06F9/30167

2. 发明授权

EP0042082B1 Microprogram sequencer for microprogrammed control unit 失效
标题翻译：微控制器微控制器序列器
公开(公告)号：EP0042082B1
公开(公告)日：1984-05-16
申请号：EP81103979.1
申请日：1981-05-23
申请人： HONEYWELL INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Zanchi, Vittorio , Maccianti, Tiziano
IPC分类号： G06F9/26
CPC分类号： G06F9/268

3. 发明公开

EP0110227A3 Control memory organization 失效
标题翻译：控制存储器组织
公开(公告)号：EP0110227A3
公开(公告)日：1984-07-25
申请号：EP83111360
申请日：1983-11-14
申请人： HONEYWELL INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Maccianti, Tiziano , Balasini, Flavio
IPC分类号： G06F09/22
CPC分类号： G06F9/30145 , G06F9/226 , G06F9/267 , G06F9/268 , G06F9/30167
摘要： in a microprogrammed data processing system wherein the execution of a microinstruction sequence may be interrupted at any time for the execution of a more prioritary microinstruction sequence, the control memory is organized in such a way as to provide microinstructions of variable length. The basic length of the microinstructions is defined by the parallelism of a first control memory (1). With regard to a first range of addresses of the first control memory, a second control memory (17), read in parallel to the first one, provides a microinstruction field which is added to the basic field of the first memory and increases the microinstruction length. With regard to the remaining field of addresses of the first control memory, a first microinstruction may load with one of its bit fields a register (22). Then such bit field is associated to the subsequent microinstruction for increasing the length of it. In this case, in order to avoid that the execution of such longer subsequent microinstruction be affected by a microprogram interruption occurring within the execution of the first microinstruction and the reading out of the subsequent one, some logic circuits (25, 26, 27, 28, 29, 30) defers, in case of interruption, the association of the bit field to the subsequent microinstruction till the return to the interrupted microprogram.

4. 发明公开

EP0110227A2 Control memory organization 失效
标题翻译： Steuerspeicherorganisation。
公开(公告)号：EP0110227A2
公开(公告)日：1984-06-13
申请号：EP83111360.0
申请日：1983-11-14
申请人： HONEYWELL INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Maccianti, Tiziano , Balasini, Flavio
IPC分类号： G06F9/22
CPC分类号： G06F9/30145 , G06F9/226 , G06F9/267 , G06F9/268 , G06F9/30167
摘要： in a microprogrammed data processing system wherein the execution of a microinstruction sequence may be interrupted at any time for the execution of a more prioritary microinstruction sequence, the control memory is organized in such a way as to provide microinstructions of variable length.
The basic length of the microinstructions is defined by the parallelism of a first control memory (1).
With regard to a first range of addresses of the first control memory, a second control memory (17), read in parallel to the first one, provides a microinstruction field which is added to the basic field of the first memory and increases the microinstruction length.
With regard to the remaining field of addresses of the first control memory, a first microinstruction may load with one of its bit fields a register (22).
Then such bit field is associated to the subsequent microinstruction for increasing the length of it.
In this case, in order to avoid that the execution of such longer subsequent microinstruction be affected by a microprogram interruption occurring within the execution of the first microinstruction and the reading out of the subsequent one, some logic circuits (25, 26, 27, 28, 29, 30) defers, in case of interruption, the association of the bit field to the subsequent microinstruction till the return to the interrupted microprogram.
摘要翻译：在微程序化的数据处理系统中，微指令序列的执行可以在任何时间被中断以执行更为优先的微指令序列，控制存储器被组织成提供可变长度的微指令。微指令的基本长度由第一控制存储器（1）的并行度定义。 ...关于第一控制存储器的第一范围的地址，与第一控制存储器并行读取的第二控制存储器（17）提供微指令字段，其被添加到第一存储器的基本字段并增加微指令长度。 ...关于第一控制存储器的剩余的地址字段，第一微指令可以与其位字段之一加载寄存器（22）。然后，这样的位域与随后的微指令相关联，以增加其长度。在这种情况下，为了避免这种更长的后续微指令的执行受到在第一微指令的执行期间发生的微程序中断和随后的读出的影响，一些逻辑电路（25， 26,27,28,29,30）在中断的情况下，将比特字段与随后的微指令相关联，直到返回到中断的微程序。

5. 发明公开

EP0042082A1 Microprogram sequencer for microprogrammed control unit 失效
标题翻译：对于固件配置微程序序列控制器。
公开(公告)号：EP0042082A1
公开(公告)日：1981-12-23
申请号：EP81103979.1
申请日：1981-05-23
申请人： HONEYWELL INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Zanchi, Vittorio , Maccianti, Tiziano
IPC分类号： G06F9/26
CPC分类号： G06F9/268
摘要： A microprogram sequencer for microprogrammed control unit develops microprogram consecutive addresses, branches to subroutines with address saving and possible return to microprogram, as well as interrupting microprogram forcings with address saving of the interrupted microprograms.
In order to allow the double saving of microprogram and subroutine addresses in case of concurrent interruptions and branches, the sequencer is provided with two address generation loops each including a register. The two loops have a common portion to which they accede through a multiplexer (23).
The first loop (23, 25, 22, 21, 30, 31) is further coupled to a saving register stack (20).
While the first loop executes the saving of a microprogram address and the latching of a branch address received from the second loop, the second loop (23, 25, 24, 39, 17, 18, 42, 19, 27, 29) executes a first updating and-, related latching of interrupting microprogram address. During the following cycle, by command of the first microinstruction of the interrupting microprogram, the second loop performs a first updating and related latch of the interrupting microprogram address and the first loop saves into the register stack (20) the branch address and performs a second updating and related latching of the interrupting microprogram address.

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