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1. 发明公开

EP0399431A3 Neuronale Netzwerkarchitektur 失效
标题翻译：神经网络架构
公开(公告)号：EP0399431A3
公开(公告)日：1991-07-03
申请号：EP90109590.1
申请日：1990-05-21
申请人： Alcatel SEL Aktiengesellschaft , ALCATEL N.V.
发明人： Hackbarth, Heidi, Dr. , Thierer, Gebhard, Dr. , Krause, Andreas, Dr.
IPC分类号： G10L9/00 , G06F15/06
CPC分类号： G06N3/04 , G10L15/16
摘要： Zur automatischen Mustererkennung weist ein neuronales Netzwerk eine Eingangsschicht (IL) auf (zweidimensionales Feld aus M×N Elementen, M=Anzahl der Merkmalsvektoren, N=Anzahl der Koeffizienten je Merkmalsvektor), die in sich überlappende Mustersegmente (LH×LV, mit LH Die verborgene Schicht (HL) wird dann mit einer eindimensionalen Ausgangsschicht (OL) vollvernetzt, wobei das Element der Ausgangsschicht, das den größten Summenwert aufweist, dem zu erkennenden Muster entspricht.

2. 发明公开

EP0335502A3 Microcontroller and associated method 失效
标题翻译：微控制器及相关方法
公开(公告)号：EP0335502A3
公开(公告)日：1991-07-03
申请号：EP89301921.6
申请日：1989-02-27
申请人： ADVANCED MICRO DEVICES, INC.
发明人： O'Dell, Robert W. , Allen, Bruce Randal , Oliver, Arthur Benjamin , O'Brien, Robert O. , Kamath, Govinda V.
IPC分类号： G06F15/06 , G06F13/42
CPC分类号： G06F15/7814
摘要： A VLSI microcontroller is provided which comprises: a processor for processing digital information; storage circuitry for storing digital information; an internal bus for conducting digital information to and from the processor and the storage circuitry; a plurality of first external terminals; transfer circuitry for transferring digital information between the internal bus and the plurality of external terminals, the transfer circuitry being operable in either a bus mode or a port mode; wherein the transfer circuitry in the bus mode is responsive to first digital information conducted on the internal bus; and wherein the transfer circuitry in the port mode is response to second digital information conducted on said internal bus.

3. 发明公开

EP0334627A3 Multiprocessor architecture 失效
标题翻译：多处理器架构
公开(公告)号：EP0334627A3
公开(公告)日：1991-06-12
申请号：EP89302830.8
申请日：1989-03-22
申请人： DU PONT PIXEL SYSTEMS LIMITED
发明人： Baldwin, David Robert , Kent, Osman , Ahishalilar, Yavuz
IPC分类号： G06F15/16 , G06F15/06
CPC分类号： G06F9/3879 , G06F9/3877 , G06F15/8069
摘要： A numeric processing subsystem, where at least three processors concurrently run separate processes. One of the three is a control processor (110), one is a data transfer processor (120), which controls the external interface, and one or several are numeric processors (130). Preferably this subsystem also includes at least a megabyte of cache memory (140), which is linked to the floating-point processor by a very high-bandwidth bus. The interface to the numeric processor(s) is so constrained that a variety of integrated circuits can be readily substituted. To compensate for the different pin-out and routing requirements of different chips, exchangeable subboards are preferably used to mount the arithmetic chips. To achieve this chip-independence without sacrificing speed, an extremely flexible and highly multiported register file is used at the interface from the cache memory (140) to the numeric processing subsystem. To achieve algorithm flexibility, parallel writes from data cache memory to the control storage of the numeric processing subsystem are preferably possible. At least one of the numeric processors is preferably a floating-point processors, and one or more others may be application-customized processors. The application-customized processor is especially well adapted for some particular class of operations, such as discrete Fourier transform operations, and the numeric processor provides acceptably high speed on the general range of numeric computations. The data transfer processor (120) controls several external interfaces, including a port, for configuring multiple subsystems together, which includes two high-bandwidth input ports and a high-bandwidth output port. This permits a wide variety of highly pipelined and/or parallel architectures to be readily implemented.

4. 发明公开

EP0333365A3 Method and apparatus for handling asynchronous memory management exceptions by a vector processor 失效
标题翻译：用于处理由矢量处理器异步存储器管理异常的方法和装置
公开(公告)号：EP0333365A3
公开(公告)日：1991-05-08
申请号：EP89302225.1
申请日：1989-03-06
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： McKeen, Francis X. , Bhandarkar, Dileep P. , Fossum, Tryggve , Wiecek, Cheryl A.
IPC分类号： G06F15/06
CPC分类号： G06F9/462 , G06F9/3001 , G06F9/30036 , G06F9/30109
摘要： A data processing system handles memory management exceptions caused by a faulting vector instruction in a vector processor by halting the execution of the faulting vector instruction being executed when the exception occurred and by setting the state information for the vector processor to acknowledge the presence of the exception and to include information about the suboperation of the vector instruction being executed when the exception occurred. The scalar processor is not interrupted at this time, however. Any other vector instructions executing simultaneously with the faulting vector instruction are allowed to continue so long as those instructions do not require data from the faulting instruction. The faulting partially completed vector instruction resumes execution after the operating system has processed the memory management exception.
摘要翻译：数据处理系统通过停止发生异常时正在执行的故障向量指令的执行，并通过设置向量处理器的状态信息来确认异常的存在来处理由向量处理器中的故障向量指令引起的存储器管理异常并且包括关于当异常发生时正在执行的向量指令的子程序的信息。然而，此时标量处理器不会中断。只要这些指令不需要来自故障指令的数据，允许与故障向量指令同时执行的任何其他向量指令。故障部分完成向量指令在操作系统处理内存管理异常后恢复执行。

5. 发明公开

EP0346031A3 Vector data processing apparatus 失效
标题翻译：矢量数据处理设备
公开(公告)号：EP0346031A3
公开(公告)日：1990-12-27
申请号：EP89305622.6
申请日：1989-06-05
申请人： FUJITSU LIMITED
发明人： Sakai, Kenichi , Sakamoto, Kazushi , Nakatani, Shoji
IPC分类号： G06F15/06 , G06F9/38
CPC分类号： G06F9/3887 , G06F9/30036 , G06F9/3877 , G06F15/8084
摘要： A vector data processing apparatus having a set of vector registers (652), one or more memory access pipelines (650, 651), and one or more composite calculation pipelines (653-660), wherein the vector registers (652) consist of a plurality of banks, and each bank is independently accessible. Each of the pipelines (650, 651, 653-660) can cyclically access each of the banks of the vector registers (652) when one or more of a predetermined number of time slots, through each of which time slot said access is carried out, are assigned to an instruction using the pipeline. Immediately when a memory access instruction is received, a vector unit control circuit (66), which controls operations of the vector data processing apparatus, assigns a time slot for the newly-detected memory access instruction using a memory access pipeline, if it is determined that the memory access pipeline is available based on the pipeline operation status flags (2), and that a time slot is available based on the detected status of the predetermined number of time slots. Further, when a composite calculation instruction is received, the vector unit control circuit (66) assigns one or more time slots, to a newly-detected composite calculation instruction using a composite calculation pipeline, if it is determined that the composite calculation pipeline is available based on the pipeline operation status flags (2), and that time slots are available based on the detected status of the predetermined number of time slots.

6. 发明公开

EP0322856A3 MICROCOMPUTER 失效
标题翻译：微机
公开(公告)号：EP0322856A3
公开(公告)日：1990-12-27
申请号：EP88121714
申请日：1988-12-27
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： MURASE, KAZUYUKI , TASAKA, NAOYASU
IPC分类号： G06F11/22 , G01R31/317 , G06F15/78 , G11C5/06 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L29/788 , H01L29/792 , G06F15/06
CPC分类号： G11C5/066 , G01R31/31701 , G06F15/7814

7. 发明公开

EP0298658A3 Computational apparatus 失效
标题翻译：计算机
公开(公告)号：EP0298658A3
公开(公告)日：1990-07-11
申请号：EP88305948.7
申请日：1988-06-30
申请人： AT&T Corp.
发明人： Huang, Alan
IPC分类号： G06F15/06
CPC分类号： G06F15/8023
摘要： An array of interconnected of processing element (PE) is simulated by a smaller array of such elements (20), which may contain as few as one element. The outputs from the smaller array are connected via delay elements (33,34) to the inputs. Control signals (30) are applied to the elements of the smaller array to cause them to carry out seriatim the functions of the elements of the simulated array.

8. 发明公开

EP0295409A3 Programmable skew-tolerant array processor architecture 失效
标题翻译：可编程耐力阵列处理器架构
公开(公告)号：EP0295409A3
公开(公告)日：1990-06-13
申请号：EP88107075.9
申请日：1988-05-03
申请人： International Business Machines Corporation
发明人： Hsu, Yarsun , Li, Hungwen
IPC分类号： G06F15/06 , G06F13/42
CPC分类号： G06F15/8023 , G06F1/04 , G06F1/08 , G06F1/10
摘要： Using a variable-duration clock, together with programmable duration definition means to alter the clock waveform (8) within strict rules, permits the programmer to arrange appropriately short durations for short data transfers, and to arrange appropriately longer durations for longer data transfers in an array processor of myriad processing elements. There is no need to allow sufficient time in every clock cycle for worst case data transfer between remote processing elements (3). The clock waveform has three recognizable edges (A,B,C) regardless of loss of sharpness during its travel to the various processing elements. The convention that three skew-sensitive activities, READ, WRITE and OPERAND SUPPLY conform to respectively assigned edges as follows:
A = READ;
B = OPERAND SUPPLY;
C = WRITE (Read next) The processing elements synchronize with the clock waveform, which is optimized for the instructions of the program being executed. There is no time wasted allowing for worst case data transfers possible in certain instructions but not possible in other instructions.

9. 发明授权

EP0063458B1 Microcomputer system 失效
标题翻译：微型计算机系统
公开(公告)号：EP0063458B1
公开(公告)日：1989-08-23
申请号：EP82301871.8
申请日：1982-04-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Thaden, Robert C. , McDonough, Kevin C. , Hayne, John W. , Bellay, Jeffrey D. , Swoboda, Gary L. , Patrick, Michael W.
IPC分类号： G06F15/06 , G06F9/26 , G06F9/46
CPC分类号： G06F9/4825 , G06F9/24 , G06F9/264 , G06F9/268

10. 发明授权

EP0104802B1 Five port module as a node in an asynchronous speed independent network of concurrent processors 失效
标题翻译：作为同步处理器的异步速度独立网络中的节点的五个端口模块
公开(公告)号：EP0104802B1
公开(公告)日：1989-08-16
申请号：EP83305087.5
申请日：1983-09-01
申请人： UNISYS CORPORATION
发明人： Wilson, Jesse Rudolph , Logsdon, Gary Lee
IPC分类号： G06F15/16 , G06F15/06 , H04L11/20
CPC分类号： G06F15/17375 , G06F15/80

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