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1. 发明公开

EP0138419A3 Central processing unit for a digital computer 失效
标题翻译：数字电脑中央处理单元
公开(公告)号：EP0138419A3
公开(公告)日：1988-08-10
申请号：EP84306436
申请日：1984-09-20
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Butts, Bruce H., Jr. , Cutler, David N. , Schnorr, Peter Charles , Short, Robert T.
IPC分类号： G06F09/30
CPC分类号： G06F9/226 , G06F9/30036 , G06F9/30076 , G06F9/30101 , G06F9/30149 , G06F9/30167 , G06F9/30189
摘要： A central processing unit for a digital computer. In one embodiment, the central processing unit comprises a plurality of pointer registers that may be used during instruction execution to directly address other registers. In a second embodiment, the central processing unit comprises a size register that is loaded during the decode of an operation code with a size code indicating the data path width for that operation code. During instruction execution, the size code may be used at various times to determine data path width.

2. 发明公开

EP0180048A3 An arithmetic processor having a parallel accumulate function 失效
标题翻译：具有并行累积函数的算术处理器
公开(公告)号：EP0180048A3
公开(公告)日：1988-06-22
申请号：EP85112408
申请日：1985-10-01
申请人： International Business Machines Corporation
发明人： Degroot, Richard Douglas
IPC分类号： G06F07/48 , G06F09/30
CPC分类号： G06F7/5443 , G06F7/483 , G06F9/3001 , G06F2207/3884
摘要： A data processing system includes a multiple floating point arithmetic unit with a putaway and a bypass bus, which includes a new instruction for handling multiple multiply or divide instructions. These instructions are separated by add operations, including passing the results of each multiply/ divide operation on a bypass bus to the input of an adder along with the inuts from an accumulate bypass bus which is the output from the adder for an automatic add operation on an accumulate multiply or accumulate divide operation. This allows two floating point results to be produced each cycle, one of which can be accumulated without any intervening control by the central decoder. The accumulation is performed under distributed control of the accumulator logic itself.

3. 发明公开

EP0126247A3 Computer system 失效
标题翻译：电脑系统
公开(公告)号：EP0126247A3
公开(公告)日：1988-01-20
申请号：EP84103514
申请日：1984-03-30
申请人： International Business Machines Corporation
发明人： Wassel, Edward Richard , Watkins, Gerald Joseph
IPC分类号： G06F09/30 , G06F09/38
CPC分类号： G06F9/30021 , G06F9/30018 , G06F9/30036 , G06F15/8084
摘要： A computer system is disclosed wherein an instruction is executed, the results of the execution of the instruction are stored, and, simultaneously with the execution of the instruction, information is generated and stored which is related to the results of the execution of the instruction. The results of the execution of the instruction may comprise a binary number. The information which is generated, simultaneously with the execution of the instruction, includes, inter-alia, a count of the number of binary "1" bits and binary "0" bits which constitute the binary number, and a set of addresses representing the address locations of each bit of the binary number which constitutes the stored results of the execution of the instruction. The set of addresses include a first set of addresses representing address locations for all the binary "1" bits and a second set of addresses representing address locations for all the binary "0" bits of the binary number. The first set of addresses are stored in a first portion of a memory, the second set of addresses being stored in a second portion of the memory. As a result, the information is immediately available upon completion of the execution of the instruction.

4. 发明公开

EP0130381A3 Mechanism for implementing one machine cycle executable branch-on-any-bit-in-any-register instructions in a primitive instruction set computing system 失效
标题翻译：在主要指令集计算系统中执行一个机器循环可执行分支机构的任意位置指令的机制
公开(公告)号：EP0130381A3
公开(公告)日：1987-11-19
申请号：EP84106179
申请日：1984-05-30
申请人： International Business Machines Corporation
发明人： Auslander, Marc Alan , Hao, Hsieh Tung , Hopkins, Martin Edward , Markstein, Peter Willy , Radin, George , Worley, William Spencer, Jr.
IPC分类号： G06F09/30 , G06F09/32
CPC分类号： G06F9/30094 , G06F9/30 , G06F9/30058 , G06F9/30101
摘要： A mechanism for fully executing a branch-on-any-bit-in-any-register instruction within one machine cycle of the host computing system. The invention has particular utility in a primitive instruction set computing system wherein a majority of its primitive instruction set is executable within such a single machine cycle. Means are provided whereby a branch decision may be made not only on a specified bit in the condition register, but on any bit in any of the general purpose registers (30) provided in the system CPU. Means are also provided for saving a given configuration of the condition register in the general purpose registers for later use in subsequent branch-on-bit operations.

5. 发明公开

EP0130377A3 Condition register architecture for a primitive instruction set machine 失效
标题翻译：主要指导设备机器的条件注册架构
公开(公告)号：EP0130377A3
公开(公告)日：1987-10-21
申请号：EP84106174
申请日：1984-05-30
申请人： International Business Machines Corporation
发明人： Auslander, Marc Alan , Cocke, John , Hao, Hsieh Tung , Markstein, Peter Willy , Radin, George
IPC分类号： G06F09/30 , G06F09/46
CPC分类号： G06F9/30014 , G06F9/30094
摘要： @ A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency. Still more particularly, the condition register architecture provides for the efficient handling of multiply and divide operations and provides for the more efficient execution of certain decimal operations within such a reduced instruction set host computer system.

6. 发明公开

EP0052828A3 Pseudo-microprogramming in microprocessor with compressed control ROM and with strip layout of busses, alu and registers 失效
标题翻译：具有压缩控制ROM的微处理器中的微处理器微处理器和具有串行布局的ALU和寄存器
公开(公告)号：EP0052828A3
公开(公告)日：1985-01-23
申请号：EP81109598
申请日：1981-11-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： McDonough, Kevin C. , Guttag, Karl M. , Laws, Gerald E.
IPC分类号： G06F15/06 , G06F09/22 , G06F09/46 , G06F09/30 , G11C17/00
CPC分类号： G06F9/30156 , G06F9/223 , G06F15/7839 , G11C17/12
摘要： A single-chip microprocessor device of the MOS/LSI type contains an ALU, several interal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. The ALU, registers and busses along with the control ROM are constructed in an interrelated layout whereby minimum space is needed on the chip. Like bits in all registers and the ALU are aligned and in a regular pattern. The busses are metal lines overlying each of the strips of ALU/register bits. Controls are polysilicon lines perpendicular to the busses and aligned with columns of the control ROM. The control ROM is an array of rows and columns of potential MOS transistors, compressed by eliminating column lines which contain no transistors. The number of bits per column is a minimum to enhance compressability producing a wide configuration (long row lines) which allows the columns for control signals to align with the part of the ALU/register strip where the signal is to be used. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM) is provided which allows execution of instruction sequences to emulate complex instructions are indistinguishable from "native" instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. This on-chip memory does not affect the off-chip main memory map. Microprocessors are thus made more versatile and can be customized with little design effort. Also, off-chip access of another memory separate from the main memory allows emulator functions or special instructions.

7. 发明公开

EP0049137A3 Fixed data reading system 失效
标题翻译：固定数据读取系统
公开(公告)号：EP0049137A3
公开(公告)日：1983-09-28
申请号：EP81304451
申请日：1981-09-25
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Minami, Munehiro
IPC分类号： G06F09/34 , G06F09/30
CPC分类号： G06F9/35 , G06F15/7814
摘要： Disclosed is a fixed data reading system which comprises a read only memory (2) for storing program data and fixed data, a random access memory (4) for storing non-program data, a program counter for specifying a location of the read only memory (2), an incrementer for incrementing the contents of the program counter (8), and a program counter input register (24) for supplying the incremented program counter contents to the program counter at a predetermined timing. The random access memory (4) includes a data counter area for storing an address specifying a location of the read only memory (2) in which the fixed data is stored. When the instruction for reading fixed data in the read only memory (2) is decoded, an address is supplied from the data counter area allocated in the random access memory (4) to the program counter (8). When executing an ordinary instruction, the corresponding address is supplied from the program counter input register (24) to the program counter (8).

8. 发明公开

EP0055128A3 Data processing system 失效
公开(公告)号：EP0055128A3
公开(公告)日：1983-07-20
申请号：EP81306043
申请日：1981-12-22
申请人： Honeywell Information Systems Inc.
发明人： Tague, Steven A. , Negi, Virendra S.
IPC分类号： G06F09/30 , G06F09/38 , G06F05/00
CPC分类号： G06F9/226
摘要： A data processing system includes a commercial instruction processor for executing decimal alphanumeric instructions uses read only memories in the alignment of the operands. The characteristics of the operands, string or packed decimal as well as the length and position of the most significant decimal digit in a main memory word are specified by data descriptors. The read only memories are responsive to the data descriptor information as well as the instruction being executed to generate signals which specify whether the direction words are read from main memory is high order word first or low order word first, the number of double words in the operand, and the location of the least or most significant decimal digit within the word as stored in registers of the commercial instruction processor. A register coupled to an arithmetic logic unit stores double words of the operands wich are written into the register as double words, bytes or decimal digits. A multiplexer is responsive to control store signals and descriptor signals for generating write control signals which are applied to a read only memory, whose output write signals select the decimal digit, byte or double word positions of the register for writing. Another read only memory generates signals indicating next decimal digit position to be processed.

9. 发明公开

EP0039227A3 Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：EP0039227A3
公开(公告)日：1982-09-01
申请号：EP81301836
申请日：1981-04-27
申请人： DATA GENERAL CORPORATION
发明人： Alsing, Carl J. , Coyle, Richard W , Druke, Michael B. , Epstein, David I. , Guyer, James M. , Henry, Carl , Holberger, Kenneth D. , Holland, Charles J. , Keating, David L. , Rasala, Edward , Reilly, Paul , Rosen, Josh , Staudaher, Steven M. , Veres, James E. , Wallach, Steven , West, Thomas , Ziegler, Michael L.
IPC分类号： G11C09/06 , G06F13/00 , G06F09/30 , G06F09/22 , G06F03/04 , G06F11/10
CPC分类号： G06F9/342 , G06F9/261 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/30181 , G06F9/30189 , G06F9/30196 , G06F11/106 , G06F12/0292 , G06F12/0623 , G06F12/0802 , G06F12/0804 , G06F12/1009 , G06F12/1491
摘要： The system includes a central processor responsive to macroinstructions to produce microcontrol signals to which arithmetic logic unit (11) responds. An instruction processor (12) decodes macroinstructions to produce a starting address for one or more microinstructions. These are decoded by a programmable read only memory capable of decoding instructions of two types, the instruction being decoded containing bit patterns which identify uniquely the instruction type to be decoded. The instructions belong to a first basic instruction set having a logical address space of 2 power 16 bytes or to a second set providing an extended logical address space of 2 power 32 bytes. A microsequencer (13) responds to the starting address to provide a sequence of one or more microinstructions for producing a number of microcontrol signals. An address translation unit (14) responds to selected ones of the microcontrol signals to convert logical addresses into physical addresses. The systems main memory (16) stores information for use in the system in one to eight memory modules providing 2-4 megabytes of main memory in several memory plans e.g four planes of 16K 39-bit words in each module. A bank controller (18) controls the transfer of information between the main memory and a temporary storage device provided by a cache unit (17) having two ports to interface with the main memory. A central processor address bus (19) and a control processor memory bus (20) permit the transfer of addresses among the instruction processor (12), address translator (14) and the memory system and the transfer of instructions and operands among the arithmetic logic (11), processor (12), translator (14) and memory system (15).

10. 发明公开

EP0213301A3 Concurrent transfer and branch 失效
标题翻译：同步传输和分支
公开(公告)号：EP0213301A3
公开(公告)日：1988-10-26
申请号：EP86108413
申请日：1986-06-20
申请人： Hewlett-Packard Company
发明人： Baum, Allen J. , Miller, Terrence C. , Fotland, David A.
IPC分类号： G06F09/30
CPC分类号： G06F9/30072 , G06F9/30032 , G06F9/30058 , G06F9/30167 , G06F9/3842
摘要： In a computer device having a reduced instruction set architecture, frequently occurring operations are combined into a single instruction (110) in accordance with the invention, and the single instruction executes the combined operations simultaneously. Specifically, the frequently used instructions for moving data and then branching are combined into a single instruction (110) in a computer device in accordance with the preferred embodiment of the invention for concurrent execution. As a result, both code compaction and higher execution speed are achieved with the invention.

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