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1. 发明公开

EP2533291A3 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：EP2533291A3
公开(公告)日：2017-05-17
申请号：EP12170980.2
申请日：2012-06-06
申请人： Renesas Electronics Corporation
发明人： Fukui, Yuki , Katou, Hiroaki
IPC分类号： H01L29/417 , H01L29/78 , H01L21/336 , H01L23/485 , H01L21/3105 , H01L23/528 , H01L27/088
CPC分类号： H01L21/324 , H01L21/823487 , H01L23/4824 , H01L27/0922 , H01L29/41741 , H01L29/66666 , H01L29/7813 , H01L29/7815 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device structure is designed to restrain the variation in properties of vertical transistors due to reducing gas treatment of the device during its manufacturing. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Plural openings are made in the first source wiring.
摘要翻译：半导体器件结构被设计成抑制由于器件在其制造期间对器件的气体处理而导致的垂直晶体管的性质变化。垂直MOS晶体管形成在半导体衬底中。第一层间介电膜和第一源极布线形成在衬底的前表面之上。第一源极布线形成在第一层间绝缘膜上，并且在平面图中与垂直MOS晶体管重叠。触点埋在第一层间介质膜中。通过接触，垂直MOS晶体管的n型源极层与第一源极布线耦合。在第一源布线中形成多个开口。

2. 发明公开

EP3050092A4 NON-SILICON DEVICE HETEROLAYERS ON PATTERNED SILICON SUBSTRATE FOR CMOS BY COMBINATION OF SELECTIVE AND CONFORMAL EPITAXY 审中-公开
标题翻译：之间。通过组合选择性，符合外延在硅衬底EYED FOR CMOS硅-FREE装置的各层
公开(公告)号：EP3050092A4
公开(公告)日：2017-05-03
申请号：EP13894917
申请日：2013-09-27
申请人： INTEL CORP
发明人： GOEL NITI , CHAU ROBERT S , KAVALIEROS JACK T , CHU-KUNG BENJAMIN , METZ MATTHEW V , MUKHERJEE NILOY , ZELICK NANCY M , DEWEY GILBERT , RACHMADY WILLY , RADOSAVLJEVIC MARKO , LE VAN H , PILLARISETTY RAVI , DASGUPTA SANSAPTAK
IPC分类号： H01L21/336 , H01L21/02 , H01L21/20 , H01L21/8238 , H01L21/8252 , H01L27/092 , H01L29/06 , H01L29/165 , H01L29/205 , H01L29/66 , H01L29/78
CPC分类号： H01L21/0245 , H01L21/02381 , H01L21/02461 , H01L21/02463 , H01L21/02502 , H01L21/02532 , H01L21/02543 , H01L21/02546 , H01L21/02598 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L21/8252 , H01L27/0922 , H01L27/0924 , H01L29/0649 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/205 , H01L29/66795 , H01L29/785
摘要： A single fin or a pair of co-integrated n- and p- type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.
摘要翻译：单鳍或一对的共整合n型和p型单晶电子装置翅片外延从表面基材在一个的底部或一对浅沟槽隔离（STI）区域之间形成的沟槽的生长。翅片或散热片被图案化和STI区域被蚀刻以形成上述的STI区的蚀刻顶表面延伸的翅片或翼片的高度。翅片高度可以是至少1.5倍的宽度。暴露的侧壁表面和每个翅片的顶表面上外延与一种或多种适形外延材料包覆，以形成在鳍的器件层。之前生长翅片，毯子缓冲外延材料可从表面衬底上生长; 和在STI生长翅片沟槽的覆盖层的上方形成。翅片的搜索形成降低从材料界面的晶格失配的缺陷。

3. 发明公开

EP3158586A1 MONOLITHIC INTEGRATION OF HIGH VOLTAGE TRANSISTORS&LOW VOLTAGE NON-PLANAR TRANSISTORS 审中-公开
标题翻译：印度尼西亚联邦议会选举委员会
公开(公告)号：EP3158586A1
公开(公告)日：2017-04-26
申请号：EP14895422.5
申请日：2014-06-20
申请人： Intel Corporation
发明人： PHOA, Kinyip , NIDHI, Nidhi , JAN, Chia-Hong , CHANG, Ting
IPC分类号： H01L29/78 , H01L21/335
CPC分类号： H01L29/7834 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823456 , H01L21/823462 , H01L27/0886 , H01L27/0922 , H01L27/0924 , H01L29/0684 , H01L29/0847 , H01L29/66621 , H01L29/7835
摘要： High voltage transistors spanning multiple non-planar semiconductor bodies, such as fins or nanowires, are monolithically integrated with non-planar transistors utilizing an individual non-planar semiconductor body. The non-planar FETs may be utilized for low voltage CMOS logic circuitry within an IC, while high voltage transistors may be utilized for high voltage circuitry within the IC. A gate stack may be disposed over a high voltage channel region separating a pair of fins with each of the fins serving as part of a source/drain for the high voltage device. The high voltage channel region may be a planar length of substrate recessed relative to the fins. A high voltage gate stack may use an isolation dielectric that surrounds the fins as a thick gate dielectric. A high voltage transistor may include a pair of doped wells formed into the substrate that are separated by the high voltage gate stack with one or more fin encompassed within each well.
摘要翻译：跨越多个非平面半导体器件（例如鳍片或纳米线）的高电压晶体管与使用单个非平面半导体器件的非平面晶体管单片集成。非平面FET可用于IC内的低电压CMOS逻辑电路，而高电压晶体管可用于IC内的高电压电路。栅极堆叠可以设置在高压沟道区域上，该高压沟道区域分隔一对翅片，每个翅片用作高压设备的源极/漏极的一部分。高电压通道区域可以是相对于散热片凹进的基板的平面长度。高压栅极堆叠可以使用围绕散热片的隔离电介质作为厚栅极电介质。高压晶体管可以包括形成在衬底中的一对掺杂阱，其被高电压栅极堆叠分隔开，其中一个或多个鳍包围在每个阱内。

4. 发明授权

EP1573823B1 DENSE MOS DEVICES WITH CHANNEL IN VERTICAL SIDEWALL 有权转让
标题翻译：带垂直侧壁通道的密集MOS器件
公开(公告)号：EP1573823B1
公开(公告)日：2016-11-16
申请号：EP03790326.7
申请日：2003-12-05
申请人： Microsoft Technology Licensing, LLC
发明人： NOWAK, Edward, J. , RAINEY, BethAnn IBM United Kingdom Limited
IPC分类号： H01L27/092 , H01L29/12 , H01L29/78 , H01L21/8238 , H01L21/84 , H01L27/12
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823821 , H01L27/0922 , H01L27/1211 , H01L29/66795 , H01L2924/0002 , H01L2924/00

5. 发明公开

EP3087597A1 HYBRID HIGH-K FIRST AND HIGH-K LAST REPLACEMENT GATE PROCESS 审中-公开
标题翻译：具有高钾HYBRID取代栅极程序在开始和结束时
公开(公告)号：EP3087597A1
公开(公告)日：2016-11-02
申请号：EP14875116.7
申请日：2014-12-29
申请人： Texas Instruments Incorporated
发明人： NIIMI, Hiroaki , MEHORTRA, Manoj , NANDAKUMAR, Mahalingam
IPC分类号： H01L21/8249 , H01L27/092
CPC分类号： H01L27/092 , H01L21/02148 , H01L21/02164 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02332 , H01L21/0234 , H01L21/0271 , H01L21/0273 , H01L21/28079 , H01L21/28088 , H01L21/28158 , H01L21/28202 , H01L21/28238 , H01L21/31053 , H01L21/31055 , H01L21/31111 , H01L21/3212 , H01L21/32133 , H01L21/823828 , H01L21/823842 , H01L21/823857 , H01L27/0922 , H01L29/42364 , H01L29/42372 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

6. 发明公开

EP3084806A1 PLANAR HETEROGENEOUS DEVICE 审中-公开
标题翻译： PLANARE异构体VORRICHTUNG
公开(公告)号：EP3084806A1
公开(公告)日：2016-10-26
申请号：EP13899945.3
申请日：2013-12-18
申请人： Intel Corporation
发明人： JUN, Kimin , MORROW, Patrick
IPC分类号： H01L21/20
CPC分类号： H01L29/1054 , H01L21/02524 , H01L21/02538 , H01L21/02551 , H01L21/76283 , H01L21/823412 , H01L21/8258 , H01L27/0922 , H01L27/1207 , H01L29/16 , H01L29/20 , H01L29/22 , H01L29/267 , H01L29/78
摘要： In an embodiment a second semiconductor layer is transferred (e.g., using layer transfer techniques) on top of a first semiconductor layer. The second layer is patterned into desired wells. Between the wells, the first layer is exposed. The exposed first layer is epitaxially grown to the level of the transferred second layer to complete a planar heterogeneous substrate including both S1 and S2. The heterogeneous materials may be utilized such that, for example, a P channel device formed from one of III-V or IV materials is coplanar with an N channel device formed from one of III-V or IV materials. The embodiment requires no lattice parameter compliance due to the second layer being transferred onto the first layer. Also, there is no (or little) buffer and/or hetero-epitaxy. Other embodiments are described herein.
摘要翻译：在一个实施例中，在第一半导体层的顶部上转移第二半导体层（例如，使用层转移技术）。将第二层图案化成所需的孔。在井之间，第一层被暴露。暴露的第一层外延生长到转移的第二层的水平，以完成包括S1和S2的平面异质衬底。可以利用异质材料，使得例如由III-V或IV材料之一形成的P沟道器件与由III-V或IV族材料之一形成的N沟道器件共面。由于第二层被转移到第一层上，该实施例不需要晶格参数依从性。此外，没有（或少量）缓冲和/或异质外延。本文描述了其它实施例。

7. 发明公开

EP2942817A1 SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES 有权转让
标题翻译：硅氧烷 - 锗 - 纳米碳酸钠
公开(公告)号：EP2942817A1
公开(公告)日：2015-11-11
申请号：EP15166618.7
申请日：2011-11-23
申请人： Intel Corporation
发明人： Kuhn, Kelin J. , Kim, Seiyon , Rios, Rafael , Cea, Stephen M. , Giles, Martin D. , Cappellani, Annalisa , Rakshit, Titash , Chang, Peter , Rachmady, Willy
IPC分类号： H01L29/775 , H01L29/786 , H01L29/66 , H01L21/336 , H01L29/78 , B82Y10/00 , H01L29/417 , H01L29/423 , H01L29/06
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/76224 , H01L27/0922 , H01L27/1203 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Methods of forming nanowire devices are described. Embodiments of those methods include forming a nanowire device comprising a substrate (100) comprising source/drain structures (110) adjacent to spacers (106), and nanowire channel structures (102, 104) disposed between the spacers, wherein the nanowire channel structures are made of different materials (eg. Si and SiGe) alternating vertically and stacked above each other. In order to arrive at GAA devices, either the Si nanowires (104) are removed (Fig. 1i) or the SiGe nanowires (102) are removed (Fig. 1j). The resulting channels may have a strained channel (Fig. 1n).
摘要翻译：描述形成纳米线器件的方法。这些方法的实施例包括形成纳米线装置，其包括基板（100），该基板（100）包括邻近间隔物（106）的源极/漏极结构（110）以及设置在间隔物之间的纳米线通道结构（102,104），其中纳米线通道结构由不同的材料（例如Si和SiGe）制成，它们彼此垂直交替堆叠。为了到达GAA器件，去除Si纳米线（104）（图1i）或去除SiGe纳米线（102）（图1j）。所得到的通道可能具有应变通道（图1n）。

8. 发明公开

EP2869344A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：EP2869344A1
公开(公告)日：2015-05-06
申请号：EP14188677.0
申请日：2014-10-13
申请人： Renesas Electronics Corporation
发明人： Kaya, Yoshinori , Nakahara, Yasushi , Araya, Azuma , Kanda, Ryo , Kurihara, Tomonobu , Toda, Tetsu
IPC分类号： H01L27/092 , H01L29/78 , H01L29/10
CPC分类号： H02M1/088 , H01L27/0285 , H01L27/0292 , H01L27/0296 , H01L27/0629 , H01L27/0922 , H01L29/0642 , H01L29/0847 , H01L29/0878 , H01L29/1033 , H01L29/1079 , H01L29/405 , H01L29/42368 , H01L29/7816 , H01L29/7835 , H01L29/7838 , H03K2017/6875 , H03K2217/0081
摘要： Provided is a semiconductor device including a substrate of a first conductivity type, a first circuit region, a separation region, a second circuit region, and a rectifying element (HRD). The rectifying element has a second conductivity type layer, a first high concentration second conductivity type region, a second high concentration second conductivity type region, an element isolation film, a first insulation layer, and a first conductive film. A first contact is coupled to the first high concentration second conductivity type region, and a second contact is coupled to the second high concentration second conductivity type region. A third contact is coupled to the first conductive film. The first contact, the second contact and the third contact are separated from each other.
摘要翻译：提供了一种半导体器件，包括第一导电类型的衬底，第一电路区域，分隔区域，第二电路区域和整流元件（HRD）。整流元件具有第二导电类型层，第一高浓度第二导电类型区域，第二高浓度第二导电类型区域，元件隔离膜，第一绝缘层和第一导电膜。第一触点耦合到第一高浓度第二导电类型区域，并且第二触点耦合到第二高浓度第二导电类型区域。第三触点耦合到第一导电膜。第一触点，第二触点和第三触点彼此分开。

9. 发明公开

EP2738809A2 Semiconductor device including gate drivers around a periphery thereof 审中-公开
标题翻译： Halbleitervorrichtung mit Gate-Treibern um eine Peripherie davon
公开(公告)号：EP2738809A2
公开(公告)日：2014-06-04
申请号：EP13194698.0
申请日：2013-11-27
申请人： Enpirion, Inc.
发明人： Lotfi, Ashraf W. , Demski, Jeffrey , Feygenson, Anatoly , Lopata, Douglas Dean , Norton, Jay , Weld, John D.
IPC分类号： H01L27/02 , H01L27/092 , H01L29/417 , H01L23/31 , H01L23/64 , H01L23/522
CPC分类号： H01L27/0207 , H01L21/28518 , H01L21/76801 , H01L21/76895 , H01L21/8234 , H01L21/823871 , H01L23/3107 , H01L23/36 , H01L23/4824 , H01L23/495 , H01L23/49589 , H01L23/522 , H01L23/642 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/83 , H01L25/50 , H01L27/0203 , H01L27/0688 , H01L27/088 , H01L27/092 , H01L27/0922 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/41758 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/7835 , H01L2224/0401 , H01L2224/04042 , H01L2224/05647 , H01L2224/16225 , H01L2224/16235 , H01L2224/32245 , H01L2224/45144 , H01L2224/48247 , H01L2224/48647 , H01L2224/49175 , H01L2224/73253 , H01L2224/73265 , H01L2224/81815 , H01L2924/10253 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/19106 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die (1105) formed with a plurality of laterally diffused metal oxide semiconductor ("LDMOS") cells, and a metallic layer (1130) electrically coupled to the plurality of LDMOS cells. The semiconductor device also includes a plurality of gate drivers (1191, 1192) positioned along a periphery of the semiconductor die (1105) and electrically coupled to gates of the plurality of LDMOS cells through the metallic layer (1130).
摘要翻译：一种半导体器件及其形成方法，在一个实施例中，包括形成有多个横向扩散的金属氧化物半导体（“LDMOS”）单元的半导体管芯（1105）和与多个电极耦合的金属层（1130）的LDMOS细胞。半导体器件还包括沿着半导体管芯（1105）的周边定位的多个栅极驱动器（1191,1192），并通过金属层（1130）电耦合到多个LDMOS电池的栅极。

10. 发明公开

EP2728612A1 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE 审中-公开
标题翻译： VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERVORRICHTUNG
公开(公告)号：EP2728612A1
公开(公告)日：2014-05-07
申请号：EP12804351.0
申请日：2012-06-21
申请人： Fuji Electric Co., Ltd.
发明人： TOYODA, Yoshiaki , OOE, Takatoshi
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/76 , H01L21/822 , H01L27/04 , H01L27/08 , H01L27/088 , H01L29/739 , H01L29/78
CPC分类号： H01L29/66666 , H01L21/823807 , H01L21/823828 , H01L21/823885 , H01L27/0922 , H01L29/402 , H01L29/66348 , H01L29/66659 , H01L29/66734 , H01L29/7395 , H01L29/7811
摘要： In order to form an device in each of a vertical trench gate MOSFET region (21) and control lateral planar gate MOSFET region (22) of a semiconductor substrate, firstly, a trench (33) is formed in the semiconductor substrate in the vertical trench gate MOSFET region (21). Next, a first gate oxide film (7a) is formed along the internal wall of the trench (33). Next, the trench (33) is filled with a polysilicon film (6a) on the first gate oxide film (7a). Next, a LOCOS oxide film (11) is formed in a region isolating the devices. Next, a second gate oxide film (7b) is formed on the semiconductor substrate in the lateral planar gate MOSFET region (22). By so doing, advantages are achieved in that an increase in the number of steps is suppressed, the gate threshold voltage of an output stage MOSFET is higher than the gate threshold voltage of a control MOSFET, the thickness of the LOCOS oxide film (11) does not decrease, and no foreign object residue remains inside the trench (33).
摘要翻译：为了在半导体衬底的垂直沟槽栅极MOSFET区域（21）和控制侧面平面栅极MOSFET区域（22）的每一个中形成器件，首先在半导体衬底中在垂直沟槽中形成沟槽（33）栅极MOSFET区域（21）。接着，沿着沟槽（33）的内壁形成第一栅氧化膜（7a）。接下来，在第一栅极氧化膜（7a）上填充有多晶硅膜（6a）的沟槽（33）。接下来，在隔离器件的区域中形成LOCOS氧化膜（11）。接下来，在侧面平面栅极MOSFET区域（22）中的半导体衬底上形成第二栅极氧化膜（7b）。通过这样做，可以抑制步数的增加，输出级MOSFET的栅极阈值电压高于控制MOSFET的栅极阈值电压，LOCOS氧化膜（11）的厚度，不减少，并且在沟槽（33）内不残留异物残留物。

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