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1. 发明公开

EP3331012A1 SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF 审中-公开
公开(公告)号：EP3331012A1
公开(公告)日：2018-06-06
申请号：EP17204264.0
申请日：2017-11-29
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： LI, Yong
IPC分类号： H01L27/11 , H01L21/8238
CPC分类号： H01L27/1104 , H01L21/28079 , H01L21/28088 , H01L21/823821 , H01L21/823842 , H01L21/82385 , H01L21/823857 , H01L27/092 , H01L27/0922 , H01L27/0924 , H01L27/1116 , H01L29/42372 , H01L29/4958 , H01L29/4966 , H01L29/66545
摘要： A method for fabricating a semiconductor device includes forming a gate dielectric layer on a base substrate including an N-type logic region, a P-type logic region, a first pull down transistor (PDT) region, a second PDT region, and a pass gate transistor (PGT) region, forming a first work function layer (WFL) in the first N-type threshold-voltage (TV) region, the P-type logic region, the second PDT region, and the PGT region, forming a second WFL on the first WFL in the first P-type TV region, and forming a third WFL on the second WFL in the first P-type TV region, the first WFL in the second P-type TV region, and the gate dielectric layer in the second N-type TV region and the first PDT region. The thickness of the third WFL is smaller than the thickness of the first WFL. The method further includes forming a fourth WFL on the substrate.

2. 发明公开

EP3158586A4 MONOLITHIC INTEGRATION OF HIGH VOLTAGE TRANSISTORS&LOW VOLTAGE NON-PLANAR TRANSISTORS 审中-公开
公开(公告)号：EP3158586A4
公开(公告)日：2018-01-17
申请号：EP14895422
申请日：2014-06-20
申请人： INTEL CORP
发明人： PHOA KINYIP , NIDHI NIDHI , JAN CHIA-HONG , CHANG TING
IPC分类号： H01L29/78 , H01L21/335 , H01L21/8234 , H01L27/088 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/66
CPC分类号： H01L29/7834 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823456 , H01L21/823462 , H01L27/0886 , H01L27/0922 , H01L27/0924 , H01L29/0684 , H01L29/0847 , H01L29/66621 , H01L29/7835
摘要： High voltage transistors spanning multiple non-planar semiconductor bodies, such as fins or nanowires, are monolithically integrated with non-planar transistors utilizing an individual non-planar semiconductor body. The non-planar FETs may be utilized for low voltage CMOS logic circuitry within an IC, while high voltage transistors may be utilized for high voltage circuitry within the IC. A gate stack may be disposed over a high voltage channel region separating a pair of fins with each of the fins serving as part of a source/drain for the high voltage device. The high voltage channel region may be a planar length of substrate recessed relative to the fins. A high voltage gate stack may use an isolation dielectric that surrounds the fins as a thick gate dielectric. A high voltage transistor may include a pair of doped wells formed into the substrate that are separated by the high voltage gate stack with one or more fin encompassed within each well.

3. 发明公开

EP3084806A4 PLANAR HETEROGENEOUS DEVICE 审中-公开
标题翻译： PLANARE HETEROGENE VORRICHTUNG
公开(公告)号：EP3084806A4
公开(公告)日：2017-07-26
申请号：EP13899945
申请日：2013-12-18
申请人： INTEL CORP
发明人： JUN KIMIN , MORROW PATRICK
IPC分类号： H01L21/8258 , H01L27/12 , H01L29/10 , H01L29/78
CPC分类号： H01L29/1054 , H01L21/02524 , H01L21/02538 , H01L21/02551 , H01L21/76283 , H01L21/823412 , H01L21/8258 , H01L27/0922 , H01L27/1207 , H01L29/16 , H01L29/20 , H01L29/22 , H01L29/267 , H01L29/78
摘要： In an embodiment a second semiconductor layer is transferred (e.g., using layer transfer techniques) on top of a first semiconductor layer. The second layer is patterned into desired wells. Between the wells, the first layer is exposed. The exposed first layer is epitaxially grown to the level of the transferred second layer to complete a planar heterogeneous substrate including both S1 and S2. The heterogeneous materials may be utilized such that, for example, a P channel device formed from one of III-V or IV materials is coplanar with an N channel device formed from one of III-V or IV materials. The embodiment requires no lattice parameter compliance due to the second layer being transferred onto the first layer. Also, there is no (or little) buffer and/or hetero-epitaxy. Other embodiments are described herein.
摘要翻译：在一个实施例中，第二半导体层在第一半导体层上被转移（例如，使用层转移技术）。第二层被图案化成所需的孔。在井之间，第一层被暴露。暴露的第一层外延生长到转移的第二层的水平以完成包括S1和S2两者的平面异质衬底。可以使用非均质材料，使得例如由III-V或IV材料中的一种形成的P沟道器件与由III-V或IV材料中的一种形成的N沟道器件共面。由于第二层被转移到第一层上，该实施例不需要晶格参数顺从性。此外，没有（或很少）缓冲和/或异质外延。这里描述了其他实施例。

4. 发明公开

EP3178116A1 METHODS AND APPARATUS FOR LDMOS DEVICES WITH CASCADED RESURF IMPLANTS AND DOUBLE BUFFERS 审中-公开
标题翻译： FOR LDMOS设备使用的方法和设备级联RESURF植入物和双缓冲器
公开(公告)号：EP3178116A1
公开(公告)日：2017-06-14
申请号：EP15830577.1
申请日：2015-08-07
申请人： Texas Instruments Incorporated
发明人： CAI, Jun
IPC分类号： H01L29/80
CPC分类号： H01L29/7823 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/823814 , H01L27/0922 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/0856 , H01L29/0873 , H01L29/0878 , H01L29/1041 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/66659 , H01L29/66681 , H01L29/66689 , H01L29/78 , H01L29/7816 , H01L29/7835
摘要： LDMOS devices are disclosed. An LDMOS device includes at least one drift region disposed in a portion of a semiconductor substrate; at least one isolation structure at a surface of the semiconductor substrate; a D-well region positioned adjacent a portion of the at least one drift region, and an intersection of the drift region and the D-well region forming a junction between first and second conductivity types; a gate structure disposed over the semiconductor substrate; a source contact region disposed on the surface of the D-well region; a drain contact region disposed adjacent the isolation structure; and a double buffer region comprising a first buried layer lying beneath the D-well region and the drift region and doped to the second conductivity type and a second high voltage deep diffusion layer lying beneath the first buried layer and doped to the first conductivity type. Methods are disclosed.
摘要翻译： LDMOS器件是游离缺失盘。 LDMOS器件包括：在半导体衬底的一部分设置在至少一个漂移区; 在在半导体基片的表面的至少一个隔离结构; 一个D-阱区位于邻近的所述至少一个漂移区的一部分，并且在所述漂移区域和所述D-阱区形成第一和第二导电类型之间的结点的交叉点; 设置在半导体衬底的栅结构; 设置在D-阱区的表面上的源极接触区; 漏极接触区相邻设置的隔离结构; 和一个双缓冲器区，其包含第一埋层位于该D-阱区域下方和漂移区和掺杂为第二导电类型并位于所述第一掩埋层下面的第二高电压深扩散层和掺杂到第一导电类型。方法是游离缺失盘。

5. 发明公开

EP3144959A3 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：EP3144959A3
公开(公告)日：2017-05-17
申请号：EP16182633.4
申请日：2016-08-03
申请人： Renesas Electronics Corporation
发明人： YAMAMOTO, Yuki , YAMASHITA, Tomohiro
IPC分类号： H01L21/28 , H01L27/1157 , H01L27/11573 , H01L27/06 , H01L21/265 , H01L49/02 , H01L21/324
CPC分类号： H01L27/11573 , H01L21/265 , H01L21/26513 , H01L21/28282 , H01L21/324 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L27/1157 , H01L27/11575 , H01L28/20 , H01L29/7816 , H01L29/792
摘要： A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.
摘要翻译：半导体器件的性能得到改善。由硅构成的膜形成在半导体基板上的电阻元件形成区域中，并且作为选自包括14族元素和18族元素的组中的至少一种元素的杂质为离子注入到膜中，并且形成由离子注入杂质的部分的膜形成的膜部分。接着，在半导体基板上的存储器形成区域中形成其中具有电荷存储部分的绝缘膜，并且在绝缘膜上形成导电膜。

6. 发明公开

EP2915257A1 SEMICONDUCTOR DEVICE HAVING FEATURES TO PREVENT REVERSE ENGINEERING 审中-公开
标题翻译：半导体器件具有防止反向工程的特点
公开(公告)号：EP2915257A1
公开(公告)日：2015-09-09
申请号：EP12887826.1
申请日：2012-12-14
申请人： Secure Silicon Layer, Inc.
发明人： THACKER, III, William Eli , TENCZAR, Robert Francis , HOKE, Michael Clinton
IPC分类号： H03K19/20
CPC分类号： H01L27/0922 , H01L21/82 , H01L23/573 , H01L27/0203 , H01L27/06 , H01L28/24 , H01L2924/0002 , H03K19/20 , H01L2924/00
摘要： It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern tear down techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.
摘要翻译：设计和制造耐受现代逆向工程技术的电子芯片是理想的。公开了一种方法和设备，其允许使用现代拆卸技术来设计难以逆向工程的芯片。所公开的设备使用具有相同几何结构但不同电压电平的设备来创建不同的逻辑设备。或者，所公开的使用具有不同几何形状和相同操作特性的装置。还公开了使用这些设备设计芯片的方法。

7. 发明公开

EP2849219A1 Method for manufacturing transistors and associated substrate 审中-公开
标题翻译： Verfahren zur Herstellung von Transistoren undzugehörigesSubstrat
公开(公告)号：EP2849219A1
公开(公告)日：2015-03-18
申请号：EP13183985.4
申请日：2013-09-11
申请人： IMEC VZW
发明人： Waldron, Niamh , Witters, Liesbeth
IPC分类号： H01L21/8258 , H01L21/8238 , H01L27/092 , H01L29/66 , H01L29/04
CPC分类号： H01L27/0922 , H01L21/762 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L21/8258 , H01L27/0924 , H01L29/045 , H01L29/0653 , H01L29/161 , H01L29/20 , H01L29/267
摘要： A method for manufacturing a CMOS device, comprising providing a starting substrate, the starting substrate comprising a silicon substrate the surface of which is oriented along the (100) crystal plane;
- forming shallow trench isolation structures in a first predetermined region, thereby defining channel areas in said substrate embodied as silicon protrusions extending from said silicon substrate and being isolated from each other by means of isolation structures;
- removing said silicon protrusions, thereby creating trenches;
- filling said trenches by epitaxially growing a III-V material in said trenches, to thereby form channel structures of transistors of a first type which are essentially defect-free; and associated substrate.
摘要翻译：一种制造CMOS器件的方法，包括提供起始衬底，所述起始衬底包括硅衬底，所述衬底的表面沿（100）晶面定向; - 在第一预定区域中形成浅沟槽隔离结构，从而限定所述衬底中的通道区域，其被实施为从所述硅衬底延伸并通过隔离结构彼此隔离的硅突起; - 去除所述硅突起，从而产生沟槽; - 通过在所述沟槽中外延生长III-V材料来填充所述沟槽，从而形成基本上无缺陷的第一类晶体管的沟道结构; 和相关底物。

8. 发明公开

EP2779225A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：EP2779225A1
公开(公告)日：2014-09-17
申请号：EP12847671.0
申请日：2012-10-12
申请人： Fuji Electric Co., Ltd.
发明人： YAMAJI, Masaharu
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/822 , H01L27/04 , H01L27/06 , H01L27/088 , H01L29/78
CPC分类号： H01L29/7393 , H01L21/765 , H01L27/0922 , H01L29/0634 , H01L29/0696 , H01L29/405 , H01L29/42368 , H01L29/7395 , H01L29/7816 , H01L29/7835 , H01L29/8611
摘要： An n - type region (101) encloses an n-type well region (201) in which is disposed a high-side drive circuit (300). A high resistance polysilicon thin film (401) configuring a resistive field plate structure of a high breakdown voltage junction termination region is disposed in spiral form on the n - type region (101). Also, an OUT electrode (120), a ground electrode (121), and a Vcc1 electrode (122) are disposed on the n - type region (101). The Vcc1 electrode (122) is connected to the positive electrode of an auxiliary direct current power supply (a bootstrap capacitor) (E1). The OUT electrode (120) is connected to the negative electrode of the auxiliary direct current power supply (E1). One end portion (a second contact portion) (403) of the high resistance polysilicon thin film (401) is connected to the ground electrode (121). Also, the other end portion (a first contact portion) (402) of the high resistance polysilicon thin film (401) is connected to the OUT electrode (120).
摘要翻译： n型区域（101）包围其中设置有高侧驱动电路（300）的n型阱区域（201）。构成高击穿电压结终端区域的电阻场板结构的高电阻多晶硅薄膜（401）以螺旋形式设置在n-型区域（101）上。而且，在n型区域（101）上设置有OUT电极（120），接地电极（121）和Vcc1电极（122）。 Vcc1电极（122）连接到辅助直流电源（自举电容器）（E1）的正极。 OUT电极（120）连接到辅助直流电源（E1）的负极。高电阻多晶硅薄膜（401）的一个端部（第二接触部分）（403）连接到接地电极（121）。而且，高电阻多晶硅薄膜（401）的另一端部（第一接触部分）（402）连接到OUT电极（120）。

9. 发明公开

EP2738813A2 Semiconductor device including alternating source and drain regions, and respective source and drain metallic strips 审中-公开
标题翻译：具有交替的源和漏区以及相关的源极和漏极金属条的半导体器件
公开(公告)号：EP2738813A2
公开(公告)日：2014-06-04
申请号：EP13194673.3
申请日：2013-11-27
申请人： Enpirion, Inc.
发明人： Lotfi, Ashraf W. , Demski, Jeffrey , Feygenson, Anatoly , Lopata, Douglas Dean , Norton, Jay , Weld, John D.
IPC分类号： H01L29/417 , H01L21/336
CPC分类号： H01L27/0207 , H01L21/28518 , H01L21/76801 , H01L21/76895 , H01L21/8234 , H01L21/823871 , H01L23/3107 , H01L23/36 , H01L23/4824 , H01L23/495 , H01L23/49589 , H01L23/522 , H01L23/642 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/83 , H01L25/50 , H01L27/0203 , H01L27/0688 , H01L27/088 , H01L27/092 , H01L27/0922 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/41758 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/7835 , H01L2224/0401 , H01L2224/04042 , H01L2224/05647 , H01L2224/16225 , H01L2224/16235 , H01L2224/32245 , H01L2224/45144 , H01L2224/48247 , H01L2224/48647 , H01L2224/49175 , H01L2224/73253 , H01L2224/73265 , H01L2224/81815 , H01L2924/10253 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/19106 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device and method of forming the same including, in one embodiment, a substrate (1105) and a plurality of source and drain regions (s, d) formed as alternating pattern on the substrate (1105). The semiconductor device also includes a plurality of gates (1150) formed over the substrate (1105) between and parallel to ones of the plurality of source and drain regions. The semiconductor device also includes a first plurality of alternating source and drain metallic strips (1111, 1121) formed in a first metallic layer above the substrate (1105) and parallel to and forming an electrical contact with respective ones of the plurality of source and drain regions.

10. 发明公开

EP2412018A4 STRUCTURE AND FABRICATION OF FIELD-EFFECT TRANSISTOR USING EMPTY WELL IN COMBINATION WITH SOURCE/DRAIN EXTENSIONS OR/AND HALO POCKET 审中-公开
标题翻译：建设和生产的场效应晶体管的空空腔与源极/漏极扩展和/或卤素组合BAG
公开(公告)号：EP2412018A4
公开(公告)日：2013-07-31
申请号：EP10756495
申请日：2010-03-25
申请人： NAT SEMICONDUCTOR CORP
发明人： BULUCEA CONSTANTIN , YANG JENG-JIUN , FRENCH WILLIAM D , BAHL SANDEEP R , PARKER D COURTNEY
IPC分类号： H01L21/70 , H01L29/02 , H01L29/10
CPC分类号： H01L29/7835 , H01L21/26513 , H01L21/2652 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L27/0922 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7833
摘要： Insulated-gate field-effect transistors (IGFETs), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET (100, 102, 112, 114, 124, or 126) has a pair of source/drain zones laterally separated by a channel zone of body material of the empty well (180, 182, 192, 194, 204, or 206). A gate electrode overlies a gate dielectric layer above the channel zone. Each source/drain zone (240, 242, 280, 282, 520, 522, 550, 552, 720, 722, 752, or 752) has a main portion (240M, 242M, 280M, 282M, 520M, 522M, 550M, 552M, 720M, 722M, 752M, or 752M) and a more lightly doped lateral extension (240E, 242E, 280E, 282E, 520E, 522E, 550E, 552E, 720E, 722E, 752E, or 752E). Alternatively or additionally, a more heavily doped pocket portion (250 or 290) of the body material extends along one of the source/drain zones. When present, the pocket portion typically causes the IGFET to be an asymmetric device.
摘要翻译：绝缘栅场效应晶体管（IGFET的），对称和非对称，适于半导体制造平台确实提供用于模拟和数字应用，包括混合信号应用的IGFET，利用空阱区域中实现高的性能。半导体阱部掺杂剂的相对小的量是靠近每个空孔的顶部。每一个IGFET（100，102，112，114，124，或126）具有一对源极/漏极区尾盘反弹由空孔（180，182，192，194，204，或206的主体材料的沟道区分开的）。栅极电极重叠的沟道区上方的栅极介电层。每个源极/漏极区（240，242，280，282，520，522，550，552，720，722，752，或752）具有主要部分（240M，242米，280M，282M，520M，522米，550米， 552米，720M，722米，752米，或752米）及较轻度掺杂的横向延伸（240E，242E，280E，282E，520E，522E，550E，552E，720E，722E，752 E，752 E或）。或者或另外，所述主体材料的更重度掺杂袋部（250或290）沿所述源极/漏极区中的一个延伸。当存在时，袋部通常导致IGFET是不对称的装置。

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