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1. 发明公开

EP1176643A2 MOS power semiconductor device having a trench gate and method of making the same 审中-公开
标题翻译：具有它们的制备沟槽栅电极和过程MOS功率半导体器件
公开(公告)号：EP1176643A2
公开(公告)日：2002-01-30
申请号：EP01116709.5
申请日：2001-07-17
申请人： Fairchild Semiconductor Corporation
发明人： Zeng, Jun , Dolny, Gary M. , Kocon, Christopher B. , Brush, Linda S.
IPC分类号： H01L29/78 , H01L29/417 , H01L29/423 , H01L29/739 , H01L29/745 , H01L21/336 , H01L21/331 , H01L21/332
CPC分类号： H01L29/7802 , H01L29/41766 , H01L29/66348 , H01L29/66363 , H01L29/7397 , H01L29/7455 , H01L29/7813
摘要： An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain region, and a plurality of spaced apart buried gates, each of which comprises a trench that extends from the upper surface of the upper layer through the well region into the drain region. Each trench comprises an insulating material lining its surface, a conductive material filling its lower portion to a selected level substantially below the upper surface of the upper layer, and an insulating material substantially filling the remainder of the trench. A plurality of highly doped source regions of a second conductance type are disposed in the upper layer adjacent the upper portion of each trench, each source region extending from the upper surface to a depth in the upper layer selected to provide overlap between the source regions and the conductive material in the trenches. A groove in each of the highly doped source regions extends through the source regions into the well region and terminates in a nadir. A highly doped body region of a first conductance type is disposed in the well region adjacent both to the nadir of one or more of the grooves and to adjacent source regions penetrated by the grooves. A conductive layer is disposed over the substrate and electrically contacts the body and source regions. A process for fabricating a device produces an MOS power device that avoids the loss of channel width and provides reduced channel resistance without sacrificing device ruggedness and dynamic characteristics.
摘要翻译：的MOS功率器件上的上表面和在底层的漏极区域具有上层的包括基材，在漏极区域中的上层设置的第一电导类型的阱区域中，和间隔开的埋入式栅极的复数，其中的每一个包括沟槽的确从通过所述阱区的上部层向漏区的上表面上延伸。绝缘材料衬里其表面的每个沟槽包括，导电材料填充其下部，以大大低于上层的上表面上选定的水平，和绝缘材料基本上填充所述沟槽的剩余部分。一个第二电导类型的高度掺杂的源极区的多个上层邻近每个沟槽的上部设置，在上层从上表面延伸至一深度各源极区选择为所述源极区域之间提供重叠导电材料在沟槽中。在每个重掺杂源极区的凹槽通过源极区域到阱区延伸，并且在最低点终止。第一电导类型的高度掺杂的体区在相邻的两个的一个或多个槽的最低点和由槽穿入的相邻源极区的阱区被设置。导电层设置在基片和电接触所述主体区和源区。 MOS功率器件的一种制造设备过程中产生确实避免了信道宽度的损失和信道提供降低的电阻而不牺牲设备的耐用性和动态特性。

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