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1. 发明公开

EP3050115A4 VERTICAL TRANSISTOR DEVICES FOR EMBEDDED MEMORY AND LOGIC TECHNOLOGIES 审中-公开
标题翻译： VERTIKALE TRANSISTORVORRICHTUNGENFÜREINGEBETTETEN SPEICHER UND LOGISCHE TECHNOLOGIEN
公开(公告)号：EP3050115A4
公开(公告)日：2017-08-30
申请号：EP14846896
申请日：2014-09-02
申请人： INTEL CORP
发明人： DOYLE BRIAN S , SHAH UDAY , KOTLYAR ROZA , KUO CHARLES C
IPC分类号： H01L21/336 , H01L29/10 , H01L29/161 , H01L29/165 , H01L29/78
CPC分类号： H01L29/66666 , H01L21/02532 , H01L21/30604 , H01L29/0847 , H01L29/1037 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/201 , H01L29/205 , H01L29/4983 , H01L29/66356 , H01L29/66363 , H01L29/7391 , H01L29/749 , H01L29/7827 , H01L29/7848
摘要： Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.
摘要翻译：描述了垂直晶体管器件。例如，在一个实施例中，垂直晶体管器件包括设置在衬底上的外延源半导体区，设置在源半导体区上的外延沟道半导体区，设置在沟道半导体区上的外延漏半导体区以及栅电极区域围绕半导体沟道区域的侧壁。至少一个半导体区域的成分沿着垂直于衬底表面的纵向轴线变化。

2. 发明公开

EP3097580A4 FIN-BASED SEMICONDUCTOR DEVICES AND METHODS 有权
标题翻译： FIN-BASIERTE HALBLEITERBAUELEMENTE UND VERFAHREN
公开(公告)号：EP3097580A4
公开(公告)日：2017-08-16
申请号：EP14879976
申请日：2014-01-24
申请人： INTEL CORP
发明人： HAFEZ WALID M , JAN CHIA-HONG
IPC分类号： H01L21/336 , H01L21/225 , H01L27/02 , H01L29/417 , H01L29/74 , H01L29/78
CPC分类号： H01L29/74 , H01L21/2255 , H01L27/0262 , H01L29/0649 , H01L29/41716 , H01L29/66363 , H01L29/785
摘要： Embodiments of semiconductor devices, integrated circuit devices and methods are disclosed. In some embodiments, a semiconductor device may include a first fin and a second fin disposed on a substrate. The first fin may have a portion including a first material disposed between a second material and the substrate, the second material disposed between a third material and the first material, and the third material disposed between a fourth material and the second material. The first and third materials may be formed from a first type of extrinsic semiconductor, and the second and fourth materials may be formed from a second, different type of extrinsic semiconductor. The second fin may be laterally separated from the first fin and materially contiguous with at least one of the first, second, third or fourth materials. Other embodiments may be disclosed and/or claimed.
摘要翻译：公开了半导体器件，集成电路器件和方法的实施例。在一些实施例中，半导体器件可以包括设置在衬底上的第一鳍和第二鳍。第一鳍状物可以具有包括设置在第二材料和基底之间的第一材料的部分，第二材料设置在第三材料和第一材料之间，并且第三材料设置在第四材料和第二材料之间。第一和第三材料可以由第一类型的非本征半导体形成，第二和第四材料可以由第二种不同类型的非本征半导体形成。第二翅片可以与第一翅片横向分离并且与第一，第二，第三或第四材料中的至少一种材料地邻接。其他实施例可以被公开和/或要求保护。

3. 发明公开

EP2628186A4 VERTICAL SEMICONDUCTOR DEVICE WITH THINNED SUBSTRATE 审中-公开
标题翻译：用稀释后的衬底垂直半导体器件，
公开(公告)号：EP2628186A4
公开(公告)日：2015-11-25
申请号：EP11833222
申请日：2011-10-11
申请人： SILANNA SEMICONDUCTOR USA INC
发明人： MOLIN STUART B , STUBER MICHAEL A
IPC分类号： H01L29/78 , H01L21/336 , H01L21/683 , H01L21/8234 , H01L23/48 , H01L27/082 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/73 , H01L29/732 , H01L29/739 , H01L29/744
CPC分类号： H01L27/1203 , H01L21/6835 , H01L21/823487 , H01L21/84 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/94 , H01L27/0823 , H01L27/088 , H01L29/0649 , H01L29/0657 , H01L29/41741 , H01L29/66272 , H01L29/66333 , H01L29/66363 , H01L29/66712 , H01L29/66734 , H01L29/73 , H01L29/732 , H01L29/7395 , H01L29/744 , H01L29/7802 , H01L29/7812 , H01L29/7813 , H01L2221/68327 , H01L2221/6834 , H01L2224/03002 , H01L2224/0401 , H01L2224/11002 , H01L2224/13022 , H01L2224/131 , H01L2224/13147 , H01L2224/1403 , H01L2224/94 , H01L2924/10253 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/014 , H01L2224/11 , H01L2924/00
摘要： A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

4. 发明公开

EP2761661A2 MCT DEVICE WITH BASE-WIDTH-DETERMINED LATCHING AND NON-LATCHING STATES 审中-公开
标题翻译：与基宽特定的锁和MCT设备不能锁定STATES
公开(公告)号：EP2761661A2
公开(公告)日：2014-08-06
申请号：EP12837357.8
申请日：2012-10-01
申请人： Pakal Technologies LLC
发明人： BLANCHARD, Richard, A. , AKIYAMA, Hidenori , TWORZYDLO, Woytek
IPC分类号： H01L29/74 , H01L21/332
CPC分类号： H01L29/7455 , H01L29/1608 , H01L29/2003 , H01L29/42308 , H01L29/66363
摘要： Methods and systems for a gate-controlled thyristor which switches between narrow-base operation in the ON state and wide -base operation in the OFF state, and which can only sustain latch-up in the narrow-base ON state.

5. 发明公开

EP2717314A1 Method of producing a junction termination for a power semiconductor device and corresponding power semiconductor device 审中-公开
标题翻译：一种用于制造结终端的功率半导体器件和相应的功率半导体装置的方法
公开(公告)号：EP2717314A1
公开(公告)日：2014-04-09
申请号：EP12187107.3
申请日：2012-10-03
申请人： ABB Technology AG
发明人： Botan, Virgiliu , Vobecky, Jan
IPC分类号： H01L29/06 , H01L29/74 , H01L21/332 , H01L21/306
CPC分类号： H01L29/0661 , H01L21/30608 , H01L29/66363 , H01L29/74
摘要： A method of producing a junction termination (16) for a power semiconductor device, said junction termination (16) being formed as a recess (20) at an edge of a first side of a semiconductor wafer (19) having a first region (12) of a first conductivity type (p) at said first side, said method comprising creating a second region (21) of a second, different conductivity type (n) at said edge of the first side, and removing said second region (21) using an etching fluid, e.g. a KOH solution, which provides a higher etching rate in the second region (21) than in the first region (12), so that the recess (20) is formed. The second region (21) may have a laterally varying doping (VLD) profile to obtain a recess (20) with correspondingly varying depth, e.g. a negative bevel junction termination. With a constant doping profile of the second region (21) a mesa junction termination is achieved.
摘要翻译：对于功率半导体器件制造结终端（16）的方法，所述结终端（16）被形成为在凹部（20）在一个半导体晶片的第一侧面（19）具有第一区域的边缘（12 ）第一导电类型（p）在所述第一侧的，所述方法包括在所述第一侧的所述边缘创建不同的第二导电类型（n）的第二区域（21）;以及去除所述第二区域（21）使用蚀刻液，例如 KOH溶液，它提供了比在第一区域（12）的第二区域（21）更高的蚀刻速率，所以DASS模具凹槽（20）形成。所述第二区域（21）可以具有一个晚的反弹变化的掺杂（VLD）简档以获得凹部（20）具有相应变化的深度，E.G. 一个负斜角结终端。与所述第二区域的恒定掺杂分布（21）的台面结终端实现。

6. 发明公开

EP2628186A2 VERTICAL SEMICONDUCTOR DEVICE WITH THINNED SUBSTRATE 审中-公开
标题翻译：用稀释后的衬底垂直半导体器件，
公开(公告)号：EP2628186A2
公开(公告)日：2013-08-21
申请号：EP11833222.0
申请日：2011-10-11
申请人： IO Semiconductor, Inc.
发明人： MOLIN, Stuart B. , STUBER, Michael A.
IPC分类号： H01L29/78 , H01L21/336 , H01L23/48
CPC分类号： H01L27/1203 , H01L21/6835 , H01L21/823487 , H01L21/84 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/94 , H01L27/0823 , H01L27/088 , H01L29/0649 , H01L29/0657 , H01L29/41741 , H01L29/66272 , H01L29/66333 , H01L29/66363 , H01L29/66712 , H01L29/66734 , H01L29/73 , H01L29/732 , H01L29/7395 , H01L29/744 , H01L29/7802 , H01L29/7812 , H01L29/7813 , H01L2221/68327 , H01L2221/6834 , H01L2224/03002 , H01L2224/0401 , H01L2224/11002 , H01L2224/13022 , H01L2224/131 , H01L2224/13147 , H01L2224/1403 , H01L2224/94 , H01L2924/10253 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/014 , H01L2224/11 , H01L2924/00
摘要： A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

7. 发明授权

EP1745515B1 TUNEABLE SEMICONDUCTOR DEVICE 有权
标题翻译：调谐半导体COMPONENT
公开(公告)号：EP1745515B1
公开(公告)日：2011-07-27
申请号：EP04822011.5
申请日：2004-04-22
申请人： International Business Machines Corporation
发明人： FREEMAN, Gregory, G. , RIEH, Jae-Sung, c/o IBM United Kingdom Ltd. , SHERIDAN, David, C. , ST.ONGE, Stephen, A. , STRICKER, Andreas, D. , VOLDMAN, Steven, H.
IPC分类号： H01L29/732 , H01L29/08
CPC分类号： H01L29/66363 , H01L29/0821 , H01L29/0834 , H01L29/66242 , H01L29/7378 , H01L29/74 , H01L29/861 , H01L29/872 , H01L29/93
摘要： Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.

8. 发明公开

EP1686616A3 Process for manufacture of mos gated device with reduced mask count 失效
标题翻译：一种用于制造MOS控制的设备与掩模的数量减少的方法
公开(公告)号：EP1686616A3
公开(公告)日：2009-03-18
申请号：EP06010237.3
申请日：1995-08-17
申请人： INTERNATIONAL RECTIFIER CORPORATION
发明人： Kinzer, Daniel M.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/1095 , H01L29/41716 , H01L29/41766 , H01L29/66363 , H01L29/66727 , H01L29/7396
摘要： A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask (33) to sequentially form a cell body (50) and a source region (51) within the cell body (50), and a second mask step to form, by a silicon etch, a central opening (80,81) in the silicon surface at each cell and to subsequently undercut the oxide (60) surrounding the central opening (80,81). A contact layer (84) then fills the openings (80,81) of each cell to connect together the body (50) and source regions (51). Only one critical mask alignment step is used in the process.

9. 发明公开

EP1384269A2 MIS-HALBLEITERLEISTUNGSBAUELEMENT UND ENTSPRECHENDES HERSTELLUNGSVERFAHREN 有权
标题翻译： MIS半导体功率器件及相应方法
公开(公告)号：EP1384269A2
公开(公告)日：2004-01-28
申请号：EP02737772.0
申请日：2002-04-03
申请人： ROBERT BOSCH GMBH
发明人： PLIKAT, Robert , FEILER, Wolfgang
IPC分类号： H01L29/745 , H01L21/332 , H01L29/06 , H01L29/10
CPC分类号： H01L29/66363 , H01L29/0634 , H01L29/102 , H01L29/7455 , H01L29/749
摘要： The invention relates to a power semiconductor component, e.g. an emitter switched thyristor comprising an anode contact at the rear (502), an emitter region (505) of a first conductivity type (p+) (504, 514, 540) and a drift region, which extends partially to the front surface; a front MOS control structure (503, 506, 560, 508, 580, 509); and a front cathode contact (501). The drift region (504, 514, 540) has a first drift zone (540) of the second conductivity type (n-), a second drift zone (504) of the second conductivity type (n) and a third drift zone (514) of the first conductivity type (p). The first drift zone (540) is a buried zone. The second drift zone (504) connects the front surface with the first drift zone (540). The third drift zone (514) connects the first and/or the second body region (508, 580) with the first drift zone (540).

10. 发明公开

EP1062692A1 DEVICES FORMABLE BY LOW TEMPERATURE DIRECT BONDING 审中-公开
标题翻译： BY DIRECT低温键联产生的安排
公开(公告)号：EP1062692A1
公开(公告)日：2000-12-27
申请号：EP99912328.4
申请日：1999-03-09
申请人： HARRIS CORPORATION
发明人： KUB, Francis, J. , TEMPLE, Victor, Keith , NEILSON, John, Manning, Savidge , HOBART, Karl
IPC分类号： H01L21/18 , H01L29/739 , H01L29/74
CPC分类号： H01L29/66348 , H01L21/187 , H01L29/1608 , H01L29/66068 , H01L29/66363 , H01L29/66424
摘要： A semiconductor device includes a laterally extending semiconductor base (82, 96), a buffer (83) adjacent the base and having a first conductivity type dopant, and a laterally extending emitter (85) adjacent the buffer and opposite the base and having a second conductivity type dopant. The buffer (83) is thin and has a fist conductivity type dopant concentration greater than a second conductivity type dopant concentration in adjacent emitter portions to provide a negative temperature coefficient for current gain and a positive temperature coefficient for forward voltage for the device. The buffer may be silicon or germanium. A low temperature bonded interface (103) may be between the emitter and the buffer or the buffer and the base. Another embodiment of a device may include a laterally extending localized lifetime killing portion (92, 102) between oppositely doped first and second laterally extending portions. The localized lifetime killing portion may comprise a plurality of laterally confined and laterally space apart lifetime killing regions. Another device may include one or more PN junctions.

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