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    • 6. 发明公开
    • FLASH-CLEAR OF RAM ARRAY USING PARTIAL RESET MECHANISM
    • BY局部RUECKSTELLMECHANISMUS的应用RAM矩阵的快速求解。
    • EP0640238A1
    • 1995-03-01
    • EP93901100.0
    • 1992-12-24
    • HARRIS CORPORATION
    • LANDETA, David, S.YOUNG, William, RonaldLONGWAY, Charles, William, Tull
    • G11C7G11C8
    • G11C7/20G11C8/16Y10S257/903Y10S257/904
    • A reset mechanism for a random access memory array comprises an auxiliary reset circuit, which does not require modification of the contents of the memory itself. For a random access memory capable of storing M, N-bit words, the auxiliary mechanism includes a plurality of M reset state circuits that are respectively associated with the M words of memory. The reset state circuit preferably comprises an additional 'resetable' memory cell for each word of memory, which is integrated within the structure of the memory itself. In order to reset one or more words of memory, the associated reset state circuits are placed in a reset state-representative condition. The state of each reset state circuit is used to controllably mask (e.g. is logically ANDed with) the contents of its associated word of memory, whenever that word is read out. If the reset memory cell has been cleared, then regardless of the contents of its associated word in memory, the mask will cause the addressed memory word to be ouput as all zeros. Whenever a new word value is written to memory, its associated reset state circuit is simultaneously accessed and a valid or non-reset representative '1' bit is stored in that reset state circuit. Subsequently, when that word is read out from memory, the ('1') value of the mask bit stored in its associated reset cell will cause the contents of the word to be output as it is.
    • 9. 发明公开
    • Static RAM memory integrated circuit
    • 统计员RAM-Speiserher在einer integrierten Schaltung。
    • EP0550175A1
    • 1993-07-07
    • EP92311253.6
    • 1992-12-10
    • AT&T Corp.
    • Lee, Kuo-HuaSung, Janmye
    • H01L27/11
    • H01L27/1108Y10S257/904
    • A static RAM is disclosed of the type comprising two access transistors (gates 25,26) and a flip-flop including two pull-down transistors (gates 23,28), the access transistors being connected in series with respective pull-down transistors via conductive paths (13,16) and a point between each access transistor and its respective pull-down transistor being connected to the gate of the other pull-down transistor. In the SRAM which is disclosed, the contacts to the points between the access transistors and pull-down transistors are made through windows (300,302) which are adjacent to, but not actually in, the respect conductive paths. Thus, over-etching of the windows does not adversely affect the conductive paths.
    • 公开了包括两个存取晶体管(门25,26)和包括两个下拉晶体管(门23,28)的触发器的类型的静态RAM,该存取晶体管与相应的下拉晶体管串联连接,经由 导电路径(13,16),并且每个存取晶体管及其相应的下拉晶体管之间的点连接到另一个下拉晶体管的栅极。 在所公开的SRAM中,通过与相对的导电路径相邻而不是实际在其中的窗口(300,302)制造在存取晶体管和下拉晶体管之间的点的触点。 因此,窗口的过度蚀刻不会不利地影响导电路径。