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1. 发明授权

EP1154488B1 A semiconductor memory device 失效
标题翻译：半导体存储装置
公开(公告)号：EP1154488B1
公开(公告)日：2003-05-07
申请号：EP01105309.7
申请日：1993-08-03
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Kuriyama, Hirotada, Mitsubishi Denki K.K. LSI
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904

2. 发明授权

EP0600488B1 Lead frame capacitor 失效
标题翻译： Leiterrahmen-Kondensator
公开(公告)号：EP0600488B1
公开(公告)日：2002-07-24
申请号：EP93119453.4
申请日：1993-12-02
申请人： LINEAR TECHNOLOGY CORPORATION
发明人： Dobkin, Robert C. , Reay, Robert L.
IPC分类号： H01L23/64 , H01L23/495 , H03K5/24
CPC分类号： H01L23/49575 , H01L23/49589 , H01L23/642 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2924/00014 , H01L2924/01014 , H01L2924/10162 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H05K1/162 , H05K3/202 , Y10S257/904 , Y10T29/435 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399

3. 发明公开

EP1154488A1 A semiconductor memory device and a manufacturing method of the same 失效
标题翻译： Halbleiterspeicherbauelement und Verfahren zu dessen Herstellung
公开(公告)号：EP1154488A1
公开(公告)日：2001-11-14
申请号：EP01105309.7
申请日：1993-08-03
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Kuriyama, Hirotada, Mitsubishi Denki K.K. LSI
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A memory cell of an SRAM prevents imbalance between GND potentials of a pair of driver transistors. In the memory cell, the driver transistors Q 1 and Q 2 in a pair have the common source region (9).
摘要翻译： SRAM的存储单元防止一对驱动晶体管的GND电位之间的不平衡。在存储单元中，一对驱动晶体管Q1和Q2具有公共源极区（9）。

4. 发明公开

EP1153435A1 TRANSISTOR MOS A TENSION DE SEUIL DYNAMIQUE EQUIPE D'UN LIMITEUR DE COURANT, ET PROCEDE DE REALISATION D'UN TEL TRANSISTOR 审中-公开
标题翻译：与具有限流器和这样的晶体管的过程EQUIPPED动态阈值MOS晶体管
公开(公告)号：EP1153435A1
公开(公告)日：2001-11-14
申请号：EP00901716.1
申请日：2000-02-04
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE
发明人： PELLOIE, Jean-Luc
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , Y10S257/903 , Y10S257/904
摘要： The invention concerns a semiconductor device comprising on a substrate: a first MOS transistor (10) with dynamic threshold voltage, with a gate (116), and a channel having one first type of conductivity, and a current limiting element (20) connected between said first transistor gate and channel. The invention is characterised in that said first transistor is provided with a first zone (160) doped with the first type of conductivity, connected to the channel, and the current limiting element comprises a second zone (124) doped with a second type of conductivity and electrically connected to the first zone by an ohmic connection. The invention is useful for producing CMOS circuits.

5. 发明公开

EP1040517A2 SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD FOR SEMICONDUCTOR COMPONENT 有权
标题翻译：半导体部件及其制造方法
公开(公告)号：EP1040517A2
公开(公告)日：2000-10-04
申请号：EP98954909.2
申请日：1998-11-16
申请人： Telefonaktiebolaget L M Ericsson (Publ)
发明人： SÖDERBÄRG, Anders , SJÖDIN, H kan
IPC分类号： H01L21/763 , H01L21/74 , H01L21/762 , H01L29/08 , H01L29/732
CPC分类号： H01L29/66265 , H01L21/84 , H01L27/1203 , H01L29/0821 , H01L29/66772 , H01L29/7809 , Y10S257/904
摘要： A semiconductor comprising a buried conducting layer (108), such as a buried collector, comprises a trench, the walls of which are covered with a layer (109') of a material in which dopant ions diffuse faster than in monocrystalline silicon. A contact area is doped in close proximity to the trench wall (109'). The dopants will diffuse through the layer (109') and form a low resistance connection to the buried layer (108). The layer (109') may comprise polysilicon or porous silicon, or a silicide. If the material used in the layer (109') is not in itself conducting, the size of the component may be significantly reduced.

6. 发明公开

EP0640238A1 FLASH-CLEAR OF RAM ARRAY USING PARTIAL RESET MECHANISM 失效
标题翻译： BY局部RUECKSTELLMECHANISMUS的应用RAM矩阵的快速求解。
公开(公告)号：EP0640238A1
公开(公告)日：1995-03-01
申请号：EP93901100.0
申请日：1992-12-24
申请人： HARRIS CORPORATION
发明人： LANDETA, David, S. , YOUNG, William, Ronald , LONGWAY, Charles, William, Tull
IPC分类号： G11C7 , G11C8
CPC分类号： G11C7/20 , G11C8/16 , Y10S257/903 , Y10S257/904
摘要： A reset mechanism for a random access memory array comprises an auxiliary reset circuit, which does not require modification of the contents of the memory itself. For a random access memory capable of storing M, N-bit words, the auxiliary mechanism includes a plurality of M reset state circuits that are respectively associated with the M words of memory. The reset state circuit preferably comprises an additional 'resetable' memory cell for each word of memory, which is integrated within the structure of the memory itself. In order to reset one or more words of memory, the associated reset state circuits are placed in a reset state-representative condition. The state of each reset state circuit is used to controllably mask (e.g. is logically ANDed with) the contents of its associated word of memory, whenever that word is read out. If the reset memory cell has been cleared, then regardless of the contents of its associated word in memory, the mask will cause the addressed memory word to be ouput as all zeros. Whenever a new word value is written to memory, its associated reset state circuit is simultaneously accessed and a valid or non-reset representative '1' bit is stored in that reset state circuit. Subsequently, when that word is read out from memory, the ('1') value of the mask bit stored in its associated reset cell will cause the contents of the word to be output as it is.

7. 发明公开

EP0603158A2 Advanced multilayer molded plastic package using mesic technology 失效
标题翻译：在MESIC-Technologie中的Verbosityes gegossenesMehrlagenplastikgehäuse。
公开(公告)号：EP0603158A2
公开(公告)日：1994-06-22
申请号：EP94101294.0
申请日：1993-02-18
申请人： SUMITOMO ELECTRIC INDUSTRIES, LIMITED
发明人： Bhattacharyya, Bidyut K. , Mallik, Debendra , Ban, Syunsuke , Takikawa, Takatoshi , Yamanaka, Shosaku
IPC分类号： H01L23/48 , H01L29/40 , H01L29/44 , H01L29/60 , H01L29/54 , H01L23/495 , H01L23/64
CPC分类号： H01L23/495 , H01L23/49527 , H01L23/49534 , H01L23/49537 , H01L23/49589 , H01L23/642 , H01L23/647 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/49109 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01051 , H01L2924/01052 , H01L2924/01057 , H01L2924/01073 , H01L2924/01074 , H01L2924/04953 , H01L2924/10253 , H01L2924/12033 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/16195 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , Y10S257/904 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A method and resulting structure for constructing an IC package utilizing thin film technology. The package has a bottom conductive plate (10) that has a layer of ceramic vapor deposited onto the plate in a predetermined pattern. Adjacent to the insulative layer of ceramic is a layer of conductive metal (24) vapor deposited onto the ceramic. The layer of metal can be laid down onto the ceramic in a predetermined pattern to create a power plane, a plurality of signal lines, or a combination of power planes and signal lines. On top of the layer of conductive material is a lead frame (34) separated by a layer of insulative polyimide material. The polyimide material has a plurality of holes filled with a conductive material (38), which electrically couple the layer of conductive material with the leads of the lead frame. The power and ground pads of the integrated circuit are connected to the layer of vapor deposited conductive material and conductive plate, which are also coupled to the corresponding leads of the lead frame, thereby connecting the IC to the leads of the lead frame. The signal pads of the IC are connected to the lead frame and/or signal lines formed within the layer of vapor deposited conductive material. The IC and attached circuit package can then be encapsulated in a plastic shell.
摘要翻译：一种利用薄膜技术构建IC封装的方法和结果。封装具有底部导电板（10），其具有以预定图案沉积在板上的陶瓷气相层。与陶瓷绝缘层相邻的是沉积在陶瓷上的导电金属层（24）。金属层可以以预定图案放置在陶瓷上，以产生电力平面，多条信号线或电力平面和信号线的组合。在导电材料层的顶部是由绝缘聚酰亚胺材料层隔开的引线框架（34）。聚酰亚胺材料具有填充有导电材料（38）的多个孔，其将导电材料层与引线框架的引线电耦合。集成电路的电源和接地焊盘连接到蒸镀导电材料和导电板的层上，导电板也耦合到引线框架的相应引线，从而将IC连接到引线框的引线。 IC的信号焊盘连接到形成在蒸镀导电材料层内的引线框和/或信号线。然后将IC和附接电路封装封装在塑料外壳中。

8. 发明公开

EP0550177A1 Static RAM memory integrated circuit with balanced resistance 失效
标题翻译： Statischer RAM-Speicher mit abgeglichenem Widerstand in einer integrierten Schaltung。
公开(公告)号：EP0550177A1
公开(公告)日：1993-07-07
申请号：EP92311258.5
申请日：1992-12-10
申请人： AT&T Corp.
发明人： Lee, Kuo-Hua , Sung, Janmye
IPC分类号： H01L27/11
CPC分类号： H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： An integrated circuit, illustratively an SRAM, with pull down gates (e.g., 28, 23) symmetrically positioned with respect to the ground line (e.g., 31) is disclosed. The symmetric positioning helps to insure cell stability.
摘要翻译：公开了一种集成电路，例如SRAM，其具有相对于接地线（例如31）对称定位的下拉门（例如，28,23）。对称定位有助于确保细胞稳定性。

9. 发明公开

EP0550175A1 Static RAM memory integrated circuit 失效
标题翻译：统计员RAM-Speiserher在einer integrierten Schaltung。
公开(公告)号：EP0550175A1
公开(公告)日：1993-07-07
申请号：EP92311253.6
申请日：1992-12-10
申请人： AT&T Corp.
发明人： Lee, Kuo-Hua , Sung, Janmye
IPC分类号： H01L27/11
CPC分类号： H01L27/1108 , Y10S257/904
摘要： A static RAM is disclosed of the type comprising two access transistors (gates 25,26) and a flip-flop including two pull-down transistors (gates 23,28), the access transistors being connected in series with respective pull-down transistors via conductive paths (13,16) and a point between each access transistor and its respective pull-down transistor being connected to the gate of the other pull-down transistor. In the SRAM which is disclosed, the contacts to the points between the access transistors and pull-down transistors are made through windows (300,302) which are adjacent to, but not actually in, the respect conductive paths. Thus, over-etching of the windows does not adversely affect the conductive paths.
摘要翻译：公开了包括两个存取晶体管（门25,26）和包括两个下拉晶体管（门23,28）的触发器的类型的静态RAM，该存取晶体管与相应的下拉晶体管串联连接，经由导电路径（13,16），并且每个存取晶体管及其相应的下拉晶体管之间的点连接到另一个下拉晶体管的栅极。在所公开的SRAM中，通过与相对的导电路径相邻而不是实际在其中的窗口（300,302）制造在存取晶体管和下拉晶体管之间的点的触点。因此，窗口的过度蚀刻不会不利地影响导电路径。

10. 发明公开

EP0002486A1 Statische Speicherzelle aus zwei Feldeffekttransistoren und Verwendung derselben in einem programmierfähigen logischen Schaltungsverband 失效
标题翻译：静态存储单元包括两个场效应晶体管，和在能够敷料的编程电路使用相同的逻辑。
公开(公告)号：EP0002486A1
公开(公告)日：1979-06-27
申请号：EP78101565.6
申请日：1978-12-05
申请人： International Business Machines Corporation
发明人： Bertin, Claude Louis
IPC分类号： H01L29/62 , G11C11/40 , H01L27/10 , H03K3/353
CPC分类号： H01L27/11 , G11C7/20 , H01L29/435 , H03K3/356 , H03K3/35606 , Y10S257/904
摘要： Es wird eine statische Speicherzelle aus zwei Feldeffekttransistoren beschrieben, deren Elektroden untereinander und/oder mit Ansteuer-, Ein- und Ausgangsleitungen in einen Speicherzellenverband oder in einer Anordnung aus vielen steuerbaren logischen Schaltungen in Verbindung stehen, wobei die Feldeffekttransistoren der Speicherzelle mit einer als Widerstand ausgebildeten Gate-Elektrode ausgerüstet sind. Das als Widerstand ausgebildete Gate ist über dem Kanalbereich angeordnet und trennt die Source-, Drain-Diffusionen voneinander, die aus polykristallinem Silicium mit hohem Widerstandswert bestehen.
摘要翻译：它是由两个场效应晶体管静态存储器单元，其中所述电极是彼此描述和/或与致动，在存储器单元关联或在连接的许多可控逻辑电路的布置的输入和输出线，所述形成所述存储器单元的场效应晶体管与电阻设置栅电极。所形成的电阻栅极设置在所述沟道区和分离所述源极，漏极彼此的扩散，其由具有高电阻值的多晶硅。

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