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1. 发明公开

EP3341939A1 MEMORY DEVICE CHECK BIT READ MODE 有权
公开(公告)号：EP3341939A1
公开(公告)日：2018-07-04
申请号：EP16842531.2
申请日：2016-08-04
申请人： Intel Corporation
发明人： HALBERT, John B , BAINS, Kuljit S
IPC分类号： G11C11/409 , G06F11/10
CPC分类号： G06F11/1048 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1068 , G11C11/401 , G11C29/42 , G11C29/52 , H03M13/095 , H03M13/6566
摘要： An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

2. 发明授权

EP2993587B1 BACKUP SYSTEM FOR VOLATILE MEMORY USING ALL-SOLID-STATE BATTERY 有权
标题翻译：备份系统对于固体电池的易失性存储器
公开(公告)号：EP2993587B1
公开(公告)日：2017-02-22
申请号：EP15781842.8
申请日：2015-04-08
申请人： NGK Insulators, Ltd.
发明人： OHWADA, Iwao , KITOH, Kenshin
IPC分类号： H02J9/06 , G06F11/14 , G06F12/16 , G11C5/14 , G11C11/401 , G11C14/00 , H01M4/131 , H01M4/485 , H01M10/052 , H01M10/0525 , H01M10/0562 , H01M10/058 , H01M10/0585 , G11C11/00 , G11C11/4072 , G06F11/20
CPC分类号： H01M10/0585 , G06F11/1441 , G06F11/2015 , G06F12/16 , G11C5/141 , G11C11/005 , G11C11/401 , G11C11/4072 , G11C14/0018 , H01M4/131 , H01M4/485 , H01M4/505 , H01M4/525 , H01M10/052 , H01M10/0525 , H01M10/0562 , H01M10/0565 , H01M10/058 , H01M2004/028 , H01M2220/30 , H01M2300/0068 , H02J9/061 , Y02E60/122

3. 发明公开

EP2786409A4 CPU WITH STACKED MEMORY 审中-公开
标题翻译： CPU堆栈存储器
公开(公告)号：EP2786409A4
公开(公告)日：2015-09-09
申请号：EP12854424
申请日：2012-11-29
申请人： CONVERSANT INTELLECTUAL PROPERTY MAN INC
发明人： PYEON HONG BEOM
IPC分类号： H01L25/18 , G06F1/18 , G06F1/20 , G06F15/78 , G11C11/401
CPC分类号： G06F1/18 , G06F1/203 , G06F15/78 , G11C11/401 , H01L25/18 , H01L2224/16225 , H01L2224/73253 , H01L2924/0002 , H01L2924/15311 , H01L2924/00

4. 发明授权

EP1388865B1 Semiconductor memory device and control method therefor 有权
标题翻译：半导体存储器及其控制方法
公开(公告)号：EP1388865B1
公开(公告)日：2013-08-28
申请号：EP03016890.0
申请日：2003-07-24
申请人： Fujitsu Semiconductor Limited
发明人： Nakagawa, Yuji
IPC分类号： G11C11/406 , G11C29/50
CPC分类号： G11C29/50012 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C29/50 , G11C29/50016

5. 发明授权

EP2003652B1 SEMICONDUCTOR MEMORY AND TEST SYSTEM 有权
标题翻译：半导体存储器测试系统
公开(公告)号：EP2003652B1
公开(公告)日：2010-11-17
申请号：EP06730214.1
申请日：2006-03-28
申请人： Fujitsu Semiconductor Limited
发明人： KOBAYASHI, Hiroyuki
IPC分类号： G11C29/44 , G11C29/12 , G11C29/50
CPC分类号： G11C29/44 , G11C11/401 , G11C29/026 , G11C29/1201 , G11C29/50 , G11C29/78
摘要： A cell array comprises a word line and a bit line which are connected to a memory cell, and a redundant word line and a redundant bit line which are connected to a redundant memory cell. A reading section reads data held in the memory cell. A defect detecting input section receives a defect detecting signal from a test device. A dummy defect output section outputs a dummy defect signal during a predetermined period of time after the defect detecting input section receives the defect detecting signal. A data output section inverts the logic of the read data outputted from a reading circuit while the dummy defect signal is activated. This enables generation of a pseudo defect by means of a semiconductor memory without changing any test device or test program. More specifically, a single bit defect can be replaced by a predetermined bit line defect or word line defect without changing any testing environment. As a result, the efficiency of the remedy can be improved to reduce the cost of the test.

6. 发明授权

EP1315176B1 Memory circuit having parity cell array 有权
标题翻译：具有奇偶校验单元阵列存储器电路
公开(公告)号：EP1315176B1
公开(公告)日：2009-10-21
申请号：EP02257328.1
申请日：2002-10-22
申请人： Fujitsu Microelectronics Limited
发明人： Fujioka, Shinya , Fujieda, Waichiro , Hara, Kota , Koga, Toru , Mori, Katsuhiro
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G06F11/106 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C2211/4062

7. 发明公开

EP1895539A3 Semiconductor device and fabrication method thereof 有权
公开(公告)号：EP1895539A3
公开(公告)日：2008-11-12
申请号：EP07107083.3
申请日：2007-04-27
申请人： FUJITSU LIMITED
发明人： Tomita, Hiroyoshi
IPC分类号： G11C11/404
CPC分类号： G11C11/4074 , G11C11/401 , G11C29/50 , G11C2029/0403 , G11C2207/2254 , H01L27/0207 , H01L27/10829
摘要： The present invention suppresses the refresh failure of a DRAM due to the dispersion of a threshold of a MOSFET. The DRAM has a first unit (5) for recording a set value of a back bias potential to be applied to a back gate of a cell transistor and a second unit (8, 9) for generating a back bias potential (V BB ) based on the set value of the back bias potential recorded in the first unit and supplying the generated back bias potential to the back gate, wherein when a threshold of a MOSFET which has a structure identical to the cell transistor and which has been fabricated in the same process as the cell transistor is greater than a target value which the cell transistor should have, a value shallower than the back bias potential for the target value is recorded in the second unit.

8. 发明公开

EP1934982A2 DRAM DENSITY ENHANCEMENTS 审中-公开
标题翻译： DRAM密度的改进
公开(公告)号：EP1934982A2
公开(公告)日：2008-06-25
申请号：EP06801760.7
申请日：2006-08-16
申请人： Novelics
发明人： TERZIOGLU, Esin , WINOGRAD, Gil, I. , AFGHAHI, Morteza, Cyrus
IPC分类号： G11C7/02
CPC分类号： G11C11/4091 , G11C7/02 , G11C7/065 , G11C7/12 , G11C11/401 , G11C11/4094 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2207/2254 , H01L27/0207 , H01L27/10873 , H03K3/356034
摘要： In one embodiment, a sense amplifier includes: a differential amplifier adapted to amplify a voltage difference between a pair of bit lines; and a self-bias generation circuit adapted to reduce an offset bias in the differential amplifier with regard to the amplification of the voltage difference between the pair of bit lines.

9. 发明公开

EP1858024A1 Semiconductor memory and refresh cycle control method 有权
标题翻译： Halbleiterspeicher und Steuerungsverfahrenfürden Auffrischungszyklus
公开(公告)号：EP1858024A1
公开(公告)日：2007-11-21
申请号：EP07107117.9
申请日：2007-04-27
申请人： Fujitsu Ltd.
发明人： Mori, Kaoru
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C7/04 , G11C11/401 , G11C11/40626 , G11C29/02 , G11C29/028 , G11C2029/0409 , G11C2029/5002 , G11C2211/4061 , G11C2211/4067
摘要： A semiconductor memory and a refresh cycle control method that reduce a standby current by properly changing a refresh cycle according to the temperature of the semiconductor memory. A temperature detection section (101) detects the temperature of the semiconductor memory. A cycle change control section (102) sends a cycle change signal for changing a refresh cycle when the temperature of the semiconductor memory reaches a predetermined cycle change temperature. A refresh timing signal generation section (103) generates a refresh timing signal and changes the cycle of the refresh timing signal in response to the cycle change signal. A constant current generation circuit (104) generates an electric current for generating the refresh timing signal. A low-temperature constant current setting circuit (105) designates the level of the electric current generated in the case that the temperature of the semiconductor memory is lower than or equal to the cycle change temperature. A high-temperature constant current setting circuit (106) designates the level of the electric current generated in the case that the temperature of the semiconductor memory is higher than the cycle change temperature.
摘要翻译：一种半导体存储器和刷新周期控制方法，其通过根据半导体存储器的温度适当地改变刷新周期来减少待机电流。温度检测部（101）检测半导体存储器的温度。当半导体存储器的温度达到预定的周期变化温度时，循环变化控制部分（102）发送用于改变刷新周期的循环改变信号。刷新定时信号生成部（103）生成刷新定时信号，根据周期变更信号改变刷新定时信号的周期。恒定电流产生电路（104）产生用于产生刷新定时信号的电流。低温恒流设定电路（105）表示在半导体存储器的温度低于或等于循环变化温度的情况下产生的电流的电平。高温恒流设定电路（106）表示在半导体存储器的温度高于循环变化温度的情况下产生的电流的电平。

10. 发明公开

EP1668671A4 APPARATUS AND METHOD FOR SELECTIVELY CONFIGURING A MEMORY DEVICE USING A BI-STABLE RELAY 审中-公开
标题翻译： DEVICE AND METHOD FOR选择性记忆模块上配置使用双稳态继电器
公开(公告)号：EP1668671A4
公开(公告)日：2007-09-19
申请号：EP04782405
申请日：2004-08-26
申请人： MICRON TECHNOLOGY INC
发明人： GOMM TYLER J
IPC分类号： G11C7/00 , G06F11/00 , G11C7/10 , G11C8/00 , G11C11/4093 , G11C23/00 , G11C29/00 , G11C29/48 , H01L20060101
CPC分类号： G11C29/883 , G11C7/10 , G11C11/401 , G11C11/4093 , G11C23/00 , G11C29/1201 , G11C29/48 , G11C29/88 , G11C2207/2254
摘要： The disclosed embodiment of the present invention include a system that includes input, output (88) and a data storage device (82), processor (102) coupled to the devcie, a memory device (108) coupled to the processor (102), and a configuration circuit (92) interposed between the processor (102) and the memory device (108) to selectively couple lines in the address (86), control (90) an data buses (88) of the processor to lines in the address (86), control (90) and data buses (88) of the memory device (108).

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