专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP4396873A1 TUNED DATAPATH IN STACKED MEMORY DEVICE 审中-实审
公开(公告)号：EP4396873A1
公开(公告)日：2024-07-10
申请号：EP22865247.5
申请日：2022-06-28
申请人： Micron Technology, Inc
发明人： GIDUTURI, Hari , JOHNSON, Bret Addison
IPC分类号： H01L25/065 , H01L25/00
CPC分类号： G11C5/04 , G11C7/22 , G11C5/02 , G11C29/023 , G11C29/028 , G11C29/12015 , G11C29/46 , G11C29/1201 , G11C2207/225420130101

2. 发明公开

EP3084648A4 STORAGE ELEMENT WITH STORAGE AND CLOCK TREE MONITORING CIRCUIT AND METHODS THEREFOR 审中-公开
标题翻译： SPEICHERELEMENT MIT EINER SPEICHERUNGS- UND EINER TAKTHIERARCHIE-ÜBERWACHUNGSSCHALTUNGUND VERFAHRENDAFÜR
公开(公告)号：EP3084648A4
公开(公告)日：2017-08-09
申请号：EP13899573
申请日：2013-12-18
申请人： NXP USA INC
发明人： ROHLEDER MICHAEL , KOCH THOMAS , LUEPKEN HARALD
IPC分类号： G06F17/50 , G01R31/317 , G06F1/10 , G06F11/16 , G06F11/18 , G11C29/00 , H03K3/037 , H03K19/003 , H03K19/007
CPC分类号： G11C14/00 , G06F1/10 , G06F21/558 , G06F2217/62 , G11C7/10 , G11C29/023 , G11C29/1201 , G11C29/12015 , G11C29/44 , G11C29/50012 , G11C29/74 , G11C2029/4402 , H03K3/0375
摘要： A storage element with monitoring circuit, comprising a previous state information storage element configured to record a previous state of a monitored state information storage element, a state change indication unit having a clock input terminal coupled to the clock signal input interface, a state change indication unit being configured to generate a state change indication signal indicative of whether the monitored state information storage element shall have performed a state change by observing the data at a data input interface and a data output terminal, and a state change confirmation unit configured to generate a storage fault indicator by observing the data output terminal of the monitored state information storage element and the data output of the previous state information storage element and checking whether the result of this observation is in line with the state change indicator.
摘要翻译：一种具有监控电路的存储元件，包括：先前状态信息存储元件，被配置为记录被监控状态信息存储元件的先前状态;状态改变指示单元，具有耦合到时钟信号输入接口的时钟输入端子;状态改变指示单元，被配置为通过观察数据输入接口和数据输出端子处的数据来生成状态改变指示信号，所述状态改变指示信号指示所监视的状态信息存储元件是否应当已经执行了状态改变;以及状态改变确认单元，通过观察被监控的状态信息存储元件的数据输出端和先前的状态信息存储元件的数据输出并且检查该观察的结果是否与状态改变指示符一致来存储故障指示器。

3. 发明公开

EP3084648A1 STORAGE ELEMENT WITH STORAGE AND CLOCK TREE MONITORING CIRCUIT AND METHODS THEREFOR 审中-公开
标题翻译：与商店和-一举层次监控电路及其方法存储器元件
公开(公告)号：EP3084648A1
公开(公告)日：2016-10-26
申请号：EP13899573.3
申请日：2013-12-18
申请人： Freescale Semiconductor, Inc.
发明人： ROHLEDER, Michael , KOCH, Thomas , LUEPKEN, Harald
IPC分类号： G06F17/50 , G06F1/10
CPC分类号： G11C14/00 , G06F1/10 , G06F2217/62 , G11C7/10 , G11C29/023 , G11C29/1201 , G11C29/12015 , G11C29/44 , G11C29/50012 , G11C29/74 , G11C2029/4402 , H03K3/0375
摘要： A storage element with monitoring circuit, comprising a previous state information storage element configured to record a previous state of a monitored state information storage element, a state change indication unit having a clock input terminal coupled to the clock signal input interface, a state change indication unit being configured to generate a state change indication signal indicative of whether the monitored state information storage element shall have performed a state change by observing the data at a data input interface and a data output terminal, and a state change confirmation unit configured to generate a storage fault indicator by observing the data output terminal of the monitored state information storage element and the data output of the previous state information storage element and checking whether the result of this observation is in line with the state change indicator.
摘要翻译：与监视电路的存储元件，包括被配置为记录一个监控的状态信息存储元件的先前状态的先前状态信息存储元件，为stateChange指示单元具有时钟输入端耦合到所述时钟信号输入接口，一个状态改变指示单元被配置为生成指示是否被监视的状态信息存储元件，由在一个数据输入接口和数据输出端子观察数据已经执行了为stateChange的状态改变指示信号，并为stateChange确认单元，被配置以产生一通过观察所监视的状态信息的存储元件的数据输出端与先前的状态信息存储元件的数据输出，并检查是否该观察的结果与状态改变指示线存储故障指示器。

4. 发明公开

EP2898334A4 METHOD, SYSTEM AND APPARATUS FOR EVALUATION OF INPUT/OUTPUT BUFFER CIRCUITRY 有权
标题翻译：方法，系统和设备评估输入/输出缓冲电路
公开(公告)号：EP2898334A4
公开(公告)日：2016-06-01
申请号：EP13838100
申请日：2013-06-14
申请人： INTEL CORP
发明人： NELSON CHRISTOPHER J , MAK TAK M , ZIMMERMAN DAVID J , VOGT PETE D
IPC分类号： G01R29/02 , G01R31/317 , G01R31/3177 , G01R31/3181 , G01R31/3187 , G06F11/34 , G11C7/10 , G11C29/02 , G11C29/12 , G11C29/32 , H04L1/24
CPC分类号： G01R31/31716 , G01R31/31713 , G01R31/3177 , G01R31/3181 , G01R31/3187 , G06F11/3485 , G11C7/10 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C29/32 , H04L1/243
摘要： Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.

5. 发明公开

EP3016026A2 Integrated capacitance sensing module and associated system 有权
标题翻译：集成电容感应模块和相关系统
公开(公告)号：EP3016026A2
公开(公告)日：2016-05-04
申请号：EP15178641.5
申请日：2015-07-28
申请人： eMemory Technology Inc.
发明人： Chen, Wei-Ren , Lee, Wen-Hao , Liu, Hsin-Chou , Yang, Ching-Sung
IPC分类号： G06K9/00
CPC分类号： G01D5/24 , G06K9/0002 , G11C29/1201 , G11C29/78 , H01L23/552 , H01L27/0248 , H01L27/11206 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： An integrated capacitance sensing module includes a silicon substrate, a first and a second and a third interlayer dielectric layers, plural conducting layers, a shielding layer, a lower and a upper sensing electrode layers, a protective coating layer. An embedded memory and a sensing circuit are constructed in the silicon substrate. The first interlayer dielectric layer covers the silicon substrate. The plural conducting layers are formed over the first interlayer dielectric layer. The shielding layer is formed over the plural conducting layers. The second interlayer dielectric layer covers the shielding layer. The lower sensing electrode layer is formed over the second interlayer dielectric layer. The third interlayer dielectric layer is formed over the lower sensing electrode layer. The upper sensing electrode layer is formed over the third interlayer dielectric layer. The protective coating layer covers the upper sensing electrode layer.
摘要翻译：一种集成电容感应模块，包括硅基板，第一和第二以及第三层间介电层，多个导电层，屏蔽层，下感应电极层和上感应电极层，保护涂层。嵌入式存储器和传感电路被构建在硅衬底中。第一层间介电层覆盖硅衬底。多个导电层形成在第一层间电介质层上。屏蔽层形成在多个导电层上。第二层间介电层覆盖屏蔽层。下感测电极层形成在第二层间电介质层上。第三层间电介质层形成在下感测电极层上方。上感测电极层形成在第三层间电介质层之上。保护涂层覆盖上部感测电极层。

6. 发明公开

EP2920787A1 THREE-DIMENSIONAL FLASH MEMORY SYSTEM 有权
标题翻译：幻灯片FLASHSPEICHERSYSTEM
公开(公告)号：EP2920787A1
公开(公告)日：2015-09-23
申请号：EP13783743.1
申请日：2013-10-09
申请人： Silicon Storage Technology Inc.
发明人： TRAN, Hieu, Van , NGUYEN, Hung, Quoc , REITEN, Mark
IPC分类号： G11C5/02 , G11C5/06 , G11C16/30 , H01L21/768 , H01L23/48 , H01L25/065 , H01L25/00 , G11C29/26
CPC分类号： G11C29/76 , G11C5/02 , G11C5/06 , G11C7/04 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C29/021 , G11C29/022 , G11C29/028 , G11C29/1201 , G11C29/26 , G11C2213/71 , H01L25/0652 , H01L25/18 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311
摘要： A three-dimensional flash memory system is disclosed.
摘要翻译：公开了三维闪存系统。

7. 发明公开

EP2533277A2 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：EP2533277A2
公开(公告)日：2012-12-12
申请号：EP12170813.5
申请日：2012-06-05
申请人： Elpida Memory, Inc.
发明人： Ishikawa, Toru
IPC分类号： H01L21/66 , H01L23/48
CPC分类号： G11C7/1057 , G01R31/2884 , G11C5/04 , G11C7/1051 , G11C29/1201 , G11C29/48 , H01L22/34 , H01L23/481 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2924/15311
摘要： A device includes a semiconductor substrate, a first penetrating electrode (TSV_0) penetrating through the semiconductor substrate, a first test pad (PAD_0), and a first tri-state buffer (TD_0) coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The device further includes a buffer control circuit (BC) supplying the buffer control signal to the first tri-state buffer.
摘要翻译：一种器件包括半导体衬底，穿透半导体衬底的第一穿透电极（TSV_0），第一测试焊盘（PAD_0）和耦合在第一穿透电极和第一测试焊盘之间的第一三态缓冲器（TD_0）。第一三态缓冲器在其控制端接收缓冲控制信号。该装置还包括将缓冲控制信号提供给第一三态缓冲器的缓冲器控制电路（BC）。

8. 发明公开

EP2421004A1 Method and device for testing memory 有权
标题翻译： Verfahren und Vorrichtung zumPrüfeneines Speichers
公开(公告)号：EP2421004A1
公开(公告)日：2012-02-22
申请号：EP11188850.9
申请日：2007-12-14
申请人： Qualcomm Incorporated
发明人： Shen, Jian , Bassett, Paul
IPC分类号： G11C29/48
CPC分类号： G11C29/48 , G11C29/1201
摘要： A method is disclosed, the method comprising initiating a test on a computer readable memory comprising a first input and a first output, the computer readable memory providing output data associated with the test; selecting to receive the output data from one of a first register and a second register the first register comprising a second input and a second output, the second output coupled to the first input of the computer readable memory, and the second register comprising a third input and a third output, the third input coupled to the first output of the computer readable memory; receiving data during a write operation at a first input of a first multiplexer, the first multiplexer comprising a fourth output coupled to the second input of the first register; and receiving data during a test mode write operation at a second input of the first multiplexer, wherein a third input of the first multiplexer is coupled to the first output of the computer readable memory.
摘要翻译：公开了一种方法，所述方法包括在包括第一输入和第一输出的计算机可读存储器上启动测试，所述计算机可读存储器提供与所述测试相关联的输出数据; 选择从第一寄存器和第二寄存器之一接收输出数据，第一寄存器包括第二输入和第二输出，第二输出耦合到计算机可读存储器的第一输入，第二寄存器包括第三输入和第三输出，所述第三输入耦合到所述计算机可读存储器的所述第一输出; 在第一多路复用器的第一输入处的写操作期间接收数据，第一多路复用器包括耦合到第一寄存器的第二输入的第四输出; 以及在所述第一多路复用器的第二输入处的测试模式写入操作期间接收数据，其中所述第一多路复用器的第三输入耦合到所述计算机可读存储器的第一输出。

9. 发明公开

EP2179420A1 MEMORY DEVICE WITH REDUCED BUFFER CURRENT DURING POWER-DOWN MODE 审中-公开
标题翻译：与系统报表模式BUFFER减量当前的存储设备
公开(公告)号：EP2179420A1
公开(公告)日：2010-04-28
申请号：EP07840901.8
申请日：2007-08-13
申请人： Agere Systems, Inc.
发明人： DUDECK, Dennis, E. , EVANS, Donald, Albert , PHAM, Hai, Quang , WERNER, Wayne, E. , WOZNIAK, Ronald, James
IPC分类号： G11C29/12 , G11C7/10 , G11C8/06
CPC分类号： G11C29/12 , G11C7/1078 , G11C7/1084 , G11C8/06 , G11C29/1201 , G11C2207/2227
摘要： A memory device comprises a memory array, at least one buffer coupled to the memory array, and test circuitry coupled to the buffer. The buffer comprises switching circuitry configured to multiplex first and second inputs of the buffer to a given output of the buffer based at least in part on a control signal generated by the test circuitry. The control signal is generated as a function of both a test signal indicative of a test mode of operation of the memory device and a power-down signal indicative of a power-down mode of operation of the memory device. The buffer further comprises current reduction circuitry responsive to the control signal for reducing an amount of current consumed by the buffer in the power-down mode of operation. The buffer may comprise an input data buffer or an address buffer of the memory device.

10. 发明授权

EP1783779B1 Integrierte Schaltung mit integrierter Testhilfe-Teilschaltung 有权
标题翻译：具有集成的调试子电路的集成电路
公开(公告)号：EP1783779B1
公开(公告)日：2008-07-02
申请号：EP06022111.6
申请日：2006-10-21
申请人： ATMEL Germany GmbH
发明人： Hauser, Clemens
IPC分类号： G11C29/46 , G11C29/48 , G11C29/24 , G11C29/44
CPC分类号： G11C29/48 , G01R31/31701 , G11C29/1201

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式