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1. 发明授权

EP1315176B1 Memory circuit having parity cell array 有权
标题翻译：具有奇偶校验单元阵列存储器电路
公开(公告)号：EP1315176B1
公开(公告)日：2009-10-21
申请号：EP02257328.1
申请日：2002-10-22
申请人： Fujitsu Microelectronics Limited
发明人： Fujioka, Shinya , Fujieda, Waichiro , Hara, Kota , Koga, Toru , Mori, Katsuhiro
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G06F11/106 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C2211/4062

2. 发明公开

EP2083423A1 Semiconductor memory device, and method of controlling the same 审中-公开
标题翻译： Halbleiterspeichervorrichtung und Steuerverfahrendafür
公开(公告)号：EP2083423A1
公开(公告)日：2009-07-29
申请号：EP09156492.2
申请日：2000-09-27
申请人： Fujitsu Microelectronics Limited
发明人： Fujioka, Shinya , Kawakubo, Tomohiro , Nishimura, Koichi , Sato, Kotoku
IPC分类号： G11C11/406
CPC分类号： G11C5/14 , G11C5/147 , G11C11/406 , G11C2207/2227
摘要： A semiconductor memory device comprises an internal voltage generator (18) which, when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator (18) consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit (14) inactivates the internal voltage generator (18). When the internal voltage generator (18) is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. During the low power consumption mode, an external voltage supplying circuit supplies a power supply voltage supplied from the exterior as the internal voltage to a predetermined internal circuit. Even when the internal voltage generator (18) is inactivated, therefore, the power supply voltage is supplied to the power supply terminal of each internal circuit, which results in preventing a leak path.
During low power consumption mode, refresh of the dynamic memory cells is prohibited.
摘要翻译：半导体存储器件包括内部电压发生器（18），其在被激活时产生将被提供给内部电路的内部电压。操作内部电压发生器（18）消耗预定量的功率。响应于来自外部的控制信号，入口电路（14）使内部电压发生器（18）失活。当内部电压发生器（18）失活时，不产生内部电压，从而降低功耗。因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。在低功耗模式期间，外部电压供给电路将从外部供给的电源电压作为内部电压供给到规定的内部电路。因此，即使当内部电压发生器（18）失活时，电源电压被提供给每个内部电路的电源端子，这导致防止泄漏路径。在低功耗模式下，禁止刷新动态存储单元。

3. 发明公开

EP2058818A1 Semiconductor memory device and memory system 有权
标题翻译：半导体存储器件和存储器系统
公开(公告)号：EP2058818A1
公开(公告)日：2009-05-13
申请号：EP09152786.1
申请日：2004-12-30
申请人： Fujitsu Microelectronics Limited
发明人： Fujioka, Shinya , Sato, Kotoku
IPC分类号： G11C11/406 , G11C7/22 , G11C7/10
CPC分类号： G11C11/406 , G11C7/1039 , G11C11/40603 , G11C11/40615
摘要： A semiconductor memory device, comprising a memory cell array with a plurality of memory cells storing data disposed therein; a processing circuit decoding command information relating to an external access request to said memory cell array supplied from an outside and address information, and instructing an operation to be executed in said memory cell array based on a decoded result; and an array control circuit executing an operation for said memory cell array based on an instruction from said processing circuit; wherein when the command information relating to the external access request and the address information are in predetermined combination, said processing circuit instructs to execute a refresh operation to hold data stored in the memory cells in said memory cell array.
摘要翻译：一种半导体存储器件，包括：存储器单元阵列，具有存储其中设置的数据的多个存储器单元; 处理电路，用于解码与从外部提供给所述存储单元阵列的外部访问请求有关的命令信息和地址信息，并且基于解码结果指示在所述存储单元阵列中执行的操作; 以及阵列控制电路，根据来自所述处理电路的指示，对所述存储单元阵列进行工作; 其中，当涉及外部访问请求的命令信息和地址信息处于预定组合时，所述处理电路指示执行刷新操作以保存存储在所述存储器单元阵列中的存储器单元中的数据。

4. 发明公开

EP2083424A1 Semiconductor memory device, and method of controlling the same 审中-公开
标题翻译：半导体存储器件及其控制方法
公开(公告)号：EP2083424A1
公开(公告)日：2009-07-29
申请号：EP09156495.5
申请日：2000-09-27
申请人： Fujitsu Microelectronics Limited
发明人： Fujioka, Shinya , Kawakubo, Tomohiro , Nishimura, Koichi , Sato, Kotoku
IPC分类号： G11C14/00
CPC分类号： G11C5/14 , G11C5/147 , G11C11/406 , G11C2207/2227
摘要： A semiconductor memory device comprises an internal voltage generator (18) which, when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator (18) consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit (14) inactivates the internal voltage generator (18). When the internal voltage generator (18) is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. During the low power consumption mode, an external voltage supplying circuit supplies a power supply voltage supplied from the exterior as the internal voltage to a predetermined internal circuit. Even when the internal voltage generator (18) is inactivated, therefore, the power supply voltage is supplied to the power supply terminal of each internal circuit, which results in preventing a leak path.
For low power mode, data are saved from a dynamic memory to a flash memory. During low power mode, refresh operation of the dynamic memory is prohibited.
摘要翻译：一种半导体存储器件包括内部电压发生器（18），该内部电压发生器在被激活时产生要提供给内部电路的内部电压。操作内部电压发生器（18）消耗预定量的功率。响应于来自外部的控制信号，入口电路（14）使内部电压发生器（18）不起作用。当内部电压发生器（18）未激活时，不会产生内部电压，从而降低功耗。因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。在低功耗模式期间，外部电压提供电路将从外部提供的电源电压作为内部电压提供给预定的内部电路。因此，即使当内部电压发生器（18）未被激活时，电源电压也被提供给每个内部电路的电源端子，这导致防止泄漏路径。对于低功耗模式，数据从动态存储器保存到闪存。在低功耗模式下，动态存储器的刷新操作被禁止。

5. 发明授权

EP1100089B1 Semiconductor memory device, and method of controlling the same 有权
标题翻译：一种半导体存储器件及其控制方法
公开(公告)号：EP1100089B1
公开(公告)日：2009-05-27
申请号：EP00308482.9
申请日：2000-09-27
申请人： Fujitsu Microelectronics Limited
发明人： Fujioka, Shinya , Kawakubo, Tomohiro , Nishimura, Koichi , Sato, Kotoku
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C5/147 , G11C11/406 , G11C2207/2227

6. 发明授权

EP1746606B1 Memory circuit having parity cell array 有权
标题翻译：具有奇偶校验单元阵列存储器电路
公开(公告)号：EP1746606B1
公开(公告)日：2010-03-31
申请号：EP06021810.4
申请日：2002-10-22
申请人： Fujitsu Microelectronics Limited
发明人： Fujioka, Shinya , Fujieda, Waichiro , Hara, Kota , Koga, Toru , Mori, Katsuhiro
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G06F11/106 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C2211/4062

7. 发明公开

EP2058819A1 Semiconductor memory device and memory system 审中-公开
标题翻译： Halbleiterspeichervorrichtung und Speichersystem
公开(公告)号：EP2058819A1
公开(公告)日：2009-05-13
申请号：EP09152787.9
申请日：2004-12-30
申请人： Fujitsu Microelectronics Limited
发明人： Fujioka, Shinya , Sato, Kotoku
IPC分类号： G11C11/406 , G11C7/22 , G11C7/10
CPC分类号： G11C11/406 , G11C7/1039 , G11C11/40603 , G11C11/40615
摘要： The semiconductor memory device of the present invention has a memory cell array with a plurality of memory cells disposed therein, a refresh request circuit outputting to an outside a refresh request signal requesting a refresh operation, a processing circuit decoding information relating to an external access request to the memory cell array, and instructing an operation to be executed in the memory cell array based on a decoded result, and an array control circuit executing an operation for the memory cell array based on an instruction from the processing circuit. The external access request includes a refresh execution request being a response to the refresh request signal.
摘要翻译：本发明的半导体存储器具具有设置在其中的多个存储单元的存储单元阵列，向外部向外部输出请求刷新动作的刷新请求信号的刷新请求电路，对外部访问请求进行解码的处理电路并且基于解码结果指示在存储单元阵列中执行的操作，以及基于来自处理电路的指令对存储单元阵列执行操作的阵列控制电路。外部访问请求包括作为对刷新请求信号的响应的刷新执行请求。

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