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1. 发明授权

EP4026127B1 METHOD OF IMPROVING READ CURRENT STABILITY IN ANALOG NON-VOLATILE MEMORY USING FINAL BAKE IN PREDETERMINED PROGRAM STATE 有权
公开(公告)号：EP4026127B1
公开(公告)日：2024-01-24
申请号：EP20718021.7
申请日：2020-03-11
发明人： MARKOV, Viktor , KOTOV, Alexander
IPC分类号： G11C29/06 , G11C29/44 , G11C29/50 , G11C16/34 , G06F12/02 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/26 , G11C29/00 , G11C29/04 , G11C29/24 , G11C29/56 , H01L29/423

2. 发明公开

EP4297035A1 METHOD FOR DETERMINING SWITCHING OF NANOMAGNETS 审中-公开
公开(公告)号：EP4297035A1
公开(公告)日：2023-12-27
申请号：EP22179955.4
申请日：2022-06-20
申请人： Qnami AG
发明人： Rickhaus, Peter
IPC分类号： G11C29/00 , G01R33/12
摘要： The invention concerns a method for characterizing a magnetic device including a plurality of binary nanomagnets, which may be arranged in an array, comprising (i) applying a saturation magnetic field (µ 0 H sat ) having a first direction to a plurality of binary nanomagnets to induce a first magnetic orientation in the plurality of nanomagnets, (ii) applying a second magnetic field (µ 0 H c ) having a second direction, which is different to the first direction, to the plurality of nanomagnets, repeating steps (i) to (ii), determining a first fraction or percentage (α) of nanomagnets which switched orientation in step (ii) and a second fraction or percentage (α 1 ) of nanomagnets which switched orientation in the repeated step (ii), determining a statistical double-switching percentage β ideal based on the determined first fraction or percentage α and the determined second fraction or percentage α 1 of nanomagnets which switched orientation, and determining the effective double-switching fraction or percentage (β) of individual nanomagnets which have switched orientation in step (ii) as well as in the repeated step (ii), wherein a statement about the quality of the plurality of nanomagnets is made based on the comparison between the determined statistical double-switching percentage (β ideal ) and the determined effective double-switching percentage (β) of the plurality of nanomagnets.

3. 发明公开

EP4275207A1 LOGICAL MEMORY REPAIR WITH A SHARED PHYSICAL MEMORY 审中-公开
公开(公告)号：EP4275207A1
公开(公告)日：2023-11-15
申请号：EP21824721.1
申请日：2021-11-17
申请人： Google LLC
发明人： PRADEEP, Wilson , KARKARE, Nikhil
IPC分类号： G11C29/00 , G11C29/18 , G11C29/44

4. 发明授权

EP3933840B1 PROGRAMMABLE STORAGE UNIT AND PROGRAMMABLE MEMORY ARRAY AND READING AND WRITING METHOD THEREFOR 有权
公开(公告)号：EP3933840B1
公开(公告)日：2023-05-31
申请号：EP20893598.1
申请日：2020-07-23
发明人： LI, Xin , YING, Zhan
IPC分类号： G11C17/16 , G11C17/18 , G11C29/00

5. 发明公开

EP4181142A1 NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF 审中-公开
公开(公告)号：EP4181142A1
公开(公告)日：2023-05-17
申请号：EP22207155.7
申请日：2022-11-14
申请人： Samsung Electronics Co., Ltd.
发明人： SHIM, Dongkyo , PARK, Sang Soo
IPC分类号： G11C29/00 , G11C29/44 , G11C7/10 , G11C16/04
摘要： Disclosed is a nonvolatile memory device which includes a first plane that includes a plurality of memory blocks, a second plane that includes a plurality of memory blocks, an address replacing circuit that receives a first input address from an external controller, the first input address corresponding to a first memory block of the plurality of memory blocks of the first plane from an external controller and outputs a replaced address based on the first input address and bad block information, and an address decoder that controls word lines connected with a second memory block based on the replaced address, the word lines corresponding to the replaced address from among the plurality of memory blocks of the second plane. The first memory block of the first plane is a bad block.

6. 发明授权

EP3660615B8 SYSTEM AND METHOD FOR MONITORING AN ON-BOARD RECORDING SYSTEM 有权转让
公开(公告)号：EP3660615B8
公开(公告)日：2023-04-19
申请号：EP19211955.0
申请日：2019-11-27
发明人： GILBERTSON, Daniel David , MUTSCHLER, Christopher M.
IPC分类号： G05B23/02 , G07C5/08 , G11C29/00

7. 发明公开

EP4162490A1 MEMORY DEVICE WITH BUILT-IN FLEXIBLE DOUBLE REDUNDANCY 审中-公开
公开(公告)号：EP4162490A1
公开(公告)日：2023-04-12
申请号：EP21727667.4
申请日：2021-04-30
申请人： QUALCOMM INCORPORATED
发明人： KOTA, Anil Chowdary , LEE, Hochul
IPC分类号： G11C7/14 , G11C7/06 , G11C7/24 , G11C29/00 , G11C17/16

8. 发明公开

EP4148736A1 SEMICONDUCTOR MEMORY AND CAPACITY CONFIGURATION METHOD FOR STORAGE BLOCK THEREON 审中-公开
公开(公告)号：EP4148736A1
公开(公告)日：2023-03-15
申请号：EP21927042.8
申请日：2021-11-02
申请人： Changxin Memory Technologies, Inc.
发明人： CHEN, Jixing , SHANG, Weibing
IPC分类号： G11C29/00 , G11C11/34
摘要： The embodiments of the present disclosure provide a semiconductor memory and a method for density configuration of a bank of the semiconductor memory. The method includes: determining a target bank to be configured of the memory; determining a density configuration parameter of the target bank, and determining a target code from a set of codes of the target bank, the target code corresponding to a storage region to be trimmed in the target bank; generating, based on the target code, a region selection signal configured to select the storage region to be trimmed in the target bank; and trimming the storage region to be trimmed based on the region selection signal to configure a density of the target bank. In this way, the storage region to be trimmed is flexibly selected and the effective utilization rate of the density configuration of the banks of the semiconductor memory is improved.

9. 发明授权

EP3660615B1 SYSTEM AND METHOD FOR MONITORING AN ON-BOARD RECORDING SYSTEM 有权转让
公开(公告)号：EP3660615B1
公开(公告)日：2023-03-15
申请号：EP19211955.0
申请日：2019-11-27
发明人： GILBERTSON, Daniel David , MUTSCHLER, Christopher M.
IPC分类号： G05B23/02 , G07C5/08 , G11C29/00

10. 发明公开

EP4053841A1 MEMORY SYSTEM WITH REDUNDANT OPERATION 审中-公开
公开(公告)号：EP4053841A1
公开(公告)日：2022-09-07
申请号：EP22157358.7
申请日：2022-02-17
申请人： NXP USA, Inc.
发明人： Zeli, Rodrigo Pascoal , Qureshi, Qadeer , Spruth, Henning Fritz , Silveira, Reinaldo
IPC分类号： G11C29/00 , G11C29/12 , G11C29/18 , G11C29/44 , G11C29/48 , G11C29/10 , G11C29/36 , G11C29/50
摘要： A memory system includes a memory that provides digital data and a built-in self-test (BIST) circuit for testing the memory for determining defective storage units of the memory. The memory system has a data output for providing data from the memory to an external system. The data output of the memory system has a first bit width. The memory has a data output that has a second bit width that is greater than the first bit width. The BIST circuit has a data input that is of the second bit width.

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