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1. 发明公开

EP2936326A4 METHOD, APPARATUS AND SYSTEM FOR EXCHANGING COMMUNICATIONS VIA A COMMAND/ADDRESS BUS 有权
标题翻译： VERFAHREN，VORRICHTUNG UND系统ZUR KOMMUNIKATIONÜBEREINEN BEFEHLS- / ADRESSENBUS
公开(公告)号：EP2936326A4
公开(公告)日：2016-11-09
申请号：EP13865408
申请日：2013-06-12
申请人： INTEL CORP
发明人： BAINS KULJIT S , MCCALL JAMES A
IPC分类号： G11C7/10 , G06F12/00 , G06F13/14 , G06F13/16 , G06F13/42 , G11C7/22 , G11C11/4072 , G11C11/4076 , G11C11/4093
CPC分类号： G06F12/00 , G06F13/4243 , G11C7/1045 , G11C7/1072 , G11C7/109 , G11C7/22 , G11C11/4072 , G11C11/4076 , G11C11/4093
摘要： Techniques and mechanisms for exchanging information from a memory controller to a memory device via a command/address bus. In an embodiment, the memory device samples a first portion of a command during a first sample period and samples a second portion of the command during a second sample period, the first portion and second portion exchanged via the command/address bus. The first sample period and the second sample period are concurrent with, respectively, a first transition of a clock signal and a second transition of the clock signal. In another embodiment, a mode of the memory device determines a relationship between the first transition and the second transition.
摘要翻译：通过命令/地址总线将信息从存储器控制器交换到存储器件的技术和机制。在一个实施例中，存储器件在第一采样周期期间对命令的第一部分进行采样，并且在第二采样周期期间对命令的第二部分进行采样，第一部分和第二部分经由命令/地址总线交换。第一采样周期和第二采样周期分别与时钟信号的第一次转换和时钟信号的第二转换同时进行。在另一实施例中，存储器装置的模式确定第一转变和第二转换之间的关系。

2. 发明公开

EP2993587A1 BACKUP SYSTEM FOR VOLATILE MEMORY USING ALL-SOLID-STATE BATTERY 有权
标题翻译： DATENSICHERUNGSSYSTEMFÜRFLÜCHTIGESPEICHER MIT FESTSTOFFBATTERIE
公开(公告)号：EP2993587A1
公开(公告)日：2016-03-09
申请号：EP15781842.8
申请日：2015-04-08
申请人： NGK Insulators, Ltd.
发明人： OHWADA, Iwao , KITOH, Kenshin
IPC分类号： G06F12/16 , G11C11/401 , H01M4/131 , H01M10/052 , H01M10/0562 , H01M10/058
CPC分类号： H01M10/0585 , G06F11/1441 , G06F11/2015 , G06F12/16 , G11C5/141 , G11C11/005 , G11C11/401 , G11C11/4072 , G11C14/0018 , H01M4/131 , H01M4/485 , H01M4/505 , H01M4/525 , H01M10/052 , H01M10/0525 , H01M10/0562 , H01M10/0565 , H01M10/058 , H01M2004/028 , H01M2220/30 , H01M2300/0068 , H02J9/061 , Y02E60/122
摘要： The present invention provides a volatile memory backup system including an all-solid-state battery. The backup system includes a volatile memory, a nonvolatile memory connected to the volatile memory so as to transfer data therebetween, an all-solid-state battery connected to the volatile memory and the nonvolatile memory, the battery continuously or intermittently supplying a current to the volatile memory during a power failure to retain data in the volatile memory, and a controller connected in parallel with the battery, the controller intermittently supplying a peak current to the volatile memory during the power failure and intermittently transferring divided volumes of data in the volatile memory to the nonvolatile memory by the peak current and a current from the battery temporarily increased in association with the peak current to store the data in the nonvolatile memory, thereby gradually accumulating the data in the volatile memory into the nonvolatile memory.
摘要翻译：本发明提供一种包括全固态电池的易失性存储器备份系统。备用系统包括易失性存储器，连接到易失性存储器以便在其间传送数据的非易失性存储器，连接到易失性存储器和非易失性存储器的全固态电池，电池连续地或间歇地向电源故障期间的易失性存储器将数据保存在易失性存储器中，以及与电池并联连接的控制器，控制器在电源故障期间间歇地向易失性存储器提供峰值电流，并且在易失性存储器中间歇地传送分割数据量并且来自电池的电流与峰值电流相关联地临时增加，以将数据存储在非易失性存储器中，从而将易失性存储器中的数据逐渐积累到非易失性存储器中。

3. 发明授权

EP1266381B1 METHOD AND APPARATUS FOR AN EASY IDENTIFICATION OF A STATE OF A DRAM GENERATOR CONTROLLER 有权
标题翻译：方法和系统发电机控制模块中的动态半导体存储器结构状态的一个简单的识别
公开(公告)号：EP1266381B1
公开(公告)日：2012-01-18
申请号：EP01920340.5
申请日：2001-03-13
申请人： Qimonda AG
发明人： WEINFURTNER, Oliver
IPC分类号： G11C11/4074 , G11C5/14 , G11C11/4072 , G11C7/20
CPC分类号： G11C5/14 , G11C5/147 , G11C7/20 , G11C11/4072 , G11C11/4074
摘要： In a controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of N states. A state storage device is responsive to input signals from a transition arrangement including a 1-out-of-N code indicating a change in the state diagram from a current state to a next state of the plurality of N states. The state storage device generates a revised plurality of N state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of N states. The state storage device is also responsive to an asynchronous Reset signal received from an external source for generating a Reset and a complementary Set output signal. A state identification circuitry is responsive to a selectively applied activation signal for inhibiting the output of the revised plurality of N state signals from the state storage device and sequentially reading out the plurality of N state signals currently stored in the state storage device. The the 1-out-of N code forming the plurality of N state signals are used to determine which state of the state diagram the controller is presently in when the controller fails to complete a procedure in the state diagram.

4. 发明公开

EP2239849A2 Apparatus and method for compensating for process, voltage, and temperature variation of the time delay of a digital delay line 失效转让
标题翻译：装置和方法，用于补偿数字延迟线的时间延迟的过程，电压和温度的变化
公开(公告)号：EP2239849A2
公开(公告)日：2010-10-13
申请号：EP10152009.6
申请日：2010-01-28
申请人： Honeywell International Inc.
发明人： Seefeldt, James , Feng, Xiaoxin , Roper, Weston
IPC分类号： H03K5/13
CPC分类号： G11C29/022 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4072 , G11C11/4093 , G11C29/023 , G11C29/028 , H03K5/133 , H03K2005/00097 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs arc provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.
摘要翻译：本发明提供一种工艺，电压和温度（PVT）补偿电路和连续地产生一延迟测量结果的方法。所述补偿电路包括两个延迟线，每个延迟线提供延迟输出。两条延迟线可各自包括多个延迟元件，其又可以包括一个或多个电流限制式反相器。的延迟线的数量可以在两个延迟线之间进行区分。提供给组合电路的延迟输出的电弧那样确定性地雷基于两个延迟输出和然后平均偏置脉冲确定性矿的延迟测量的电压，以抵消脉冲。延迟测量结果可以是一个或更多的电流或电压指示的PVT补偿量施加到应用电路的输入或输出信号，检测器在存储总线驱动器，动态随机存取存储器（DRAM），同步DRAM，一个处理器或其它时钟电路。

5. 发明授权

EP1530219B1 Semiconductor memory with synchronous and asynchronous mode selection during power-down 有权
标题翻译：半导体存储器用在关机期间同步/异步模式选择
公开(公告)号：EP1530219B1
公开(公告)日：2008-06-18
申请号：EP04014667.2
申请日：2004-06-23
申请人： FUJITSU LIMITED
发明人： Koga, Toru, c/o Fujitsu Limited , Kawakubo, Tomohiro, c/o Fujitsu Limited , Kanda, Tatsuya, c/o Fujitsu Limited
IPC分类号： G11C11/22 , G11C7/10 , G11C11/4072
CPC分类号： G11C7/22 , G11C5/14 , G11C7/1072 , G11C11/4072 , G11C2207/2227

6. 发明公开

EP1705663A3 Semiconductor memory and system apparatus 有权
标题翻译：半导体存储器设备和系统
公开(公告)号：EP1705663A3
公开(公告)日：2007-03-07
申请号：EP05013395.8
申请日：2005-06-22
申请人： FUJITSU LIMITED
发明人： Nishimura, Koichi, c/o Fujitsu Ltd. , Yamada, Shinichi, c/o Fujitsu Ltd. , Nomura, Yukihiro, c/o Fujitsu Ltd.
IPC分类号： G11C7/10
CPC分类号： G11C7/1045 , G11C11/4072 , G11C2029/0407
摘要： A register part of a mode register has a plurality of operation setting parts in which plural types of operating specifications are respectively set to operate the semiconductor memory. The mode register outputs a soft reset signal when at least a value of one-bit of the register part represents a reset state. A reset signal generator outputs a reset signal for resetting an internal circuit in response to the soft reset signal. In the present invention, a system that controls the semiconductor memory is required to necessarily assign a predetermined bit with a setting command of the mode register in order to generate the soft reset signal. Accordingly, it is possible to reliably reset the internal circuit by external control.

7. 发明公开

EP1624558A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：整合HALBLEITERBAUELEMENT
公开(公告)号：EP1624558A1
公开(公告)日：2006-02-08
申请号：EP03728065.8
申请日：2003-05-13
申请人： FUJITSU LIMITED
发明人： YAMAZAKI, Masafumi; C/O FUJITSU LIMITED , UCHIDA, Toshiya; C/O FUJITSU LIMITED
IPC分类号： H02M3/07
CPC分类号： G11C11/4074 , G11C5/14 , G11C5/145 , G11C8/08 , G11C11/4072 , G11C11/4085 , H02M3/07 , H02M2001/009
摘要： A semiconductor integrated circuit device has a boosted-voltage power-supply circuit generating a boosted voltage, an internal circuit being driven with the boosted voltage, and a control circuit controlling the internal circuit by receiving the boosted voltage. The boosted-voltage power-supply circuit has a first output terminal for the internal circuit, and a second output terminal for the control circuit. The boosted voltage output from the second terminal has a specified level regardless of variation in the boosted voltage being output from the first terminal.
摘要翻译：半导体集成电路装置具有产生升压电压的升压电源电路，利用升压电压驱动的内部电路，以及通过接收升压电压来控制内部电路的控制电路。升压电源电路具有用于内部电路的第一输出端子和用于控制电路的第二输出端子。不管从第一端子输出的升压电压的变化如何，来自第二端子的升压电压都具有指定电平。

8. 发明公开

EP1610342A1 Integrated circuit device with automatic internal command function 有权
标题翻译： Schaltungeinheit mit automatischer interner Befehlsfunktion
公开(公告)号：EP1610342A1
公开(公告)日：2005-12-28
申请号：EP05018384.7
申请日：2001-04-30
申请人： FUJITSU LIMITED
发明人： Matsuzaki, Yasurou
IPC分类号： G11C11/406 , G11C11/4072
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4072 , G11C11/4094 , G11C2211/4061 , G11C2211/4065
摘要： A memory circuit requiring refresh operations, comprising: a first circuit which receives a command (CMD) in synchronization with a clock signal (CK1), and which generates a first internal command (RD, WR) internally and a second circuit which generates a second internal command, e.g. a refresh command (REF), internally in a prescribed refresh cycle. An internal circuit, according to said first internal command (RD, WR), executes corresponding control through clock-synchronous operations, and when said refresh command (REF) is issued, sequentially executes control corresponding to the refresh command (REF) and control corresponding to said first internal command (RD, WR) through clock-asynchronous operations. When a refresh timing signal is generated, the refresh operation can be interrupted among external command operations.
摘要翻译：一种需要刷新操作的存储器电路，包括：第一电路，与时钟信号（CK1）同步地接收命令（CMD），并在内部产生第一内部命令（RD，WR），以及产生第二电路的第二电路内部命令，例如刷新命令（REF），在规定的刷新周期内部。根据所述第一内部命令（RD，WR）的内部电路通过时钟同步操作执行相应的控制，并且当发出所述刷新命令（REF）时，顺序地执行与刷新命令（REF）相对应的控制，并且对应于通过时钟异步操作到第一个内部命令（RD，WR）。当产生刷新定时信号时，可以在外部命令操作之间中断刷新操作。

9. 发明授权

EP1150301B1 Memory circuit with automatic refresh function, and integrated circuit device with automatic internal command function 有权
标题翻译：存储具有自动刷新功能和切换单元具有自动内部指令功能
公开(公告)号：EP1150301B1
公开(公告)日：2005-11-02
申请号：EP01303938.3
申请日：2001-04-30
申请人： FUJITSU LIMITED
发明人： Matsuzaki, Yasurou
IPC分类号： G11C11/406 , G11C11/4072
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4072 , G11C11/4094 , G11C2211/4061 , G11C2211/4065

10. 发明授权

EP1374244B1 A METHOD OF SYNCHRONIZING READ TIMING IN A HIGH SPEED MEMORY SYSTEM 有权
标题翻译：过程进行同步高速内存的选择时间
公开(公告)号：EP1374244B1
公开(公告)日：2005-08-31
申请号：EP02718884.6
申请日：2002-02-01
申请人： MICRON TECHNOLOGY, INC.
发明人： JANZEN, Jeffery, W. , MANNING, Troy, A. , MARTIN, Chris, G. , KEETH, Brent
IPC分类号： G11C7/22 , G11C11/409 , G11C7/10 , G11C7/20 , G11C11/4072 , G06F13/42
CPC分类号： G11C7/1066 , G06F13/1689 , G06F13/4243 , G11C7/1006 , G11C7/1072 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/409 , G11C2207/107 , G11C2207/2254 , G11C2207/2281
摘要： The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.

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