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1. 发明公开

EP3417455A1 RECONFIGURABLE CLOCKING ARCHITECTURE 审中-公开
公开(公告)号：EP3417455A1
公开(公告)日：2018-12-26
申请号：EP17753613.3
申请日：2017-01-17
申请人： Intel Corporation
发明人： MANSURI, Mozhgan , MARTIN, Aaron , MCCALL, James A.
IPC分类号： G11C11/4076 , G11C7/22 , H03K3/03 , G05F1/575
CPC分类号： G11C11/4076 , G06F1/10 , G06F13/4234 , G11C7/10 , G11C7/1087 , G11C7/222 , G11C11/4093 , H03K5/14 , H03K2005/00052 , H04L7/0337
摘要： Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.

2. 发明公开

EP3311386A1 DIGITAL PHASE CONTROL WITH PROGRAMMABLE TRACKING SLOPE 审中-公开
标题翻译：具有可编程跟踪斜率的数字相位控制
公开(公告)号：EP3311386A1
公开(公告)日：2018-04-25
申请号：EP16812131.7
申请日：2016-05-27
申请人： Intel Corporation
发明人： WEI, Fangxing , SHAH, Setul M. , ALLEN, Michael J. , CHANDAN, Khushal N.
IPC分类号： G11C7/22 , H03L7/081 , H03K5/13
CPC分类号： H03L7/0814 , G11C7/10 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/0818
摘要： Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for better tracking of environmental conditions. The phase compensation circuit can generate a linear code to apply phase compensation to lock phase of an I/O signal to a phase of a timing signal. The circuit selectively adjusts the linear code with a variable, programmable slope, where the slope defines how much phase compensation is applied per unit change in the linear code. The circuit applies the adjusted linear code to a lock loop to lock the phase of the I/O signal to the phase of the timing signal.

3. 发明授权

EP2347417B1 PROGRAMMING DATA INTO A MULTI-PLANE FLASH MEMORY 有权
标题翻译：将数据编程到多平面闪存中
公开(公告)号：EP2347417B1
公开(公告)日：2018-04-18
申请号：EP09792140.7
申请日：2009-09-01
申请人： Marvell World Trade Ltd.
发明人： GOTO, Akio , LEE, Chi Kong , URABE, Masayuki
IPC分类号： G11C7/10 , G11C16/10 , G06F13/16
CPC分类号： G11C16/10 , G11C7/10 , G11C2207/2245 , G11C2216/14
摘要： Systems, methods and computer program products for programming data into a multi-plane memory device employ a multi-plane data order. To allow multiple data pages to be programmed without a need to increase the size of page buffers, in some implementations, a data transfer scheme at which the data pages are programmed can be manipulated. Specifically, data across all channels can first be programmed into a first plane of the multi-plane flash memory device in parallel. While the data transfer program operation is in progress, data to be programmed into a succeeding plane (e.g., plane “1”) can be read into and cached in one or more page buffers. After the data transfer program for the first plane is complete, data cached in the page buffers can be immediately latched and programmed into the multi-plane flash memory device.

4. 发明公开

EP3306614A1 MEMORY ARRAY HAVING SEGMENTED ROW ADDRESSED PAGE REGISTERS 审中-公开
标题翻译：内存阵列具有分段行地址寄存器
公开(公告)号：EP3306614A1
公开(公告)日：2018-04-11
申请号：EP17195232.8
申请日：2017-10-06
申请人： Kilopass Technology, Inc.
发明人： Ong, Adrian E. , Bateman, Bruce
IPC分类号： G11C7/10 , G11C16/26 , G11C11/39 , G11C11/418 , G11C11/419
CPC分类号： G11C11/419 , G11C7/10 , G11C11/39 , G11C11/418 , G11C16/26 , H01L27/1027
摘要： The access speeds of new memory technologies may not be compatible with product specifications of existing memory technologies such as DRAM, SRAM, and FLASH technologies. Their electrical parameters and behaviors are different such that they cannot meet existing memory core specifications without new architectures and designs to overcome their limitations. New memories such as STT-MRAM, Resistive-RAM, Phase-Change RAM, and a new class of memory called Vertical Layer Thysistor (VLT) RAM requires new read sensing and write circuits incorporating new voltage or current levels and timing controls to make these memory technologies work in today's systems. Systems and methods are provided for rendering the memory cores of these technologies transparent to existing peripheral logic so that they can be easily integrated.
摘要翻译：新存储器技术的存取速度可能与现有存储器技术（如DRAM，SRAM和FLASH技术）的产品规格不兼容。它们的电气参数和行为是不同的，因此如果没有新的体系结构和设计来克服它们的限制，它们将无法满足现有的内存核心规格。新型存储器如STT-MRAM，电阻式RAM，相变RAM以及称为垂直层晶体管（VLT）RAM的新型存储器需要新的读出感应和写入电路，以结合新的电压或电流电平以及时序控制，以使这些内存技术在当今的系统中起作用。提供了用于使这些技术的存储器核心对现有的外围逻辑是透明的以使它们可以容易地集成的系统和方法。

5. 发明公开

EP3289590A2 FULLY VALID-GATED READ AND WRITE FOR LOW POWER ARRAY 审中-公开
标题翻译：完全有效的读取和写入低功率阵列
公开(公告)号：EP3289590A2
公开(公告)日：2018-03-07
申请号：EP16716107.4
申请日：2016-03-28
申请人： Qualcomm Incorporated
发明人： HOFF, David Paul , MARTZLOFF, Jason Philip , SWEITZER, Robert Andrew
IPC分类号： G11C7/12 , G11C8/08 , G11C11/419 , G11C7/10
CPC分类号： G11C7/106 , G11C7/10 , G11C7/1009 , G11C7/1066 , G11C7/1087 , G11C7/109 , G11C7/1093 , G11C7/12 , G11C7/22 , G11C8/08 , G11C11/419
摘要： In an array that qualifies each row according to a valid/invalid state, each row may each include valid-gated read circuitry to conditionally block a read wordline from toggling unless the row stores a data word that has a valid state or a read force signal is asserted. Furthermore, in a write operation, each row may have valid-gated write circuitry that conditionally blocks a write wordline from toggling unless input data to be written to the row has a valid state or a write force signal is asserted. Moreover, output latch clocking may be blocked from toggling unless a row to be read stores a data word that has a valid state or the read force signal is asserted, and input latch clocking may also be blocked unless the input data to be written has a valid state or the write force signal is asserted.

6. 发明授权

EP2898334B1 METHOD, SYSTEM AND APPARATUS FOR EVALUATION OF INPUT/OUTPUT BUFFER CIRCUITRY 有权
标题翻译：用于评估输入/输出缓冲器电路的方法，系统和装置
公开(公告)号：EP2898334B1
公开(公告)日：2018-03-07
申请号：EP13838100.9
申请日：2013-06-14
申请人： Intel Corporation
发明人： NELSON, Christopher J. , MAK, Tak M. , ZIMMERMAN, David J. , VOGT, Pete D.
IPC分类号： G01R29/02 , G01R31/317 , G11C7/10 , G01R31/3181 , G01R31/3187 , G01R31/3177 , G06F11/34 , G11C29/02 , G11C29/12 , G11C29/32 , H04L1/24
CPC分类号： G01R31/31716 , G01R31/31713 , G01R31/3177 , G01R31/3181 , G01R31/3187 , G06F11/3485 , G11C7/10 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C29/32 , H04L1/243
摘要： Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.

7. 发明公开

EP3284089A1 LOW POWER AND HIGH SPEED SENSE AMPLIFIER LATCH WITH LOW POWER RAIL-TO-RAIL INPUT COMMON MODE RANGE 审中-公开
标题翻译：低功率和高速感应放大器与低功率轨到轨输入通用模式范围锁定
公开(公告)号：EP3284089A1
公开(公告)日：2018-02-21
申请号：EP16780406.1
申请日：2016-02-10
申请人： INTEL Corporation
发明人： DUDULWAR, Pankaj Vinayak , BANDI, Chenchu Punnarao , TEH, Lip Khoon , TAN, Tat Hin
IPC分类号： G11C7/06 , G11C5/14
CPC分类号： H04L7/0037 , G11C7/062 , G11C7/065 , G11C7/08 , G11C7/10 , G11C7/1057 , G11C7/106 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C11/165 , G11C11/4093 , G11C11/4096 , H03L7/0812 , H04L27/0002
摘要： Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.

8. 发明公开

EP3254286A1 APPARATUSES AND METHODS FOR PARALLEL WRITING TO MULTIPLE MEMORY DEVICE LOCATIONS 审中-公开
标题翻译：用于并行写入多个存储器设备位置的装置和方法
公开(公告)号：EP3254286A1
公开(公告)日：2017-12-13
申请号：EP16746987.3
申请日：2016-01-27
申请人： Micron Technology, Inc.
发明人： ZAWODNY, Jason T. , HUSH, Glen E. , MANNING, Troy A. , FINKBEINER, Timothy P.
IPC分类号： G11C7/06 , G11C7/10 , G11C8/12
CPC分类号： G06F3/0611 , G06F3/0625 , G06F3/0659 , G06F3/0683 , G06F15/7821 , G11C5/025 , G11C7/10 , G11C7/1006 , G11C8/12 , G11C29/28 , G11C2029/2602
摘要： The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

9. 发明公开

EP3238079A1 PACKED WRITE COMPLETIONS 有权
标题翻译：包装写完成
公开(公告)号：EP3238079A1
公开(公告)日：2017-11-01
申请号：EP15874051.4
申请日：2015-11-27
申请人： Intel Corporation
发明人： MORRIS, Brian S. , SWANSON, Jeffrey C. , NALE, Bill , BLANKENSHIP, Robert G. , WILLEY, Jeff , HENDRICKSON, Eric L.
IPC分类号： G06F13/16 , G06F12/08
CPC分类号： G06F13/1663 , G06F13/1673 , G11C5/04 , G11C7/10
摘要： A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory interface. A completion packet is sent to the host device that includes a plurality of write completions to correspond to the plurality of completed writes.
摘要翻译：识别对应于来自通过缓冲存储器接口接收的来自主机设备的多个写入请求的对存储器的多个完成的写入。完成包被发送到包括多个写入完成的主机设备以对应于多个完成的写入。

10. 发明公开

EP3234784A1 DYNAMIC RANDOM ACCESS MEMORY (DRAM) COMPONENT FOR HIGH-PERFORMANCE,HIGH-CAPACITY REGISTERED MEMORY MODULES 有权转让
标题翻译：动态随机存取存储器（DRAM）组件，用于高性能，高容量注册存储模块
公开(公告)号：EP3234784A1
公开(公告)日：2017-10-25
申请号：EP15870528.5
申请日：2015-10-28
申请人： Rambus Inc.
发明人： WARE, Frederick A. , TSERN, Ely , LINSTADT, John Eric , GIOVANNINI, Thomas J. , WRIGHT, Kenneth L.
IPC分类号： G06F13/00
CPC分类号： G06F13/287 , G06F13/16 , G06F2213/28 , G11C5/04 , G11C7/10 , G11C7/1045
摘要： The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.
摘要翻译：这里描述的实施例描述了用于诸如注册的双列直插式存储器模块（RDIMM）的高性能，高容量注册存储器模块的动态随机存取存储器（DRAM）组件的技术。一个DRAM组件可以包括一组存储单元和导向逻辑。转向逻辑可以包括第一数据接口和第二数据接口。第一和第二数据接口在第一模式中选择性地耦合到控制器组件，并且第一数据接口在第二模式中选择性地耦合到控制器组件，并且第二数据接口选择性地耦合到第二模式中的第二DRAM组件。

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