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1. 发明公开

EP3226246A1 METHOD AND SYSTEM FOR PREDICTING HIGH-TEMPERATURE OPERATING LIFE OF SRAM DEVICES 审中-公开
标题翻译：用于预测SRAM器件的高温工作寿命的方法和系统
公开(公告)号：EP3226246A1
公开(公告)日：2017-10-04
申请号：EP17162508.0
申请日：2017-03-23
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： CHIEN, Wei Ting , ZHU, Yue Qin , SONG, Yongliang , ZHAO, Yong
IPC分类号： G11C29/00 , G11C29/06 , G11C29/50 , G11C29/56 , G01R31/26 , G01R31/28 , G11C7/04 , G11C11/412
CPC分类号： G01R31/2875 , G01R31/2628 , G01R31/2642 , G01R31/2851 , G11C11/412 , G11C29/006 , G11C29/06 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C29/56008 , G11C2029/0403 , G11C2029/4002
摘要： A method for predicting high-temperature operating life of an integrated circuit (IC) includes performing bias temperature instability tests and high-temperature operating life tests on a device of the IC, establishing a relationship between the device bias temperature instability and the IC's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests. The method further includes providing a lot of subsequent integrated circuits (ICs), performing wafer-level bias temperature instability tests on a device of the ICs, and predicting high-temperature operating life of the ICs based on a result of the wafer-level bias temperature instability tests and based on the established relationship between the device's bias temperature instability and the IC's high-temperature operating life. The method can save significant effort and time over conventional approaches for accurate prediction of high-temperature operating life of an IC.
摘要翻译：一种用于预测集成电路（IC）的高温工作寿命的方法包括在IC的器件上执行偏置温度不稳定性测试和高温工作寿命测试，建立器件偏置温度不稳定性与IC的高温工作寿命之间的关系，基于偏置温度不稳定性测试和高温工作寿命测试的结果的温度工作寿命。该方法还包括提供大量后续集成电路（IC），在IC的器件上执行晶片级偏置温度不稳定性测试，并且基于晶片级偏置的结果预测IC的高温工作寿命温度不稳定性测试，并基于器件偏置温度不稳定性与IC的高温工作寿命之间建立的关系。与传统方法相比，该方法可以节省大量的精力和时间，以精确预测IC的高温工作寿命。

2. 发明公开

EP1895539A2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：EP1895539A2
公开(公告)日：2008-03-05
申请号：EP07107083.3
申请日：2007-04-27
申请人： FUJITSU LIMITED
发明人： Tomita, Hiroyoshi
IPC分类号： G11C11/404
CPC分类号： G11C11/4074 , G11C11/401 , G11C29/50 , G11C2029/0403 , G11C2207/2254 , H01L27/0207 , H01L27/10829
摘要： The present invention suppresses the refresh failure of a DRAM due to the dispersion of a threshold of a MOSFET. The DRAM has a first unit (5) for recording a set value of a back bias potential to be applied to a back gate of a cell transistor and a second unit (8, 9) for generating a back bias potential (V BB ) based on the set value of the back bias potential recorded in the first unit and supplying the generated back bias potential to the back gate, wherein when a threshold of a MOSFET which has a structure identical to the cell transistor and which has been fabricated in the same process as the cell transistor is greater than a target value which the cell transistor should have, a value shallower than the back bias potential for the target value is recorded in the second unit.
摘要翻译：本发明抑制了由于MOSFET的阈值的分散导致的DRAM的刷新失败。 DRAM具有用于记录要施加到单元晶体管的背栅极的反向偏置电位的设定值的第一单元（5）和用于基于反向偏置电位（VBB）产生反偏置电位（VBB）的第二单元（8,9）在所述第一单元中记录的所述反偏置电位的设定值，并将所生成的反偏置电位提供给所述背栅，其中，当具有与所述单元晶体管相同的结构且已经在相同工艺中制造的MOSFET的阈值由于单元晶体管大于单元晶体管应具有的目标值，所以在第二单元中记录比目标值的反向偏置电位浅的值。

3. 发明公开

EP1891661A1 TEST CELLS FOR SEMICONDUCTOR YIELD IMPROVEMENT 审中-公开
标题翻译：测试单元，以提高半导体产量
公开(公告)号：EP1891661A1
公开(公告)日：2008-02-27
申请号：EP05761872.0
申请日：2005-06-16
申请人： PDF Solutions, Inc.
发明人： STINE, Brian , KITCH, Victor , ZWALD, Mark , TONELLO, Stefano
IPC分类号： H01L21/00 , H01L21/66 , H01L23/58 , G11C29/00
CPC分类号： G11C29/025 , G01R31/2884 , G11C17/14 , G11C29/006 , G11C29/24 , G11C2029/0403 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A test cell (100) for localizing defects includes a first active region (110), a second active region (120) formed substantially parallel to the first active region, a third active region (130) formed substantially parallel to the first and second active regions, a fourth active region (115) formed between the first and second active regions, and a fifth active region (125) formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.

4. 发明公开

EP1170147A1 INFORMATION RECORDING MEDIUM AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： HERSTELLUNGSVERFAHREN公司的信息管理
公开(公告)号：EP1170147A1
公开(公告)日：2002-01-09
申请号：EP00908019.3
申请日：2000-03-10
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： YAMADA, Noboru , KOJIMA, Rie , MATSUNAGA, Toshiyuki , KAWAHARA, Katsumi
IPC分类号： B41M5/26 , G11B7/24 , G11B7/26 , G11B9/04
CPC分类号： G11B13/00 , G03G5/02 , G11B7/243 , G11B7/2433 , G11B7/2585 , G11B7/26 , G11B7/266 , G11B9/00 , G11B9/04 , G11B9/08 , G11B11/00 , G11B11/08 , G11B11/12 , G11B2007/24306 , G11B2007/24308 , G11B2007/2431 , G11B2007/24312 , G11B2007/24314 , G11B2007/24316 , G11B2007/24322 , G11B2007/2571 , G11B2007/25713 , G11C13/0004 , G11C13/04 , G11C2029/0403 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683 , Y10T428/21
摘要： An information recording medium having such a recording material layer on a substrate where reversible phase change between electrically or optically detectable states can be caused by electric energy or electromagnetic energy. The recording material forming the recording layer is either a material having a crystal structure including lattice defects in one phase of the reversible phase change or a material having a complex phase composed of a crystal portion including a lattice defect in one phase of the reversible phase change and an amorphous portion. Both portions contain a common element. A part of the lattice defects are filled with an element other than the element constituting the crystal structure. The recording medium having a recording thin film exhibits little variation of the recording and reproduction characteristics even after repetition of recording and reproduction, excellent weatherability, strong resistance against composition variation, and easily controllable characteristics.
摘要翻译：在基板上具有这样的记录材料层的信息记录介质，其可以由电能或电磁能引起电或光可检测状态之间的可逆相位变化。形成记录层的记录材料是具有在可逆相变的一相中包括晶格缺陷的晶体结构的材料或具有由可逆相变的一相中包括晶格缺陷的晶体部分组成的复相的材料和无定形部分。两部分都包含一个共同的元素。晶格缺陷的一部分用构成晶体结构的元素以外的元素填充。具有记录薄膜的记录介质即使在重复记录和再现之后也显示出很小的记录和再现特性的变化，优异的耐候性，对组合变化的强抗性以及容易控制的特性。

5. 发明公开

EP0993033A1 Gate insulating structure for power devices, and related manufacturing process 审中-公开
标题翻译： Gate-Isolierungsstrukturfüreinen Leistungstransistor und Herstellungsverfahrendafür
公开(公告)号：EP0993033A1
公开(公告)日：2000-04-12
申请号：EP98830585.0
申请日：1998-10-06
申请人： STMicroelectronics S.r.l.
发明人： Frisina, Ferruccio , Ferla, Giuseppe
IPC分类号： H01L21/336 , H01L29/78 , H01L29/423
CPC分类号： H01L29/7802 , G11C29/14 , G11C29/50 , G11C2029/0403 , H01L21/76202 , H01L21/8238 , H01L29/6656 , H01L29/66712
摘要： Semiconductor power device comprising a semiconductor layer (1) of a first type of conductivity, wherein a body region (2) of a second type of conductivity comprising source regions (3) of the first type of conductivity is formed, a gate oxide layer (4) superimposed to the semiconductor layer (1) with an opening over the body region (2), polysilicon regions (5) superimposed to the gate oxide layer (4), and regions of a first insulating material (6) superimposed to the polysilicon regions (5). The device comprises regions of a second insulating material (10) situated on side of both the polysilicon regions (5) and the regions of a first insulating material (6) and over zones (14) of the gate oxide layer (4) situated near the opening on the body region (2), oxide regions (9) interposed between the polysilicon regions (5) and the regions of a second insulating material (10), oxide spacers (8) superimposed to the regions of a second insulating material (10).
摘要翻译：半导体功率器件包括第一导电类型的半导体层（1），其中形成第一导电类型的源区（3）的第二导电类型的体区（2），栅极氧化层 4），叠加到所述体区（2）上的开口叠加到所述半导体层（1），叠加到所述栅极氧化物层（4）的多晶硅区域（5）和与所述多晶硅层叠叠的第一绝缘材料（6）的区域地区（5）。该器件包括位于两个多晶硅区域（5）和第一绝缘材料（6）的区域以及位于栅极氧化物层（4）附近的区域（14）的侧面上的第二绝缘材料（10）的区域在体区域（2）上的开口，插入在多晶硅区域（5）和第二绝缘材料（10）的区域之间的氧化物区域（9），叠加到第二绝缘材料区域的氧化物间隔物（8） 10）。

6. 发明公开

EP1542237A4 SEMICONDUCTOR MEMORY 审中-公开
标题翻译： HALBLEITERSPEICHER
公开(公告)号：EP1542237A4
公开(公告)日：2008-08-06
申请号：EP02780005
申请日：2002-11-06
申请人： FUJITSU LTD
发明人： SHINOZAKI NAOHARU , KANDA TATSUYA , SATO TAKAHIKO , FUNYU AKIHIRO
IPC分类号： G11C11/406 , G11C7/00 , G11C29/02
CPC分类号： G11C29/028 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C29/02 , G11C29/50012 , G11C29/50016 , G11C2029/0403 , G11C2211/4061
摘要： A refresh signal is outputted in response to a refresh request being generated at a specified period, and refresh operation is executed. The refresh operation is ended when an access request competes with the refresh request. Consequently, access operation corresponding to an access request can be started quickly and the access time can be shortened. The access time can be shortened further more by varying the ending time of the refresh operation depending on the timing for delivering the access request. Operational margin of the refresh operation can be evaluated in a short time by forming a test circuit for informing the state of the refresh operation to the outside. As a result, developing period of a semiconductor memory can be reduced.
摘要翻译：响应于在特定周期处生成的刷新请求而输出刷新信号，并且执行刷新操作。当访问请求与刷新请求竞争时刷新操作结束。因此，可以快速开始与访问请求对应的访问操作，并且可以缩短访问时间。访问时间可以通过根据传送访问请求的时间改变刷新操作的结束时间而进一步缩短。通过形成用于向外部通知刷新操作的状态的测试电路，可以在短时间内评估刷新操作的操作余量。结果，可以减少半导体存储器的开发周期。

8. 发明公开

EP1170147A4 INFORMATION RECORDING MEDIUM AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：信息记录元件及其制造方法
公开(公告)号：EP1170147A4
公开(公告)日：2004-04-14
申请号：EP00908019
申请日：2000-03-10
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMADA NOBORU , KOJIMA RIE , MATSUNAGA TOSHIYUKI , KAWAHARA KATSUMI
IPC分类号： G11B7/2433 , G03G5/02 , G11B7/26 , G11B9/00 , G11B9/04 , G11B9/08 , G11B11/00 , G11B11/08 , G11B11/12 , G11B13/00 , G11C16/02 , H01L45/00 , B41M5/26 , G11B7/24
CPC分类号： G11B13/00 , G03G5/02 , G11B7/243 , G11B7/2433 , G11B7/2585 , G11B7/26 , G11B7/266 , G11B9/00 , G11B9/04 , G11B9/08 , G11B11/00 , G11B11/08 , G11B11/12 , G11B2007/24306 , G11B2007/24308 , G11B2007/2431 , G11B2007/24312 , G11B2007/24314 , G11B2007/24316 , G11B2007/24322 , G11B2007/2571 , G11B2007/25713 , G11C13/0004 , G11C13/04 , G11C2029/0403 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683 , Y10T428/21
摘要： An information recording medium having such a recording material layer on a substrate where reversible phase transition between electrically or optically detectable states can be caused by electric energy or electromagnetic energy. The recording material forming the recording layer is either a material having a crystal structure including lattice defects in one phase of the reversible phase transition or a material having a complex phase composed of a crystal portion including a lattice defect in one phase of the reversible phase transition and an amorphous portion. Both portions contain a common element. A part of the lattice defects are filled with an element other than the element constituting the crystal structure. The recording medium having a recording thin film exhibits little variation of the recording and reproduction characteristics even after repetition of recording and reproduction excellent weatherability, strong resistance against composition variation, and easily controllable characteristics.

9. 发明公开

EP3086322A1 PROCÉDÉ DE DÉTERMINATION D'UNE IMPULSION DE TENSION OPTIMALE POUR PROGRAMMER UNE CELLULE MÉMOIRE FLASH 审中-公开
标题翻译：一种用于确定最佳电压脉冲编程闪存单元
公开(公告)号：EP3086322A1
公开(公告)日：2016-10-26
申请号：EP16165667.3
申请日：2016-04-15
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： COIGNUS, Jean
IPC分类号： G11C16/10 , G11C29/24 , G11C29/50 , H01L27/115
CPC分类号： G11C16/12 , G11C16/0408 , G11C16/10 , G11C16/102 , G11C29/028 , G11C29/24 , G11C29/50 , G11C2029/0403 , G11C2216/02
摘要： L'invention concerne un procédé de détermination d'une impulsion de tension optimale pour programmer une cellule mémoire flash, ladite impulsion de tension optimale étant définie par une rampe de tension depuis un niveau de tension initial non-nul pendant une durée de programmation. Le procédé comprend les étapes suivantes :
- fournir un jeu de paramètres comprenant une valeur cible de fenêtre de programmation et une valeur cible de courant de drain de la cellule mémoire ;
- mesurer dynamiquement le courant de drain de la cellule mémoire lorsqu'une impulsion de tension de forme rectangulaire est appliquée sur la grille de contrôle ;
- prévoir un transistor équivalent à la cellule mémoire, de sorte que le courant de drain du transistor est égal au courant de drain de la cellule mémoire lorsque l'électrode de grille du transistor est portée à un potentiel égal au potentiel de la grille flottante de la cellule mémoire ;
- mesurer dynamiquement le courant de drain du transistor en fonction du potentiel de l'électrode de grille du transistor ;
- déterminer le potentiel de la grille flottante lors de l'impulsion de tension de forme rectangulaire, à partir de la mesure du courant de drain de la cellule mémoire et de la mesure du courant de drain du transistor ;
- déterminer, respectivement à partir de la valeur cible de courant de drain, du potentiel de la grille flottante lors de l'impulsion de tension de forme rectangulaire et de la valeur cible de fenêtre de programmation, le niveau de tension initial, la pente de la rampe de tension et la durée de programmation, de sorte que le courant de drain de la cellule mémoire pendant l'impulsion de tension optimale soit sensiblement égal à la valeur cible de courant de drain.
摘要翻译：用于编程快闪存储器单元在最佳电压脉冲确定性采矿的方法，该最佳电压脉冲被从非零初始电压电平的电压斜坡编程持续时间期间限定，worin该方法考虑到了一组包含一个参数编程窗口目标值和存储单元的漏极电流目标值。

10. 发明公开

EP1895539A3 Semiconductor device and fabrication method thereof 有权
公开(公告)号：EP1895539A3
公开(公告)日：2008-11-12
申请号：EP07107083.3
申请日：2007-04-27
申请人： FUJITSU LIMITED
发明人： Tomita, Hiroyoshi
IPC分类号： G11C11/404
CPC分类号： G11C11/4074 , G11C11/401 , G11C29/50 , G11C2029/0403 , G11C2207/2254 , H01L27/0207 , H01L27/10829
摘要： The present invention suppresses the refresh failure of a DRAM due to the dispersion of a threshold of a MOSFET. The DRAM has a first unit (5) for recording a set value of a back bias potential to be applied to a back gate of a cell transistor and a second unit (8, 9) for generating a back bias potential (V BB ) based on the set value of the back bias potential recorded in the first unit and supplying the generated back bias potential to the back gate, wherein when a threshold of a MOSFET which has a structure identical to the cell transistor and which has been fabricated in the same process as the cell transistor is greater than a target value which the cell transistor should have, a value shallower than the back bias potential for the target value is recorded in the second unit.

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