专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP3259756A1 READ CIRCUITRY FOR ELECTROSTATIC DISCHARGE SWITCHING MEMRISTIVE ELEMENT 审中-公开
标题翻译：阅读电路静电放电开关元件
公开(公告)号：EP3259756A1
公开(公告)日：2017-12-27
申请号：EP15894481.9
申请日：2015-06-05
申请人： Hewlett Packard Enterprise Development LP
发明人： BUCHANAN, Brent , GE, Ning , AULETTA, Richard James
IPC分类号： G11C11/15 , G11C13/00
CPC分类号： G11C7/24 , G11C5/06 , G11C13/0007 , G11C13/004 , G11C13/0059 , G11C13/0069 , G11C13/0097 , G11C29/50 , G11C2013/0045 , G11C2013/0054 , G11C2013/0078 , G11C2029/5002 , H02H1/0061 , H02H9/046
摘要： In the examples provided herein, an apparatus has a memristive element coupled to a pin of an integrated circuit, wherein the memristive element switches from a first resistance within a first range of resistance values to a second resistance within a second range of resistance values in response to an electrostatic discharge (ESD) event at the pin. The apparatus also has read circuitry coupled to the memristive element to determine whether a resistance of the memristive element is in the first or second range of resistance values, wherein the read circuitry includes a first transistor. Further, the coupling between the read circuitry and the memristive element does not include a direct path for current from the ESD event to a gate terminal of the first transistor.

2. 发明公开

EP2777065A4 A METHOD OF TESTING DATA RETENTION OF A NON-VOLATILE MEMORY CELL HAVING A FLOATING GATE 有权转让
标题翻译：程序对于非挥发性记忆体单元与浮栅数据保留
公开(公告)号：EP2777065A4
公开(公告)日：2015-06-10
申请号：EP12848380
申请日：2012-10-22
申请人： SILICON STORAGE TECH INC
发明人： MARKOV VIKTOR , YOO JONG-WON , BANSAL SATISH , KOTOV ALEXANDER
IPC分类号： G11C29/50 , G11C29/06
CPC分类号： G11C29/50 , G11C16/00 , G11C16/349 , G11C29/06 , G11C29/50004 , G11C29/50016

3. 发明公开

EP2823486A1 VOLTAGE MODE SENSING FOR LOW POWER FLASH MEMORY 审中-公开
标题翻译：电压模式集合低功耗闪存
公开(公告)号：EP2823486A1
公开(公告)日：2015-01-14
申请号：EP13708636.9
申请日：2013-03-01
申请人： Medtronic Inc.
发明人： WALSH, Kevin K. , PATTERSON, Paul B. , BENTON, Glen W. , WILKINSON, Jeffrey D.
IPC分类号： G11C16/28 , G11C16/26 , G11C7/08 , G11C7/22 , G11C7/14 , G11C11/00 , G11C17/12 , G11C29/50
CPC分类号： G11C16/30 , G11C7/065 , G11C7/08 , G11C7/14 , G11C7/227 , G11C11/005 , G11C16/26 , G11C16/28 , G11C17/12 , G11C29/50 , G11C29/50004
摘要： Electrically erasable flash memory and method. The memory has a data storage element and a voltage sensing circuit. The data storage element is configured to store data bits, each of the data bits having a data state. The voltage sensing circuit is selectively coupled to individual ones of data bits and is configured to bias the data bits with at least one of a bias current and a bias resistance and to read the data state of the individual ones of the plurality of data bits.

4. 发明公开

EP2810281A1 DEVICE AND METHOD TO PERFORM A PARALLEL MEMORY TEST 审中-公开
标题翻译： VORRICHTUNG VERFAHREN ZURDURCHFÜHRUNGEINER PARALLELENSPEICHERPRÜFUNG
公开(公告)号：EP2810281A1
公开(公告)日：2014-12-10
申请号：EP12805627.2
申请日：2012-11-29
申请人： Inside Secure
发明人： HICKEY, Graeme , KINCAID, Stuart
IPC分类号： G11C29/26
CPC分类号： G11C29/26 , G11C29/50 , G11C2029/2602
摘要： The invention relates to a semiconductor device including N memory modules, N being greater than or equal to three, each module having an array of memory cells arranged in rows and columns, a write circuit coupled to each module and configured to write data in the memory cells, a read circuit coupled to each module and configured to supply output data from the memory cells, a module selection circuit configured to individually select one memory module in a regular operation mode, and to collectively select two or more of the modules in a parallel mode, and a comparator circuit coupled to the N modules and configured to compare, in the parallel mode, the output data supplied by the N modules.
摘要翻译：本发明涉及一种包括N个存储器模块的半导体器件，N个大于或等于三个，每个模块具有排列成行和列的存储器单元阵列，写入电路耦合到每个模块并被配置为将数据写入存储器单元，耦合到每个模块并被配置为从存储器单元提供输出数据的读取电路，模块选择电路，被配置为以常规操作模式单独选择一个存储器模块，并且并行地选择两个或更多个模块模式，以及耦合到所述N个模块的比较器电路，并且被配置为在并行模式下比较由所述N个模块提供的输出数据。

5. 发明授权

EP2136372B1 METHOD FOR EVALUATING SRAM MEMORY CELL AND MEDIUM RECORDING EVALUATION PROGRAM OF SRAM MEMORY CELL COMPUTER READABLY 有权
标题翻译：方法SRAM存储单元的评估与介质的评价程序用于SRAM存储单元的计算机可读记录
公开(公告)号：EP2136372B1
公开(公告)日：2014-12-03
申请号：EP08721724.6
申请日：2008-03-10
申请人： Kyushu Institute of Technology
发明人： NAKAMURA, Kazuyuki , KOIKE, Hiroki
IPC分类号： G11C29/50
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5002

6. 发明公开

EP2798639A1 BUILT IN SELF-TESTING AND REPAIR DEVICE AND METHOD 审中-公开
标题翻译：一体化自测试和维修设备及方法
公开(公告)号：EP2798639A1
公开(公告)日：2014-11-05
申请号：EP13731652.7
申请日：2013-01-08
申请人： Mosys, Inc.
发明人： KLEVELAND, Bendik , SIKDAR, Dipak, K. , CHOPRA, Rajesh , PATEL, Jay
IPC分类号： G11C29/12
CPC分类号： G06F11/2094 , G06F11/106 , G11C29/06 , G11C29/12 , G11C29/16 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/50 , G11C29/808 , G11C2029/0409
摘要： A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks.

7. 发明授权

EP2202753B1 Information processing system with longevity evaluation 有权
标题翻译：与寿命评估信息处理系统
公开(公告)号：EP2202753B1
公开(公告)日：2013-11-20
申请号：EP09180239.7
申请日：2009-12-21
申请人： FUJITSU LIMITED
发明人： Kasuga, Kazunori , Mesaki, Yoshinori
IPC分类号： G11C11/406 , G11C29/52 , G11C29/50
CPC分类号： G11C29/52 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C29/023 , G11C29/50 , G11C29/50016 , G11C2211/4061 , G11C2211/4068
摘要： An information processing system (1) includes a dynamic random access memory (14), a processor for information processing in cooperation with the dynamic access memory, and a built-in diagnosis module including a longevity evaluation device, the longevity evaluation device comprising, a timer (21) for measuring an elapsed time after data is entered into a memory device, a read controller (22) for reading the data from the memory device when the elapsed time reaches a predetermined time, and an evaluator (23) for evaluating a longevity of the memory device based on an existence of an error in the data read by the read controller and the elapsed time.

8. 发明授权

EP1834337B1 SRAM TEST METHOD AND SRAM TEST ARRANGEMENT TO DETECT WEAK CELLS 有权转让
标题翻译： SRAM试验程序和SRAM测试装置用于检测弱单元
公开(公告)号：EP1834337B1
公开(公告)日：2012-09-12
申请号：EP05802806.9
申请日：2005-11-08
申请人： NXP B.V.
发明人： PINEDA DE GYVEZ, Jose de Jesus , AZIMANE, Mohamed , PAVLOV, Andrei, S.
IPC分类号： G11C29/50
CPC分类号： G11C29/50

9. 发明授权

EP2015308B1 Oscillation device, method of oscillation, and memory device 有权
标题翻译：振荡，振荡的方法和存储装置
公开(公告)号：EP2015308B1
公开(公告)日：2011-10-19
申请号：EP08158490.6
申请日：2008-06-18
申请人： Fujitsu Semiconductor Limited
发明人： Tomita, Hiroyoshi
IPC分类号： G11C11/406 , G11C29/50
CPC分类号： G11C11/406 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12015 , G11C29/14 , G11C29/50 , G11C29/50012 , G11C2211/4061

10. 发明公开

EP2286412A1 FLASH MEMORY TIMING PRE-CHARACTERIZATION FOR USE IN ORMAL OPERATION 审中-公开
标题翻译： FLASH内存时序预表征使用在操作ORMAL
公开(公告)号：EP2286412A1
公开(公告)日：2011-02-23
申请号：EP08866212.7
申请日：2008-12-23
申请人： Rambus Inc.
发明人： HAUKNESS, Brent, S. , SHAEFFER, Ian
IPC分类号： G11C29/50 , G11C16/32
CPC分类号： G11C16/32 , G06F12/0246 , G06F2212/7201 , G11C16/04 , G11C16/107 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C2029/4402
摘要： This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly. A mechanism is also provided for recalibrating memory previously marked. By minimizing variability, flash memory can be applied to a broader range of designs and potentially to a broader set of main memory applications.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式