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    • 47. 发明公开
      EP0043943A3 Method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and resulting structures 失效
    • Method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and resulting structures
    • 形成具有窄尺寸电介质区域和结构结构图案的场效应晶体管集成电路的方法
    • EP0043943A3
    • 1983-01-26
    • EP81104805
    • 1981-06-23
    • International Business Machines Corporation
    • Abbas, Shakir Ahmed , Magdo, Ingrid Emese
    • H01L21/28 , H01L21/31 , H01L21/00
    • H01L27/10844 , H01L21/0334 , H01L21/0337 , H01L21/321 , H01L29/41 , H01L29/41783 , H01L29/66537 , H01L29/66545 , H01L29/66553 , H01L29/66575 , H01L29/66583 , H01L29/66606 , H01L29/66621 , H01L2924/0002 , H01L2924/00
    • method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and more particularly a self-aligned metal process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body (10) and then forming a first insulating layer (14) on a major surface of the silicon body. A layer of polycrystalline silicon (16) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces (20) and substantially vertical surfaces (21). The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer (22) is then formed on both the substantially horizontal surfaces (20) and substantially vertical surfaces (21). Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (22) on the major surface of the silicon body (10). The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation techniques. The remaining polycrystalline silicon layer (16) is then removed by etching to leave the narrow dimensioned regions (22) on the major surface of the silicon body (10). A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source;drain PN regions and form the gate electrodes. A blanker layer of a plastic material over the conductive layer is used to planarize the surface. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having having a thickness dimension in the order of a micron or less. The gate, source and drain electrodes are thusly formed.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 48. 发明公开
      EP0043943A2 Method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and resulting structures 失效
    • Method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and resulting structures
    • 一种用于制造包括具有与由该方法生产的窄尺寸和结构的电介质区域的图案的场效应晶体管的集成电路的方法。
    • EP0043943A2
    • 1982-01-20
    • EP81104805.7
    • 1981-06-23
    • International Business Machines Corporation
    • Abbas, Shakir Ahmed , Magdo, Ingrid Emese
    • H01L21/28 , H01L21/31 , H01L21/00
    • H01L27/10844 , H01L21/0334 , H01L21/0337 , H01L21/321 , H01L29/41 , H01L29/41783 , H01L29/66537 , H01L29/66545 , H01L29/66553 , H01L29/66575 , H01L29/66583 , H01L29/66606 , H01L29/66621 , H01L2924/0002 , H01L2924/00
    • method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and more particularly a self-aligned metal process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body (10) and then forming a first insulating layer (14) on a major surface of the silicon body. A layer of polycrystalline silicon (16) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces (20) and substantially vertical surfaces (21). The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer (22) is then formed on both the substantially horizontal surfaces (20) and substantially vertical surfaces (21). Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (22) on the major surface of the silicon body (10). The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation techniques. The remaining polycrystalline silicon layer (16) is then removed by etching to leave the narrow dimensioned regions (22) on the major surface of the silicon body (10). A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source;drain PN regions and form the gate electrodes. A blanker layer of a plastic material over the conductive layer is used to planarize the surface. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having having a thickness dimension in the order of a micron or less. The gate, source and drain electrodes are thusly formed.
    • 一种用于形成具有狭窄尺寸的电介质区域的图案和场效应晶体管的集成电路的方法更具体地自对准金属过程被描述其实现自对准金属硅接触和亚微米接触到接触和金属 - 金属 间距场效应晶体管的集成电路。 触点与金属之间的绝缘是具有一微米或更小的数量级的厚度尺寸的介电材料的图案。 的金属和电介质结构是基本平坦的。 用于形成具有这种结构的集成电路的方法，包括提供硅体（10），然后形成在硅主体的主表面上的第一绝缘层（14）。 多晶硅（16）的层上形成在那里。 开口中通过反应离子蚀刻，这导致结构具有基本上水平的表面（20）和基本垂直的表面（21）的多晶硅层制成。 开口可以是在任一指定为栅极区或在集成电路中的场效应晶体管的PN结区域的区域。 然后，第二绝缘层（22）形成在两个基本水平的表面（20）和基本垂直的表面（21）。 该第二绝缘层的反应离子蚀刻去除基本上水平层，并且提供一个窄尺寸的电介质区域上的硅体（10）的主表面图案（22）。 栅极电介质或者是于此形成，或者PN结是通过扩散或离子注入技术制造。 剩余的多晶硅层（16）然后，通过蚀刻到离开窄尺寸的区域（22）上的硅体（10）的主表面除去。 导电层是毯式沉积在窄尺寸的区域和区域之间进行接触到源极漏极区域的PN并且形成栅电极。 塑料材料在所述导电层的平滑层是用来使表面平坦化。 继续反应离子蚀刻所述塑料材料和导电层直到窄尺寸的区域的顶部被达到离开的填充具有在顺序具有厚度尺寸的介电材料的图案之间的区域的金属或多晶硅图案的结构 一微米或更小。 栅极，源极和漏极电极是这样形成的。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 49. 发明公开
      EP0028655A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 失效
    • METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    • 制造半导体器件的方法
    • EP0028655A1
    • 1981-05-20
    • EP80900915.2
    • 1980-05-17
    • FUJITSU LIMITED
    • FUKUDA, Takeshi , ICHINOSE, Yoshito
    • H01L21/22 , H01L21/31 , H01L29/70 , H01L21/72
    • H01L21/76202 , H01L21/0334 , H01L21/22 , H01L21/3105 , H01L21/7621 , Y10S438/942
    • In the fabrication of a semiconductor device including a semiconductive element such as a bipolar transistor, the conventionally-known technique comprises the steps of patterning on a silicon nitride layer (3) to form windows the dimensions of which are so determined as to correspond to the dimensions of the regions (6a,6b) for bipolar transistors, isolating regions (5) and so on; and then forming at first the isolating regions (5) and sequently the regions (6a,6b) by thermal diffusion of boron. In such a method so called self- alignment, boron react with the silicon nitride layer (3) and the reaction products deteriorate silicon dioxide layer (4). According to the present invention, in the patterning process on the silicon nitride layer a first mask (13') is formed which is of an endless stripe shape in a plan view, so that the interaction of boron and silicon nitride influences on the silicon dioxide layer, i.e., a second mask (12') remarkably less than in the conventional method so as to solve the problems of decreasing yields and reliability in the fabrication of semiconductor devices.
    • 在制造包括诸如双极晶体管的半导体元件的半导体器件时，常规已知的技术包括在氮化硅层（3）上形成图案以形成窗口的步骤，窗口的尺寸被确定为对应于 用于双极晶体管的区域（6a，6b）的尺寸，隔离区域（5）等等; 然后首先形成隔离区域（5），然后通过硼的热扩散形成区域（6a，6b）。 在所谓的自对准的这种方法中，硼与氮化硅层（3）反应并且反应产物使二氧化硅层（4）劣化。 根据本发明，在氮化硅层上的图案化工艺中，形成第一掩模（13'），该第一掩模在平面图中为环形条纹形状，从而硼和氮化硅的相互作用影响二氧化硅 层，即第二掩模（12'）明显少于常规方法，以解决半导体器件制造中产量和可靠性降低的问题。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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