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1. 发明公开

EP3158586A4 MONOLITHIC INTEGRATION OF HIGH VOLTAGE TRANSISTORS&LOW VOLTAGE NON-PLANAR TRANSISTORS 审中-公开
公开(公告)号：EP3158586A4
公开(公告)日：2018-01-17
申请号：EP14895422
申请日：2014-06-20
申请人： INTEL CORP
发明人： PHOA KINYIP , NIDHI NIDHI , JAN CHIA-HONG , CHANG TING
IPC分类号： H01L29/78 , H01L21/335 , H01L21/8234 , H01L27/088 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/66
CPC分类号： H01L29/7834 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823456 , H01L21/823462 , H01L27/0886 , H01L27/0922 , H01L27/0924 , H01L29/0684 , H01L29/0847 , H01L29/66621 , H01L29/7835
摘要： High voltage transistors spanning multiple non-planar semiconductor bodies, such as fins or nanowires, are monolithically integrated with non-planar transistors utilizing an individual non-planar semiconductor body. The non-planar FETs may be utilized for low voltage CMOS logic circuitry within an IC, while high voltage transistors may be utilized for high voltage circuitry within the IC. A gate stack may be disposed over a high voltage channel region separating a pair of fins with each of the fins serving as part of a source/drain for the high voltage device. The high voltage channel region may be a planar length of substrate recessed relative to the fins. A high voltage gate stack may use an isolation dielectric that surrounds the fins as a thick gate dielectric. A high voltage transistor may include a pair of doped wells formed into the substrate that are separated by the high voltage gate stack with one or more fin encompassed within each well.

2. 发明授权

EP1676296B1 CMOS structure with strained, dislocation-free channels and a method of manufacturing the same 有权
标题翻译： CMOS结构应变，无位错的信道和用于制造其的方法
公开(公告)号：EP1676296B1
公开(公告)日：2014-12-10
申请号：EP04795664.4
申请日：2004-10-19
申请人： International Business Machines Corporation
发明人： CHIDAMBARRAO, Dureseti , DOKUMACI, Omer, c/o IBM United Kingdom Ltd.
IPC分类号： H01L29/10 , H01L21/8238 , H01L21/336 , H01L27/12 , H01L21/00 , H01L29/778
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/66621 , Y10S438/933

3. 发明公开

EP2267769A3 DRAM transistor with a gate formed in a substrate trench 审中-公开
标题翻译：具有形成在衬底上的栅极沟槽DRAM晶体管
公开(公告)号：EP2267769A3
公开(公告)日：2011-08-24
申请号：EP10011474.3
申请日：2005-08-29
申请人： Micron Technology, Inc.
发明人： Sanh, Tang , Haller, Gordon , Brown, Kris , Earl, Allen, T., III
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/336 , H01L29/10 , H01L29/417 , H01L29/78 , H01L29/423
CPC分类号： H01L29/41758 , H01L27/10817 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/1037 , H01L29/4236 , H01L29/4238 , H01L29/66621 , H01L29/78
摘要： The invention includes a transistor device (69) having a semiconductor substrate (12) with an upper surface. A pair of source/drain regions (41,59) are formed within the semiconductor substrate and a channel region (46) is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate (54) is formed within the semiconductor substrate between the pair of the source/drain regions (41,59) and can surround the channel region and/or one of the source/drain regions.

4. 发明公开

EP2187431A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：EP2187431A1
公开(公告)日：2010-05-19
申请号：EP08792574.9
申请日：2008-08-20
申请人： Seiko Instruments Inc.
发明人： RISAKI, Tomomitsu
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/0692 , H01L29/4236 , H01L29/42376 , H01L29/66621 , H01L29/66636 , H01L29/66795 , H01L29/66803 , H01L29/7851
摘要： In order to further improve a driving performance without increasing an element area in a lateral MOS having a high driving performance, in which a gate width is increased per unit area by forming a plurality of trenches horizontally with respect to a gate length direction, the semiconductor device includes: a well region which is formed of a high resistance first conductivity type semiconductor at a predetermined depth from a surface of a semiconductor substrate; a plurality of trenches which extend from a surface to a midway depth in the well region; a gate insulating film which is formed on surfaces of concave and convex portions formed by the trenches; a gate electrode embedded inside the trenches; a gate electrode film which is formed on the surface of the substrate in contact with the gate electrode embedded inside the trenches in regions of the concave and convex portions, the regions excluding vicinities of both ends of the trenches; another gate electrode film which is embedded inside the trenches in the vicinities of the both ends of the trenches in contact with the gate electrode film so that a surface of the another gate electrode film is located at a position deeper than the surface of the semiconductor substrate; and a source region and a drain region which are formed as two low resistance second conductivity type semiconductor layers formed from a part of the semiconductor surface, the part being out of contact with the another gate electrode film, so as to be shallower than the depth of the well region.
摘要翻译：为了进一步提高驱动性能而不增加具有高驱动性能的横向MOS中的元件面积，其中通过相对于栅极长度方向水平地形成多个沟槽来增加每单位面积的栅极宽度，器件包括：阱区，其由距半导体衬底的表面预定深度的高电阻第一导电类型半导体形成; 在阱区中从表面延伸到中途深度的多个沟槽; 形成在由沟槽形成的凹部和凸部的表面上的栅极绝缘膜; 嵌入沟槽内的栅电极; 栅电极膜，其形成在所述基板的与埋入所述沟槽内的所述栅电极相接触的所述凹凸部的区域中的除了所述沟槽的两端附近以外的区域; 在所述沟槽的两端附近嵌入所述沟槽中并与所述栅电极膜接触的另一栅电极膜，使得所述另一栅电极膜的表面位于比所述半导体衬底的表面深的位置 ; 以及源极区和漏极区，其形成为由半导体表面的一部分形成的两个低电阻第二导电类型半导体层，该部分与另一栅电极膜不接触，以便比深度浅井区。

5. 发明公开

EP2089908A2 DUAL STRESS DEVICE AND METHOD 审中-公开
标题翻译： ZWEIFACH-ANSPANNUNGS-EINRICHTUNG UND VERFAHREN
公开(公告)号：EP2089908A2
公开(公告)日：2009-08-19
申请号：EP07854720.5
申请日：2007-11-20
申请人： International Business Machines Corporation
发明人： ANDERSON, Brent A. , BRYANT, Andres , NOWAK, Edward J.
IPC分类号： H01L29/786 , H01L29/78 , H01L21/84 , H01L21/336
CPC分类号： H01L29/785 , H01L21/31155 , H01L21/76283 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1203 , H01L29/1037 , H01L29/66621 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.
摘要翻译：一种包括半导体材料的半导体器件，该半导体材料具有形成在该弯曲处的弯曲部和沟槽部分，以及至少部分地设置在该沟槽特征中的栅极结构。一种制造半导体结构的方法，包括在层上形成具有沟槽特征的半导体材料，在沟槽特征中至少部分地形成栅极结构，以及弯曲半导体材料，使得半导体材料中的应力在反转沟道栅结构的区域。

6. 发明公开

EP2054928A1 DRAM TRANSISTOR WITH RECESSED GATES AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：具有凹陷GATES DRAM晶体管及其制造方法
公开(公告)号：EP2054928A1
公开(公告)日：2009-05-06
申请号：EP07810696.0
申请日：2007-07-24
申请人： Micron Technology, Inc.
发明人： HALLER, Gordon, A. , TANG, Sanh, D.
IPC分类号： H01L21/8242 , G11C11/401 , H01L21/336 , H01L29/423 , H01L27/108
CPC分类号： H01L29/66621 , G11C11/405 , H01L27/10823 , H01L27/10844 , H01L27/10876 , H01L27/10891
摘要： A memory array includes a plurality of memory cells (20) formed on a semiconductor substrate (22). Individual of the memory cells include first (24) and second (26) field effect transistors respectively comprising a gate (28/30), a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are formed in openings in the substrate and are hard wired together. A conductive data are formed in openings in the substrate and line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two.

7. 发明公开

EP1676296A4 STRAINED DISLOCATION-FREE CHANNELS FOR CMOS AND METHOD OF MANUFACTURE 有权
标题翻译：的位错紧张空闲通道CMOS和方法
公开(公告)号：EP1676296A4
公开(公告)日：2008-08-20
申请号：EP04795664
申请日：2004-10-19
申请人： IBM
发明人： CHIDAMBARRAO DURESETI , DOKUMACI OMER
IPC分类号： H01L29/10 , H01L20060101 , H01L21/00 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/04 , H01L29/778 , H01L31/036 , H01R4/64
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/66621 , Y10S438/933
摘要： A semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET (40) and an nFET (45). An SiGe layer (45a) is grown in the channel of the nFET channel and a Si:C layer (40a) is grown in the pFET channel. The SiGe and Si:C match lattice network of the underlying Si layer (15) to create a stress component in an overlying grown epitaxial layer (60). In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In further implementation, the SiGe layer grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.

8. 发明公开

EP1929510A2 SILICIDED RECESSED SILICON 审中-公开
标题翻译：硅化硅橡胶
公开(公告)号：EP1929510A2
公开(公告)日：2008-06-11
申请号：EP06813796.7
申请日：2006-08-28
申请人： Micron Technology, Inc.
发明人： NEJAD, Hasan , FIGURA, Thomas, A. , HALLER, Gordon, A. , IYER, Ravi , MELDRIM, John, Mark , HARNISH, Justin
IPC分类号： H01L21/28
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon (52) is provided within a trench (50). A mixture of metals (55) is provided over the silicon (52) in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon (52) within the trench (50) is allowed to fully silicide (56) without void formation, despite a relatively high aspect ratio for the trench (50). Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays (10).
摘要翻译：提供了用于完全硅化嵌入硅的方法和结构。硅（52）设置在沟槽（50）内。在硅（52）上提供金属混合物（55），其中一种金属比硅中的硅更容易在硅中扩散，并且另一种金属在硅中的扩散比在金属中的硅不易扩散。示例性的混合物包括80％的镍和20％的钴。尽管沟槽（50）具有相对较高的纵横比，但沟槽（50）内的硅（52）被允许完全硅化（56）而不形成空隙。在其他装置中，可以通过用于存储器阵列（10）的方法形成凹入式存取装置（RAD）。

9. 发明公开

EP1732124A2 Method for forming word lines in a semiconductor memory device 有权
标题翻译：一种制备的字线的半导体存储器件的工艺
公开(公告)号：EP1732124A2
公开(公告)日：2006-12-13
申请号：EP06010424.7
申请日：2006-05-19
申请人： Nanya Technology Corporation
发明人： Lee, Pei-Ing
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10888 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L27/10891 , H01L29/66621 , H01L29/7834
摘要： A method for forming a semiconductor device. A substrate (100) is provided, wherein the substrate has recessed gates (118) and deep trench capacitor devices (102) therein. Protrusions (120) of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers (124) are formed on sidewalls of the upper portions (104) and the protrusions. Buried portions of conductive material (134a,b) are formed in spaces between the spacers. The substrate, the spacers and the buried portions are patterned to form parallel shallow trenches (132) for defining active regions. A layer of dielectric material is formed in the shallow trenches, wherein some of the buried portions (134a) serve as buried bit line contacts. Word lines (140) are formed across the recessed gates (120), wherein at least one of the word lines comprises portions overlapping the recessed gates. At least one of the overlapped portions has a narrower width than at least one of the recessed gates.
摘要翻译：一种用于形成半导体器件的方法。 A底（100）被提供，worin衬底在其中具有凹门（118）和深沟槽电容器装置（102）。凹入栅极与深沟槽电容器的设备的上部的突出部（120）显露。间隔物（124）形成在所述上部分（104）和所述突出的侧壁。导电材料的掩埋部分（134A，B）形成在所述间隔物之间的空间。基板，间隔物和掩埋部分被图案化，以形成平行的浅沟槽（132），用于活性限定区域。介电材料的层中的浅沟槽形成，worin一些掩埋部分（134A）作为埋位线接触。字线（140）在各个凹陷栅极FORMED（120）worin字线中的至少一个包括重叠的凹部门。至少重叠部分中的一个具有比所述凹门中的至少一个窄的宽度。

10. 发明公开

EP1671364A1 DRAM ACCESS TRANSISTOR AND METHOD OF FORMATION 审中-公开
标题翻译：栅极结构的DRAM存取晶体管的方法
公开(公告)号：EP1671364A1
公开(公告)日：2006-06-21
申请号：EP04784282.8
申请日：2004-09-16
申请人： MICRON TECHNOLOGY, INC.
发明人： TRAN, Luan, C.
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10811 , H01L27/10891 , H01L29/42376 , H01L29/66621 , H01L29/7834 , H01L29/7835
摘要： Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Poly-silicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.

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