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1. 发明公开

EP1340249A2 PATTERNED BURIED INSULATOR 有权
标题翻译：结构化埋置隔离
公开(公告)号：EP1340249A2
公开(公告)日：2003-09-03
申请号：EP01996045.9
申请日：2001-11-29
申请人： Infineon Technologies North America Corp. , International Business Machines Corporation
发明人： CHEN, Bomy, A. , HIRSCH, Alexander , IYER, Sundar, K. , ROVEDO, Nivo , WANN, Hsing-Jen , ZHANG, Ying
IPC分类号： H01L21/336 , H01L29/06 , H01L29/78 , H01L21/762
CPC分类号： H01L29/0653 , H01L21/7621 , H01L21/76224 , H01L21/7624 , H01L21/823418 , H01L21/823481
摘要： A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

2. 发明公开

EP0386798A3 A method for forming a channel stopper in a semiconductor structure 失效
标题翻译：一种在半导体结构中形成通道停止的方法
公开(公告)号：EP0386798A3
公开(公告)日：1993-11-03
申请号：EP90106467.5
申请日：1982-10-19
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION
发明人： Ko, Wen-Chuang
IPC分类号： H01L21/76 , H01L21/265
CPC分类号： H01L29/7325 , H01L21/76205 , H01L21/7621 , H01L21/76216
摘要： A method of forming a channel stopper in a semiconductor structure containing a substrate including the steps:
forming a protective layer of material of a predetermined thickness over a portion of said substrate;
implanting ions through said protective layer using a dosage of at least 1x10¹⁵ ions/cm² to form a channel stop region in said substrate beneath said protective layer; then
annealing said structure before the following oxidizing step; then,
oxidizing said structure to form an oxide layer over said portion of said substrate to a thickness no greater than substantially 1 micrometer (micron), thereby to minimize the lateral encroachment of said oxide material, where the thickness of said protective layer is such that said implanting, annealing, and oxidizing does not cause stacking faults in said channel stop region.

3. 发明公开

EP0421703A2 Encapsulation method for localized oxidation of silicon 失效
标题翻译： Maskierungsverfahrenfürlokalisierte氧化on硅。
公开(公告)号：EP0421703A2
公开(公告)日：1991-04-10
申请号：EP90310722.5
申请日：1990-10-01
申请人： MOTOROLA, INC.
发明人： Roth, Scott S. , Nguyen, Bich-Yen , Tobin, Philip J. , Ray, Wayne , Wachholz, E Petyr , Wissen, Glenn
IPC分类号： H01L21/76 , H01L21/32
CPC分类号： H01L21/32 , H01L21/7621
摘要： An improved LOCOS isolation process is disclosed wherein an oxidizable layer (34) is conformably deposited to overlie a silicon nitride oxidation mask (28). In accordance with one embodiment of the invention, a composite layer comprising a buffer layer (31) and an oxidation resistant material (28) is patterned to form an oxidation mask on a silicon substrate (20). A layer of an oxidizable material (34) is conformably deposited to overlie the oxidation mask. During the oxidation process used to form electrical isolation structures (36) in the substrate (20), a substantial reduction in lateral oxidation encroachment is realized.
摘要翻译：公开了改进的LOCOS分离方法，其中可氧化层（34）被顺应沉积以覆盖氮化硅氧化掩模（28）。根据本发明的一个实施例，将包含缓冲层（31）和耐氧化材料（28）的复合层图案化以在硅衬底（20）上形成氧化掩模。一层可氧化材料（34）被顺应地沉积以覆盖氧化掩模。在用于在衬底（20）中形成电隔离结构（36）的氧化过程中，实现了横向氧化侵蚀的显着减少。

4. 发明授权

EP0080731B1 Semiconductor device comprising a buried oxide isolation 失效
标题翻译：包含氧化银分离的半导体器件
公开(公告)号：EP0080731B1
公开(公告)日：1988-09-14
申请号：EP82111034.3
申请日：1982-11-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Konaka, Masami , Shibyo, Naoyuki , Dang, Ryo
IPC分类号： H01L29/78 , H01L21/76 , H01L29/08
CPC分类号： H01L21/7621 , H01L21/76 , H01L21/76216 , H01L29/0847
摘要： A semiconductor device comprising a semiconductor substrate (10) having a transistor region (20) in which a field-effect transistor having a channel width of 1 mu or less is formed, and an insulating film (12) deposited in recesses formed in the part of the semiconductor substrate surrounding the transistor region. The angle theta that is formed between the side wall (22) of the recesses and the imaginary extension of the top surface (24) of the transistor region is defined as: theta + 0.2778 epsilon 1 - 1.639 epsilon 1 + 88.39 theta >/= - 0.009259 epsilon 1 - 0.2222 epsilon 1 - 2.528 epsilon 1 + 76.76 theta >/= 50 DEG and epsilon 1 >/= 1, where epsilon 1 is the relative permittivity of the insulating film.

5. 发明授权

EP0001300B1 Method of manufacturing a LOCOS semiconductor device 失效
标题翻译：制造LOCOS半导体器件的方法
公开(公告)号：EP0001300B1
公开(公告)日：1981-11-25
申请号：EP78200122.6
申请日：1978-07-31
申请人： Philips Electronics N.V.
发明人： Van Gils, Johannes Antonius Andreas
IPC分类号： H01L21/76 , H01L21/265 , H01L29/10
CPC分类号： H01L21/32 , H01L21/76202 , H01L21/7621 , H01L21/76216 , H01L21/8226 , H01L27/0233 , H01L29/1004

6. 发明公开

EP0731983A4 IMPROVED ISOLATION BETWEEN DIFFUSION LINES IN A MEMORY ARRAY 失效
标题翻译： BETWEEN DIFFUSIONS LINES改进的绝缘在存储领域
公开(公告)号：EP0731983A4
公开(公告)日：1997-11-26
申请号：EP95931812
申请日：1995-09-13
申请人： INTEL CORP
发明人： ONG TONG-CHERN , TANG DANIEL N
IPC分类号： H01L21/762 , H01L21/8247 , H01L27/105 , H01L21/8246
CPC分类号： H01L21/7621 , H01L21/76216 , H01L21/76221 , H01L27/105 , H01L27/11521
摘要： A method of forming a memory device with improved isolation between diffusion lines. Parallel, spaced apart thick oxide strips (201) are grown on a substrate. Next, spaced apart, parallel strips (302) having a polysilicon (302a) and nitride (302b) layer, oriented perpendicular to the first strips (201), are formed. The oxide (201) between the second strips is removed, followed by an implantation to form source (402) and drain (401) regions. The nitride layer (302b) on the second strips is removed on those strips between two drain diffusions (401) and an oxidation is performed to form self-aligned thick oxide (602) over the source and drain regions. The strips from which the nitride has been removed are also oxidized, thus providing isolation between adjacent drain lines.

7. 发明公开

EP0731983A1 IMPROVED ISOLATION BETWEEN DIFFUSION LINES IN A MEMORY ARRAY 失效
标题翻译： BETWEEN DIFFUSIONS LINES改进的绝缘在存储领域
公开(公告)号：EP0731983A1
公开(公告)日：1996-09-18
申请号：EP95931812.0
申请日：1995-09-13
申请人： INTEL CORPORATION
发明人： ONG, Tong-Chern , TANG, Daniel, N.
IPC分类号： H01L21 , H01L27
CPC分类号： H01L21/7621 , H01L21/76216 , H01L21/76221 , H01L27/105 , H01L27/11521
摘要： A method of forming a memory device with improved isolation between diffusion lines. Parallel, spaced apart thick oxide strips (201) are grown on a substrate. Next, spaced apart, parallel strips (302) having a polysilicon (302a) and nitride (302b) layer, oriented perpendicular to the first strips (201), are formed. The oxide (201) between the second strips is removed, followed by an implantation to form source (402) and drain (401) regions. The nitride layer (302b) on the second strips is removed on those strips between two drain diffusions (401) and an oxidation is performed to form self-aligned thick oxide (602) over the source and drain regions. The strips from which the nitride has been removed are also oxidized, thus providing isolation between adjacent drain lines.

8. 发明授权

EP0098775B1 Procédé de réalisation de l'oxyde de champ d'un circuit intégré 失效
标题翻译：制造集成电路氧化物的方法
公开(公告)号：EP0098775B1
公开(公告)日：1987-09-09
申请号：EP83401332.8
申请日：1983-06-28
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE
发明人： Jeuch, Pierre , Parrens, Pierre
IPC分类号： H01L21/76 , H01L21/31
CPC分类号： H01L21/76216 , H01L21/31055 , H01L21/76205 , H01L21/7621 , Y10S438/978

9. 发明公开

EP0078725A3 Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure 失效
标题翻译：无外延生长和结构结构形成亚基双极晶体管的方法
公开(公告)号：EP0078725A3
公开(公告)日：1987-01-21
申请号：EP82401917
申请日：1982-10-19
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Ko, Wen-Chuang
IPC分类号： H01L21/76 , H01L29/72
CPC分类号： H01L29/7325 , H01L21/76205 , H01L21/7621 , H01L21/76216
摘要： A vertical bipolar transistor is fabricated in a semiconductor substrate without an epitaxial layer using oxide isolation and ion implantation techniques. ion implantation energies in the KEV ranges are used to implant selected ions into the substrate to form a collector region and buried collector layer less than 1 micron from the surface of the device, and then to form a base region of opposite conductivity type in the collector layer and an emitter region of the first conductivity type in the base region. Even though ion implantation techniques are used to form all regions, the base and the emitter regions can, if desired, be formed to abut the field oxide used to laterally define the islands of semiconductor material. The field oxide is formed to a thickness of less than 1 micron and typically to a thickness of approximately 0.4 microns, thereby substantially reducing the lateral oxidation of the semiconductor silicon islands and making possible devices of extremely small size, typically around 16-18 square microns. During the implantation of channel stop regions between the islands of semiconductor material a thin oxide layer is used to screen the underlying silicon from forming oxidation-induced stacking faults by the subsequent high dose field implantation and oxidation. A nitrogen anneal following this implantation and prior to forming the field oxide further reduces the frequency of stacking faults.

10. 发明公开

EP0028655A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：EP0028655A1
公开(公告)日：1981-05-20
申请号：EP80900915.2
申请日：1980-05-17
申请人： FUJITSU LIMITED
发明人： FUKUDA, Takeshi , ICHINOSE, Yoshito
IPC分类号： H01L21/22 , H01L21/31 , H01L29/70 , H01L21/72
CPC分类号： H01L21/76202 , H01L21/0334 , H01L21/22 , H01L21/3105 , H01L21/7621 , Y10S438/942
摘要： In the fabrication of a semiconductor device including a semiconductive element such as a bipolar transistor, the conventionally-known technique comprises the steps of patterning on a silicon nitride layer (3) to form windows the dimensions of which are so determined as to correspond to the dimensions of the regions (6a,6b) for bipolar transistors, isolating regions (5) and so on; and then forming at first the isolating regions (5) and sequently the regions (6a,6b) by thermal diffusion of boron. In such a method so called self- alignment, boron react with the silicon nitride layer (3) and the reaction products deteriorate silicon dioxide layer (4). According to the present invention, in the patterning process on the silicon nitride layer a first mask (13') is formed which is of an endless stripe shape in a plan view, so that the interaction of boron and silicon nitride influences on the silicon dioxide layer, i.e., a second mask (12') remarkably less than in the conventional method so as to solve the problems of decreasing yields and reliability in the fabrication of semiconductor devices.
摘要翻译：在制造包括诸如双极晶体管的半导体元件的半导体器件时，常规已知的技术包括在氮化硅层（3）上形成图案以形成窗口的步骤，窗口的尺寸被确定为对应于用于双极晶体管的区域（6a，6b）的尺寸，隔离区域（5）等等; 然后首先形成隔离区域（5），然后通过硼的热扩散形成区域（6a，6b）。在所谓的自对准的这种方法中，硼与氮化硅层（3）反应并且反应产物使二氧化硅层（4）劣化。根据本发明，在氮化硅层上的图案化工艺中，形成第一掩模（13'），该第一掩模在平面图中为环形条纹形状，从而硼和氮化硅的相互作用影响二氧化硅层，即第二掩模（12'）明显少于常规方法，以解决半导体器件制造中产量和可靠性降低的问题。

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