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1. 发明公开

EP3224860A1 POLY SANDWICH FOR DEEP TRENCH FILL 有权
标题翻译：用于深坑填充的POLY夹层
公开(公告)号：EP3224860A1
公开(公告)日：2017-10-04
申请号：EP15862620.0
申请日：2015-11-24
申请人： Texas Instruments Incorporated
发明人： HU, Binghua , PENDHARKAR, Sameer P. , JACOBS, Jarvis Benjamin
IPC分类号： H01L21/762
CPC分类号： H01L29/41 , H01L21/02164 , H01L21/02255 , H01L21/02532 , H01L21/02595 , H01L21/2253 , H01L21/26513 , H01L21/32155 , H01L21/324 , H01L21/743 , H01L21/763 , H01L28/20 , H01L28/40 , H01L29/407 , H01L29/45 , H01L29/945
摘要： A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.
摘要翻译：通过在深沟槽的侧壁上形成衬底中的深沟槽和电介质衬垫来形成半导体器件。第一未掺杂多晶硅层形成在半导体器件上，延伸到电介质衬里上的深沟槽中，但不填充深沟槽。掺杂剂被注入到第一多晶硅层中。在第一层多晶硅上形成第二层多晶硅。热驱动退火激活和扩散掺杂剂。在一个版本中，在形成第一多晶硅层之前，在深沟槽的底部去除电介质衬垫，使得深沟槽中的多晶硅提供与衬底的接触。在另一个版本中，深沟槽中的多晶硅通过电介质衬里与衬底隔离。

2. 发明公开

EP3020070A4 GALLIUM NITRIDE POWER SEMICONDUCTOR DEVICE HAVING A VERTICAL STRUCTURE 审中-公开
标题翻译：蛋黄酱 - 牛皮癣菌MIT VERTIKALER STRUKTUR
公开(公告)号：EP3020070A4
公开(公告)日：2017-03-08
申请号：EP14823270
申请日：2014-06-18
申请人： VISHAY GEN SEMICONDUCTOR LLC
发明人： CHEN MAX SK , LIN YIH-YIN
IPC分类号： H01L29/205 , H01L29/20 , H01L29/417 , H01L29/778 , H01L29/872
CPC分类号： H01L29/205 , H01L29/2003 , H01L29/41 , H01L29/4175 , H01L29/66469 , H01L29/7786 , H01L29/7787 , H01L29/7788 , H01L29/872

3. 发明公开

EP2993695A1 SEMI-FLOATING GATE DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译： HUSBSCHWEBENDE GATE-VORRICHTUNG UND HERSTELLUNGSVERFAHRENDAFÜR
公开(公告)号：EP2993695A1
公开(公告)日：2016-03-09
申请号：EP14791834.6
申请日：2014-04-29
申请人： Fudan University
发明人： WANG, Pengfei , ZHANG, Wei , SUN, Qingqing
IPC分类号： H01L27/105 , H01L29/788 , H01L29/00 , H01L21/8239
CPC分类号： H01L29/788 , H01L21/265 , H01L21/28273 , H01L21/28525 , H01L21/30604 , H01L21/3085 , H01L21/3086 , H01L27/0727 , H01L27/11521 , H01L27/11553 , H01L27/11556 , H01L29/0847 , H01L29/1037 , H01L29/401 , H01L29/41 , H01L29/42324 , H01L29/42336 , H01L29/4916 , H01L29/66356 , H01L29/66666 , H01L29/66825 , H01L29/7391 , H01L29/7827 , H01L29/7889 , H01L29/861
摘要： The disclosure, belonging to the technological field of semiconductor memory, specifically relates to a semi-floating-gate device which comprises at least a semiconductor substrate, a source region, a drain region, a floating gate, a control gate, a perpendicular channel region and a gated p-n junction diode used to connect the floating gate and the substrate. The semi-floating-gate device disclosed in the disclosure using the floating gate to store information and realizing charging or discharging of the floating gate through a gated p-n junction diode boasts small unit area, high chip density, low operating voltage in data storage and strong ability in data retain.
摘要翻译：属于半导体存储器的技术领域的公开具体涉及一种半浮栅器件，其包括至少半导体衬底，源极区，漏极区，浮置栅极，控制栅极，垂直沟道区域以及用于连接浮动栅极和衬底的选通pn结二极管。在本公开中公开的使用浮动栅极存储信息并通过门控pn结二极管实现浮置栅极的充电或放电的半浮栅器件具有小的单位面积，高芯片密度，数据存储中的低工作电压和强数据保留能力。

4. 发明公开

EP1048074A1 LEISTUNGS-MOSFET 审中-公开
标题翻译：功率MOSFET
公开(公告)号：EP1048074A1
公开(公告)日：2000-11-02
申请号：EP98966510.4
申请日：1998-12-07
申请人： Infineon Technologies AG
发明人： TIHANYI, Jenö
IPC分类号： H01L23/48 , H01L23/367
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/41 , H01L29/4175 , H01L29/41766 , H01L29/4236 , H01L29/7834 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a power MOSFET comprising a first conductive type highly doped semiconductor substrate (1) upon which a second conductive type semiconductor layer (2) is arranged and wherein a second conductive type highly doped source zone (4) and a second conductive type highly doped drain zone (3) are formed, in addition to a gate electrode (7). A metal conducting connection (9) runs between the source zone (4) and the semiconductor substrate (1). The MOSFET is thus embodied as a source down MOSFET and heat is dissipated by means of the semiconductor substrate or a cooling device (12) installed thereon.

5. 发明公开

EP0966761A1 VERTIKAL IGBT MIT EINER SOI-STRUKTUR 有权
标题翻译：垂直IGBT的SOI结构
公开(公告)号：EP0966761A1
公开(公告)日：1999-12-29
申请号：EP98965104.0
申请日：1998-12-07
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： TIHANYI, Jenö
IPC分类号： H01L21 , H01L27 , H01L29
CPC分类号： H01L29/7813 , H01L29/04 , H01L29/0649 , H01L29/402 , H01L29/41 , H01L29/7395 , H01L29/7396
摘要： SOI-IGBT with a first conductive type channel area (13), at least one second conductive type cell area (10) and at least one first conductive type intermediate area (15) defining the IGBT. The channel area (13), cell area (10) and intermediate area (15) are arranged in an insulating layer (5) on a first conductive type semi-conductor body (1). The channel area (13), cell area (10) and intermediate area (15) are connected to the semiconductor body (1) by means of recesses (6, 7, 8) in the insulating layer (5).

6. 发明公开

EP0951740A1 LATERAL DMOS TRANSISTOR FOR RF/MIRCROWAVE APPLICATIONS 失效
标题翻译：横向DMOS TRAMSISTOR帧中继/微波应用
公开(公告)号：EP0951740A1
公开(公告)日：1999-10-27
申请号：EP97941494.0
申请日：1997-09-09
申请人： Spectrian, Inc.
发明人： D'ANNA, Pablo, E. , HERBERT, Francois
IPC分类号： H01L21 , H01L29
CPC分类号： H01L29/7816 , H01L29/1087 , H01L29/1095 , H01L29/41 , H01L29/41741 , H01L29/42368 , H01L29/66674 , H01L29/7801 , Y10S148/126
摘要： An IGFET device (lateral DMOS transistor) with reduced cell dimensions which is especially suitable for RF and microwave applications, includes a semiconductor substrate having an epitaxial layer with a device formed in a surface of the epitaxial layer. A sinker contact is provided from the surface to the epitaxial layer to the substrate for use in grounding the source region to the grounded substrate. The sinker contact is aligned with the source region and spaced from the width of the channel region whereby lateral diffusion in forming the sinker contact does not adversely affect the pitch of the cell structure. The reduced pitch increases output power and reduces parasitic capacitance whereby the device is well-suited for low side switches and as an RF/microwave power transistor.

7. 发明授权

EP0468136B1 Contact structures for semiconductor devices and method for their manufacture 失效
标题翻译：用于半导体器件和它们的制备方法接触结构
公开(公告)号：EP0468136B1
公开(公告)日：1998-01-07
申请号：EP91104939.3
申请日：1991-03-28
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： Solheim, Alan G., c/o A.N. Solheim
IPC分类号： H01L29/41 , H01L29/45 , H01L21/28 , H01L21/60 , H01L21/8249
CPC分类号： H01L29/6659 , H01L21/8249 , H01L29/41 , H01L29/41783 , H01L29/456 , H01L29/665 , H01L2924/0002 , Y10S148/009 , H01L2924/00

8. 发明授权

EP0440394B1 Mosfet with substrate source contact 失效
标题翻译： MOSFET与衬底源极接触
公开(公告)号：EP0440394B1
公开(公告)日：1996-06-19
申请号：EP91300622.7
申请日：1991-01-28
申请人： MOTOROLA INC.
发明人： Johnsen, Robert J. , Sanders, Paul W.
IPC分类号： H01L29/772 , H01L29/08
CPC分类号： H01L29/7813 , H01L21/743 , H01L29/1095 , H01L29/41 , H01L29/42368 , H01L29/781 , Y10S148/168
摘要： A MOSFET (90,105,170) having a back-side source contact (94,169) and top-side gate (104,166) and drain contacts (98,168) is provided by a structure comprising superposed N (97,136), N- (96,132),P- (95,128), N (92,120) regions arranged between top (99,137) and bottom (93,121) surfaces of the semiconductor die (90,105,170). In a preferred implementation, two trenches (100,108) (148,149) are etched from the top surface (99,137) to the P- (95,128), N (92,120) interface. A buried P- (95,128), N (92,120) short (110,162) is provided in one trench (108,148) and a gate dielectric (102,160) and gate electrode (104,166) are provided over the sidewall P- (95,128) region exposed in the other trench (100,149). This creates a vertical MOSFET (170) in which the N substrate (92,120) forms the source region shorted to the P- body region (95,128) in which the channel (106) is created by the gate (104,166). Superior performance is obtained in RF grounded-source circuit applications.

9. 发明授权

EP0316799B1 Semiconductor device 失效
标题翻译：半导体设备。
公开(公告)号：EP0316799B1
公开(公告)日：1994-07-27
申请号：EP88118822.1
申请日：1988-11-11
申请人： NISSAN MOTOR CO., LTD.
发明人： Komiya, Yoshio
IPC分类号： H01L23/52 , H01L21/90
CPC分类号： H01L21/8221 , H01L21/76898 , H01L23/481 , H01L29/41 , H01L2924/0002 , H01L2924/00

10. 发明公开

EP0468136A2 Contact structures for semiconductor devices and method for their manufacture 失效
标题翻译： KontaktstrukturenfürHalbleiteranordnungen und Verfahren zu ihrer Herstellung。
公开(公告)号：EP0468136A2
公开(公告)日：1992-01-29
申请号：EP91104939.3
申请日：1991-03-28
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： Solheim, Alan G., c/o A.N. Solheim
IPC分类号： H01L29/40 , H01L21/28
CPC分类号： H01L29/6659 , H01L21/8249 , H01L29/41 , H01L29/41783 , H01L29/456 , H01L29/665 , H01L2924/0002 , Y10S148/009 , H01L2924/00
摘要： A contact structure and a method for fabrication is disclosed for a semiconductor device that includes a plurality of semiconductor regions along the surface of the device, each region having a top surface and at least a sidewall surface, where a first part of the semiconductor regions are of a first conductivity type and a second part of semiconductor regions are of a second conductivity type. Select dielectric spacers are formed along the sidewalls of the select semiconductor regions of first conductivity type
while a refractory metal such as titanium, molybdenum or tungsten is used to form contact on the sidewalls of the semiconductor regions of second conductivity type. This structure is most advantageous in bipolar, CMOS and BiCMOS transistor structures as it allows the formation of the sidewall spacers on emitter/gate contacts while having local metal interconnects with the reactive metal on the sidewall of the select base/source/drain contacts.
摘要翻译：公开了一种用于半导体器件的接触结构和制造方法，所述半导体器件包括沿器件表面的多个半导体区域，每个区域具有顶表面和至少一个侧壁表面，其中半导体区域的第一部分的第一导电类型和第二部分半导体区域是第二导电类型。沿着第一导电类型的选择半导体区域的侧壁形成选择的电介质间隔物，而使用诸如钛，钼或钨的难熔金属在第二导电类型的半导体区域的侧壁上形成接触。这种结构在双极，CMOS和BiCMOS晶体管结构中是最有利的，因为它允许在发射极/栅极触点上形成侧壁间隔物，同时具有与选择基极/源极/漏极触点的侧壁上的反应性金属的局部金属互连。

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