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1. 发明公开

EP3410830A1 DEVICE COMPRISING AN INTEGRATED CIRCUIT DIE CONNECTED TO A SUBSTRATE 审中-公开
公开(公告)号：EP3410830A1
公开(公告)日：2018-12-05
申请号：EP18183518.2
申请日：2008-12-03
申请人： Micron Technology, Inc.
发明人： LEE, Teck Kheng
IPC分类号： H05K3/40
CPC分类号： H01L24/14 , H01L21/4846 , H01L23/481 , H01L23/49811 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/0603 , H01L2224/1012 , H01L2224/13012 , H01L2224/13016 , H01L2224/13019 , H01L2224/13023 , H01L2224/1403 , H01L2224/16145 , H01L2224/73103 , H01L2224/73204 , H01L2224/81136 , H01L2224/81138 , H01L2224/8114 , H01L2224/81193 , H01L2224/812 , H01L2224/81208 , H01L2224/81801 , H01L2224/83192 , H01L2224/83194 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01033 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/20105 , H01L2924/20106 , H05K3/06 , H05K3/325 , H05K3/4007 , H05K2201/0367 , H05K2201/10674 , H05K2201/10734 , H05K2201/10977 , H05K2203/0315 , H05K2203/0369 , H05K2203/1476 , H01L2924/00012
摘要： A method is disclosed which includes forming a layer of conductive material above a substrate, forming a masking layer above the layer of conductive material, performing a first etching process on the layer of conductive material with the masking layer in place, removing the masking layer and, after removing the masking layer, performing an isotropic etching process on the 0', layer of conductive material to thereby define a plurality of piercing bond structures positioned on the substrate.

2. 发明授权

EP1984947B1 METHOD FOR FABRICATING AND FILLING CONDUCTIVE VIAS 有权
公开(公告)号：EP1984947B1
公开(公告)日：2018-12-05
申请号：EP07763302.2
申请日：2007-01-26
申请人： Micron Technology, Inc.
发明人： AKRAM, Salman , HIATT, William, Mark , OLIVER, Steve , WOOD, Alan, G. , RIGG, Sidney, B. , WARK, James, M. , KIRBY, Kyle, K.
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/17181 , H01L2924/09701
摘要： Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.

3. 发明授权

EP2351074B1 SEMICONDUCTOR SUBSTRATES WITH UNITARY VIAS AND VIA TERMINALS, AND ASSOCIATED SYSTEMS AND METHODS 有权
公开(公告)号：EP2351074B1
公开(公告)日：2018-11-21
申请号：EP09764944.6
申请日：2009-10-13
申请人： Micron Technology, Inc.
发明人： KIRBY, Kyle, K. , PAREKH, Kunal, R.
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L24/11 , H01L24/16 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/06181 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2225/06513 , H01L2225/06544 , H01L2225/06548 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.

4. 发明公开

EP3394887A1 SOLID STATE DEVICE MINIATURIZATION 审中-公开
公开(公告)号：EP3394887A1
公开(公告)日：2018-10-31
申请号：EP16879730.6
申请日：2016-11-22
申请人： Intel Corporation
发明人： MELONE, Mark , SHOJAIE, Saeed
IPC分类号： H01L23/498 , H01L23/13 , H01L23/31 , H01L23/24 , H01L25/065 , H01L25/18 , H01L23/00
CPC分类号： H01L25/162 , G06F1/1658 , H01L21/565 , H01L21/76802 , H01L21/76877 , H01L23/3107 , H01L23/3121 , H01L23/481 , H01L23/49833 , H01L23/49838 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/16 , H01L25/50 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/1306 , H01L2924/14 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/15313 , H01L2924/15333 , H01L2924/157 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2924/00014 , H01L2924/00012
摘要： One or more example embodiments of miniaturized electric devices are disclosed. In some example embodiments, the electric device includes a first thin substrate layer and a second thin substrate layer positioned above the first thin substrate layer. The electric device further includes one or more components electrically coupled to the first thin substrate layer. An overmold compound is deposited covering the one or more components between the first thin substrate and the second thin substrate. The electric device further includes one or more through mold vias that electrically and communicatively connect the first thin substrate layer and the second thin substrate layer.

5. 发明授权

EP2419930B1 THROUGH SUBSTRATE VIAS 有权
公开(公告)号：EP2419930B1
公开(公告)日：2018-09-19
申请号：EP10764819.8
申请日：2010-03-23
申请人： NXP USA, Inc.
发明人： SANDERS, Paul, W. , PETRAS, Michael, F. , RAMIAH, Chandrasekaram
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region (26) of a first thickness (27) proximate the front surface (23) of a substrate wafer (20, 20′) by: (i) from the front surface (23), forming comparatively shallow vias (30, 30′) of a first aspect ratio containing first conductors (36, 36′) extending preferably through the first thickness (27) but not through the initial wafer (20) thickness (21), (ii) removing material (22″) from the rear surface (22) to form a modified wafer (20′) of smaller final thickness (21′) with a new rear surface (22′), and (iii) forming from the new rear surface (22′), much deeper vias (40, 40′) of second aspect ratios beneath the device region (26) with second conductors (56, 56′) therein contacting the first conductors (36, 36′), thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦̸40, usefully ≦̸10 and preferably ≦̸5.

6. 发明公开

EP3364451A1 SEMICONDUCTOR PACKAGE ASSEMBLY 审中-公开
公开(公告)号：EP3364451A1
公开(公告)日：2018-08-22
申请号：EP18156200.0
申请日：2018-02-11
申请人： MediaTek Inc.
发明人： LIN, Tzu-Hung , CHANG, Chia-Cheng , PENG, I-Hsuan
IPC分类号： H01L23/367 , H01L23/538 , H01L25/10 , H01L25/18
CPC分类号： H01L23/5389 , H01L21/486 , H01L21/563 , H01L23/3128 , H01L23/3675 , H01L23/481 , H01L23/49816 , H01L23/5283 , H01L23/5386 , H01L24/05 , H01L24/13 , H01L24/81 , H01L25/105 , H01L25/18 , H01L2224/16225 , H01L2924/15311
摘要： The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package overlying a portion of the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure, a first semiconductor die and a molding compound. The first semiconductor die is disposed on a first surface of the first RDL structure and electrically coupled to the first RDL structure. The molding compound is positioned overlying the first semiconductor die and the first surface of the first RDL structure. The second semiconductor package includes a first memory die and a second memory die vertically stacked on the first memory die. The second memory die is electrically coupled to first memory die by through silicon via (TSV) interconnects formed passing through the second memory die.

7. 发明公开

EP3363040A1 LOCAL SEMICONDUCTOR WAFER THINNING 审中-公开
公开(公告)号：EP3363040A1
公开(公告)日：2018-08-22
申请号：EP16855948.2
申请日：2016-09-29
申请人： Vishay General Semiconductor LLC
发明人： CARMELO, Sanfilippo , MERLIN, Luigi , PARA, Isabella , RICHIERI, Giovanni
IPC分类号： H01L21/302 , H01L21/3105 , H01L21/683
CPC分类号： H01L21/3083 , H01L23/367 , H01L23/3736 , H01L23/481 , H01L24/03 , H01L24/05 , H01L29/0657 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/06181 , H01L2924/10158 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091
摘要： A local thinning process is employed on the backside of a semiconductor substrate such as a wafer in order to improve the thermal performance of the electronic device built on or in the front side of the wafer.

8. 发明公开

EP3327774A1 DEVICE WITH A CONDUCTIVE FEATURE FORMED OVER A CAVITY AND METHOD THEREFOR 审中-公开
公开(公告)号：EP3327774A1
公开(公告)日：2018-05-30
申请号：EP16170591.8
申请日：2016-05-20
申请人： NXP USA, Inc.
发明人： Green, Bruce McRae , Huang, Jenn Hwa , Shilimkar, Vikas
IPC分类号： H01L23/522 , H01L23/66 , H01L23/48 , H01L29/417 , H01L29/66 , H01L21/762 , H01L29/778 , H01L49/02 , H01L29/06 , H01L29/20
CPC分类号： H01L29/2003 , H01L21/30621 , H01L21/76224 , H01L23/481 , H01L23/5227 , H01L23/66 , H01L28/10 , H01L29/0657 , H01L29/4175 , H01L29/66462 , H01L29/7787 , H01L2223/6605
摘要： An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the first substrate surface and electrically coupled to the transistor, and a second conductive feature covering only a portion of the second substrate surface to define a first conductor-less region. A cavity vertically aligned with the first conductive feature within the first conductor-less region extends into the semiconductor substrate. A dielectric medium may be disposed within the cavity and have a dielectric constant less than a dielectric constant of the semiconductor substrate. A method for forming the device may include forming a semiconductor substrate, forming a transistor on the semiconductor substrate, forming the first conductive feature, forming the second conductive feature, forming the conductor-less region, forming the cavity, and filling the cavity with the dielectric medium.

9. 发明公开

EP3316295A1 DISPOSITIF COMPRENANT UN EMPILEMENT DE PUCES ÉLECTRONIQUES 审中-公开
标题翻译：包含一堆电子芯片的器件
公开(公告)号：EP3316295A1
公开(公告)日：2018-05-02
申请号：EP17164858.7
申请日：2017-04-04
申请人： STMICROELECTRONICS (ROUSSET) SAS
发明人： CHAMPEIX, Clément , BORREL, Nicolas
IPC分类号： H01L23/58 , H01L25/065
CPC分类号： H01L23/576 , H01L23/481 , H01L25/0657 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06565
摘要： L'invention concerne un dispositif comprenant : une première puce (5) ayant une face avant et une face arrière ; une deuxième puce (3) empilée avec la première puce et située du côté de la face arrière de la première puce ; et une première boucle (39) comportant : des premier (30A) et deuxième (30B) vias traversants situés dans la première puce et ayant chacun une première extrémité (32A, 32B) du côté de la face avant de la première puce et une deuxième extrémité (34A, 34B) du côté de la face arrière de la première puce ; une première piste (36) reliant les premières extrémités et située dans la première puce du côté de sa face avant ; et une deuxième piste (38) reliant les deuxièmes extrémités et située dans la deuxième puce, la première puce comprenant un circuit de détection (40) d'une caractéristique électrique de la première boucle.
摘要翻译：本发明涉及一种装置，包括：具有正面和背面的第一芯片（5）与第一芯片堆叠并且位于第一芯片的背面一侧的第二芯片; 和第一环（39），包括：第一（30A）和第二（30B）通过位于所述第一芯片的通孔和在所述第一芯片和第二的前表面的侧面各具有一个第一端部（32A，32B）（34A，34B）在所述第一芯片的背面上; 第一轨道（36），连接第一端并位于第一芯片的正面一侧; 以及连接所述第二端并位于所述第二芯片中的第二轨道（38），所述第一芯片包括具有所述第一回路的电特性的检测电路（40）。

10. 发明公开

EP3316283A1 THROUGH SUBSTRATE VIA (TSV) AND METHOD THEREFOR 审中-公开
标题翻译：通过基板通孔（TSV）及其方法
公开(公告)号：EP3316283A1
公开(公告)日：2018-05-02
申请号：EP17172306.7
申请日：2017-05-22
申请人： NXP USA, Inc.
发明人： ZHANG, Qing , LIU, Lianjun
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L21/76828 , H01L21/7684 , H01L21/76844 , H01L21/76879 , H01L23/481 , H01L23/53228 , H01L23/5329
摘要： A through substrate via (TSV) and method of forming the same are provided. The method of making the TSV may include etching a via opening into the backside of semiconductor substrate, the via opening exposing a surface of a metal landing structure. A conductive layer is deposited over the backside of semiconductor substrate, sidewalls of the via opening, and exposed surface of the metal landing structure. The conductive layer is coated with a polymer material, filling the via opening. The polymer material is developed to remove the polymer material from the backside of semiconductor substrate, leaving the via opening filled with undeveloped polymer material. A planar backside surface of semiconductor substrate is formed by removing the conductive layer.
摘要翻译：提供贯穿基板通孔（TSV）及其形成方法。制造TSV的方法可以包括蚀刻通孔开口到半导体衬底的背侧中，通孔开口暴露金属着陆结构的表面。导电层沉积在半导体衬底的背面，通孔开口的侧壁和金属接合结构的暴露表面上。导电层涂覆有聚合物材料，填充通孔开口。显影聚合物材料以从半导体衬底的背面去除聚合物材料，使通孔开口填充未显影的聚合物材料。通过去除导电层形成半导体衬底的平面背侧表面。

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