专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明公开

EP0231656A2 Silicon semiconductor device 失效
标题翻译： Silizium-Halbleiterbauelement。
公开(公告)号：EP0231656A2
公开(公告)日：1987-08-12
申请号：EP86310129.1
申请日：1986-12-24
申请人： HITACHI, LTD.
发明人： Saitoh, Tadashi , Miyazaki, Takao , Kokunai, Shigeru
IPC分类号： H01L29/267 , H01L29/72 , H01L29/86
CPC分类号： H01L29/267 , H01L29/7371
摘要： A silicon semiconductor device, e.g. an n-p-n transistor has layers (13,14,16) with p-n junctions therebetween. Electrodes (10,11,12) provide electrical connection to the layers. A further layer (15) is provided on the opposite side of n layer (14) to the junction with p layer (13),thatfurther layerforming a heterojunction and being of semiconductor whose principal components are silicon and carbon. The presence of this het - erojunction reduces the number of minority carriers recombining at the interface of the semiconductor layers (13,14,16) with the electrodes (10,11,12), so that a transistor of high current gain is produced. The invention is also applicable to other silicon semiconductor devices having a semiconductor junction.
摘要翻译：硅半导体器件，例如 n-p-n晶体管具有其间具有p-n结的层（13,14,16）。电极（10,11,12）提供与层的电连接。另外的层（15）设置在n层（14）的与播放器（13）的连接处的相对侧上，该另一层形成异质结，并且是主要成分是硅和碳的半导体。这种异质结的存在减少了在半导体层（13,14,16）与电极（10,11,12）的界面处重新结合的少数载流子的数量，从而产生高电流增益的晶体管。本发明也适用于具有半导体结的其它硅半导体器件。

92. 发明公开

EP0229362A2 Semiconductor device and method of fabrication 失效
标题翻译： Halbleitervorrichtung und Methode zur Herstellung。
公开(公告)号：EP0229362A2
公开(公告)日：1987-07-22
申请号：EP86117777.2
申请日：1986-12-19
申请人： GENERAL ELECTRIC COMPANY
发明人： Chang, Mike Fu-shing , Pifer, George Charles
IPC分类号： H01L29/10 , H01L29/784 , H01L29/72 , H01L21/225
CPC分类号： H01L29/66712 , H01L21/2255 , H01L29/1095 , H01L29/66333
摘要： A semiconductor device, such as a MOSFET or IGT, with a deep base region having a high dopant concentration at least as high as 5 x 10 19 atoms per cubic centimeter and a method of fabrication are disclosed. The novel method involves formation of the deep base region at a later stage in the fabrication and reduces the leaching of dopant from the deep base region, as well as achieving greater control over the dopant concentration in the deep base region. Further, the increased dopant concentration in the deep base region lowers the base shunt resistance of the device to provide improved electrical ruggedness. For IGTs, parasitic thyristor action is reduced.
摘要翻译：公开了具有至少高达5×10 9原子/立方厘米的高掺杂剂浓度的深基区的MOSFET或IGT的半导体器件，以及制造方法。该新方法涉及在制造的稍后阶段形成深碱性区域并减少掺杂剂从深碱性区域的浸出，以及实现对深基区域中的掺杂剂浓度的更大控制。此外，深基底区域中增加的掺杂剂浓度降低了器件的基极分流电阻，以提供改善的电气耐久性。对于IGT，寄生晶闸管动作降低。

93. 发明公开

EP0226383A2 Resonant-tunneling transistor 失效
标题翻译：晶体管共振隧穿效应。
公开(公告)号：EP0226383A2
公开(公告)日：1987-06-24
申请号：EP86309383.7
申请日：1986-12-02
申请人： FUJITSU LIMITED
发明人： Yokohama, Naoki , Imamura, Kenichi
IPC分类号： H01L29/72 , H01L29/203
CPC分类号： B82Y10/00 , B82Y30/00 , H01L29/0895 , H01L29/7376
摘要： A resonant-tunneling heterojunction bipolar transistor (RHBT) device, having a superlattice structure and a PN junction, includes an emitter layer (17), a base layer (14), a collector layer (13) operatively facing the base layer to form a PN junction at the face between the base layer and the collector layer, and a superlattice structure (16) including at least one quantum well defining a sub-band of energy at which carriers resonant-tunnel therethrough, formed at least in the emitter layer and operatively facing the base layer.
The RHBT has differential negative resistance characteristics for realizing a variety of logic circuits and includes an electron resonance and a positive hole resonance, for which the generation condition is changeable in response to a mole fraction of material of the emitter layer.
Such an RHBT, unlike a prior RHET, can be made to operate satisfactorily at normal ambient temperatures with adequate current gain.

94. 发明公开

EP0226148A2 Current limited insulated gate device 失效
标题翻译：电流限制装置与绝缘栅。
公开(公告)号：EP0226148A2
公开(公告)日：1987-06-24
申请号：EP86116958.9
申请日：1986-12-05
申请人： GENERAL ELECTRIC COMPANY
发明人： Hamza, Yilmaz
IPC分类号： H01L29/08 , H01L29/06 , H01L29/72
CPC分类号： H01L29/0696 , H01L29/7395
摘要： A current limited insulated gate transistor (IGT) is disclosed wherein the individual cells are rectangular and each has four discrete, mutually spaced emitter regions to provide a reduced gate periphery. Each cell lacks emitter portions at the cell corners to reduce current crowding in the corner areas. The size of each cell is kept small to decrease the forward voltage drop of the IGT at its operating current level and the spacing between individual cells of the IGT is minimized in order to further reduce the maximum IGT current. These features enable the cell to survive a short-circuit load condition by preventing the maximum current from reaching the latch-up level.

95. 发明公开

EP0224682A2 Method for fabricating a bipolar transistor 失效
标题翻译：制造双极晶体管的方法。
公开(公告)号：EP0224682A2
公开(公告)日：1987-06-10
申请号：EP86113866.7
申请日：1986-10-07
申请人： International Business Machines Corporation
发明人： Ahlgren, David Cutler , Bendernagel, Robert , Lange, Russell , Revitz, Martin NMN
IPC分类号： H01L21/00 , H01L21/306 , H01L21/322 , H01L29/72
CPC分类号： H01L21/033 , H01L21/31111 , Y10S148/017 , Y10S148/118
摘要： A method for fabricating a bipolar transistor having a base doping variation of less than 20% is disclosed. A polysilicon base contact bipolar transistor is formed up to the point just prior to the intrinsic base-emitter formation. The intrinsic base-emitter opening is then reactive ion etched through the polysilicon base contact layer down to and into a single crystal silicon body (10, 20, 30) thereunder, whereby the surface of the single crystal silicon is damaged. A silicon dioxide layer is then grown on the exposed and damaged single crystal silicon to convert the damaged silicon surface into a silicon dioxide layer. The silicon dioxide layer is removed by chemical etching to expose undamaged single crystal silicon. A screen silicon dioxide layer 50 to 500 Å ± 10%, e.g., 180 Å, is then formed on the thus exposed undamaged single crystal silicon. The intrinsic base region (140) is then formed by ion implantation through the screen silicon dioxide layer, the emitter region (150) is formed within the intrinsic base region and electrical contact is made to the various elements of the bipolar transistor.

96. 发明公开

EP0176146A3 High voltage semiconductor devices 失效
标题翻译：高电压半导体器件
公开(公告)号：EP0176146A3
公开(公告)日：1987-04-15
申请号：EP85201488
申请日：1985-09-18
申请人： PHILIPS ELECTRONIC AND ASSOCIATED INDUSTRIES LIMITED , N.V. Philips' Gloeilampenfabrieken
发明人： Coe, David James
IPC分类号： H01L29/06 , H01L29/72 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0696 , H01L29/0834 , H01L29/1004 , H01L29/1095 , H01L2924/0002 , H01L2924/00
摘要： A high voltage semiconductor device comprises a two-dimensional array of polygonal regions (1) in a higher resistivity body portion (2) of the opposite conductivity type. The p-n Junction (3) between these regions (1) and the body portion (2) may be, for example, a drain junction of a D-MOS transistor or a collector junction of a bipolar transistor and is reverse-biased in at least a high voltage mode of operation. In order to relieve the high electric field at the corners of the polygonal regions (1), a plurality of further regions (4) is distributed in each area of the body portion (2) between facing corners of three or more of the polygonal regions (1). These further regions (4) of the same conductivity type as the polygonal regions (1) are located on at least one line from each of these corners in a symmetrical arrangement of the further regions (4) within each area.

97. 发明公开

EP0152116A3 LATERAL BIPOLAR TRANSISTOR AND METHOD OF PRODUCING THE SAME 失效
标题翻译：横向双极晶体管及其制造方法
公开(公告)号：EP0152116A3
公开(公告)日：1986-12-30
申请号：EP85101688
申请日：1985-02-15
申请人： HITACHI, LTD.
发明人： NAKAZATO, KAZUO , NAKAMURA, TOHRU , KATO, MASATAKA , OKABE, TAKAHIRO
IPC分类号： H01L29/73 , H01L21/225 , H01L21/285 , H01L21/331 , H01L29/10 , H01L29/735 , H01L29/72 , H01L21/316
CPC分类号： H01L21/28525 , H01L21/2257 , H01L29/1008 , H01L29/735

98. 发明公开

EP0106254A3 Transistor with an adjustable energy barrier, and its application 失效
标题翻译：具有可调能量障碍物的晶体管及其应用
公开(公告)号：EP0106254A3
公开(公告)日：1986-12-10
申请号：EP83109863
申请日：1983-10-03
申请人： Siemens Aktiengesellschaft
发明人： Mader, Hermann, Dr.
IPC分类号： H01L29/10 , H01L29/72
CPC分类号： H01L29/7325 , H01L29/7606
摘要： Die Erfindung betrifft einen Transistor mit einstellbarer Energiebarriere und mit ohmschen Kontakten, der eine n⁺ pn- oder p⁺ np-Dreischichtstruktur (1, 2, 3) mit so dünn ausgebildeter mittlerer Schicht (2) (Basis) aufweist, daß bereits ohne äußbere, an die Elektroden angelegte elektri sche Spannung bei der gegebenen Dotierung dieser Schicht (2) ihr gesamter Bereich an freien Ladungsträgern verarmt ist. Für die Dotierungsdichten N von Emitter (E)-, Basis (B)- und Kollektorzone (C) gilt: N
E > N
B > N
C . Die Steuerung des Kollektorstromes erfolgt über die Änderung einer Energie barriere für Majoritätsträger mit einer angelegten Basis- Emitter-Spannung im Gegensatz zum Bipolartransistor, bei dem die Kollektorstromsteuerung durch Änderung der Mino ritätsträgerdichte in der Basis mit einer angelegten Basis- Emitter-Spannung erfolgt. Der Anwendungsbereich erstreckt sich auf diskrete bipolare Halbleiterbauelemente und auf integrierte Schaltungen; Verwendung als Verstärker, Schal ter, Mischer, Oszillator und Temperatursensor.
摘要翻译：具有可调能量势垒并具有欧姆接触的晶体管，具有具有中心层（2）基极的n + pn或p + np三层结构（1,2,3），其具有如此薄，使得即使没有施加到电极的电压，该层（2）的整个区域以其给定的掺杂水平耗尽自由电荷载流子。发射极（E），基极（B）和集电极（C）区域的掺杂密度N满足NE> NB> NC要求。通过用施加的基极 - 发射极电压改变多数载流子的能量势垒来控制集电极电流，与双极晶体管相反，双极晶体管通过施加的基极 - 发射极电压来改变基极中的少数载流子密度来控制集电极电流。应用领域包括分立双极半导体器件和集成电路; 用作放大器，开关，混频器，振荡器和温度传感器。

99. 发明公开

EP0202477A2 Method of forming an electrical short circuit between adjoining regions in an insulated gate semiconductor device 失效
标题翻译：具有绝缘栅半导体器件的制造相邻区域之间的电短路的方法。
公开(公告)号：EP0202477A2
公开(公告)日：1986-11-26
申请号：EP86105334.6
申请日：1986-04-17
申请人： GENERAL ELECTRIC COMPANY
发明人： Chow, Tat-Sing Paul , Baliga, Bantval Jayant , Love, Robert Paul
IPC分类号： H01L21/285 , H01L29/60 , H01L29/72
CPC分类号： H01L29/6634 , H01L21/3086 , H01L21/31116 , H01L29/7396
摘要： A method of forming an electrical short circuit between adjoining regions of an insulated gate semiconductor device uses retained portions of insulating layers formed over gate electrodes as an etching mask. The insulating layers are formed over the exposed surfaces of the insulated gate device, including the gate electrodes, and are then selectively removed to leave the retained portions covering the gate electrode top surfaces and sidewalls while exposing selected areas of a semiconductor substrate. The retained portions of the insulating layers are then used as an etching mask to etch away selected portions of the adjoining regions in the semiconductor substrate and expose a junction therebetween. The electrical short circuit is subsequently formed at the exposed junction.
摘要翻译：上形成的绝缘栅型半导体装置的相邻区域之间的电短路的方法使用保持绝缘层，形成在栅电极层作为蚀刻掩模的部分上。绝缘层被形成在所述绝缘栅型器件的暴露的表面，包括所述栅电极，然后被选择性地去除，以留下覆盖栅电极顶表面和侧壁同时暴露半导体衬底的选定区域上所保留的部分。绝缘层的保留部分随后被用作蚀刻掩模，以蚀刻掉，以在半导体衬底的邻接区域的选定部分和暴露的结之间存在。电气短路是在暴露结随后形成。

100. 发明公开

EP0092643A3 Ballistic conduction transistor 失效
标题翻译： BALLISTIC导体晶体管
公开(公告)号：EP0092643A3
公开(公告)日：1986-10-01
申请号：EP83100916
申请日：1983-02-01
申请人： International Business Machines Corporation
发明人： Jackson, Thomas Nelson , Woodall, Jerry Mac Pherson
IPC分类号： H01L29/10 , H01L29/72
CPC分类号： H01L29/7606 , H01L29/205 , Y10S148/084 , Y10S148/14
摘要： A majority carrier ballistic conduction transistor is fabricated with a built-in difference in barrier height (0a, 0b) between the emitter/base and collector/base interfaces by employing surface Fermi level pinning in a crystalline structure with three coplanar regions of different semiconductor materials. The central region base 3 has a thickness of the order of the mean free path of an electron- The matenals of the external regions (2. 4) are such that there is a mismatch between the crystal spacing of the external regions and the central region which causes the Fermi level of the material in the central region to be pinned in the region of the conduction band at the interfaces with the external regions and the material of the external regions is selected so that the surface Fermi level is pinned in the forbidden region. A monocrystalline structure having an emitter region (2) of GaAs. a base region (3) of InAs or W 100Ato 500Athick and a collector region (4) of GainAs provides switching in the range of 10 -12 seconds.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式