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1. 发明授权

EP0463330B1 Iterative self-aligned contact metallization process 失效
标题翻译：用于制造自对准接触金属化迭代方法
公开(公告)号：EP0463330B1
公开(公告)日：2004-08-18
申请号：EP91107384.9
申请日：1991-05-07
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Coleman, Donald J., Jr.
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/76802 , Y10S148/14 , Y10S148/164

2. 发明公开

EP0579286A3 Method of fabricating a semiconductor device with Schottky barrier 失效
标题翻译：用肖特基阻挡层制造半导体器件的方法
公开(公告)号：EP0579286A3
公开(公告)日：1994-09-07
申请号：EP93115576.6
申请日：1989-10-31
申请人： SANKEN ELECTRIC CO., LTD.
发明人： Ohtsuka,Koji , Goto, Hirokazu
IPC分类号： H01L29/91 , H01L29/40 , H01L29/06 , H01L29/48 , H01L21/329
CPC分类号： H01L29/66143 , H01L29/475 , H01L29/872 , Y10S148/139 , Y10S148/14 , Y10S438/934
摘要： A semiconductor device such as a Schottky-barrier rectifier diode is disclosed which has a barrier electrode formed on a semiconductor substrate of gallium arsenide or the like. Formed around the barrier electrode is an annular resistive layer, typically of titanium oxide, creating a Schottky barrier at its interface with the semiconductor substrate. The resistive layer has a sheet resistance of more than 10 kilohms per square. In order to prevent preliminary breakdowns from taking place at the peripheral part of the resistive layer before final breakdown of the device, the sheet resistance of the resistive layer is made higher as it extends away from the barrier electrode. For the ease of manufacture, the resistive layer can be divided into two or more annular regions of distinctly different sheet resistances.
摘要翻译：公开了一种诸如肖特基势垒整流二极管的半导体器件，其具有形成在砷化镓等的半导体衬底上的势垒电极。形成在阻挡电极周围的环状电阻层通常为氧化钛，在其与半导体衬底的界面处产生肖特基势垒。电阻层具有大于10千欧每平方的薄层电阻。为了防止在器件的最终击穿之前在电阻层的周边部分发生初步破坏，电阻层的薄层电阻随着远离阻挡电极而越高。为了易于制造，电阻层可以分成两个或更多个明显不同的薄层电阻的环形区域。

3. 发明公开

EP0463330A2 Iterative self-aligned contact metallization process 失效
标题翻译：迭代Verfahren zum Herstellen von selbstjustierender Kontaktmetallisierung。
公开(公告)号：EP0463330A2
公开(公告)日：1992-01-02
申请号：EP91107384.9
申请日：1991-05-07
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Coleman, Donald J., Jr.
IPC分类号： H01L21/90
CPC分类号： H01L21/76877 , H01L21/76802 , Y10S148/14 , Y10S148/164
摘要： A method is provided for forming multiple layers of interconnections adjacent a planar surface. A first insulator layer is formed adjacent the selected planar surface. A first conductor layer is formed adjacent the first insulator layer. A second insulator is formed adjacent the first conductor layer. A first cavity and a second cavity are formed, each having sidewalls extending through said second insulator layer and said first conductor layer. The first cavity is formed wider than the second cavity. A third insulator layer is conformally deposited adjacent the second insulator layer, such that sidewall insulators are deposited on sidewalls of the first cavity and such that the second cavity is substantially filled with insulator. An etch is performed through the first cavity to expose a portion of the planar surface. A second conductor layer is conformally deposited adjacent third insulator layer such that second conductor layer extends through the first cavity to contact the planar surface.
摘要翻译：提供了一种用于在平面附近形成多层互连的方法。邻近所选择的平面形成第一绝缘体层。在第一绝缘体层附近形成第一导体层。在第一导体层附近形成第二绝缘体。形成第一空腔和第二空腔，每个具有延伸穿过所述第二绝缘体层和所述第一导体层的侧壁。第一腔形成得比第二腔更宽。第三绝缘体层与第二绝缘体层相邻地共形沉积，使得侧壁绝缘体沉积在第一腔的侧壁上，并且使得第二腔基本上被绝缘体填充。通过第一腔进行蚀刻以暴露平坦表面的一部分。第二导体层相邻于第三绝缘体层共形沉积，使得第二导体层延伸穿过第一腔以接触平面。

4. 发明公开

EP0308939A3 Verfahren zur Herstellung eines MESFET mit selbstjustiertem Gate 失效
标题翻译：用自对准门制造MESFET的方法
公开(公告)号：EP0308939A3
公开(公告)日：1989-10-11
申请号：EP88115612.9
申请日：1988-09-22
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Willer, Josef, Dr.
IPC分类号： H01L21/28
CPC分类号： H01L29/66863 , H01L21/28587 , Y10S148/139 , Y10S148/14 , Y10S148/168
摘要： Verfahren zur Herstellung eines MESFET mit einem Gate, das sowohl bezüglich der Source- und Drain-Bereiche als auch bezüglich der zugehörigen Metallisierungen selbstjustiert ist, wobei nach Dotierung des Trägersubstrates (1) ganzflächig eine erste Metallschicht (21), eine erste Dielektrikumschicht (31) und eine erste Lackmaskenschicht (41,42) aufgebracht, durch anisotropes Ätzen (a) ein in der Dotierungsschicht (11) einen äußeren Rücksprung (11a) erzeugender Graben ausgebildet, eine zweite Dielektrikumschicht (32) isotrop abgeschieden und anisotrop bis auf Spacer (51,52) rückgeätzt, wobei in der Dotierungsschicht (11) ein innerer Rücksprung (11b) erzeugt wird (double recess), und schließlich das Gate-Metall (22) aufgebracht wird.

5. 发明公开

EP0308939A2 Verfahren zur Herstellung eines MESFET mit selbstjustiertem Gate 失效
标题翻译：一种用于制造自对准栅极MESFET方法。
公开(公告)号：EP0308939A2
公开(公告)日：1989-03-29
申请号：EP88115612.9
申请日：1988-09-22
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Willer, Josef, Dr.
IPC分类号： H01L21/28
CPC分类号： H01L29/66863 , H01L21/28587 , Y10S148/139 , Y10S148/14 , Y10S148/168
摘要： Verfahren zur Herstellung eines MESFET mit einem Gate, das sowohl bezüglich der Source- und Drain-Bereiche als auch bezüglich der zugehörigen Metallisierungen selbstjustiert ist, wobei nach Dotierung des Trägersubstrates (1) ganzflächig eine erste Metallschicht (21), eine erste Dielektrikumschicht (31) und eine erste Lackmaskenschicht (41,42) aufgebracht, durch anisotropes Ätzen (a) ein in der Dotierungsschicht (11) einen äußeren Rücksprung (11a) erzeugender Graben ausgebildet, eine zweite Dielektrikumschicht (32) isotrop abgeschieden und anisotrop bis auf Spacer (51,52) rückgeätzt, wobei in der Dotierungsschicht (11) ein innerer Rücksprung (11b) erzeugt wird (double recess), und schließlich das Gate-Metall (22) aufgebracht wird.
摘要翻译：一种用于与相关联的金属化的栅极的MESFET的制造工艺是自对准相对于源和漏区以及相对于，其中在整个表面上的载体基底（1）的掺杂的第一金属层（21），第一介电层（31）沉积和第一抗蚀剂掩模层（41,42），通过各向异性蚀刻（A）到掺杂层（11）包括外凹部（11A）产生形成的沟槽，第二介电层（32）各向同性地沉积和各向异性直到间隔件（51， 52）进行回蚀，其中（在掺杂层11），内凹槽（11B）被产生（双凹部），并最终被施加的栅极金属（22）。

6. 发明公开

EP0183032A3 High density CMOS integrated circuit manufacturing process 失效
标题翻译：高密度CMOS集成电路制造工艺
公开(公告)号：EP0183032A3
公开(公告)日：1987-04-29
申请号：EP85113079
申请日：1985-10-15
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Doering, Robert R. , Duane, Michael P. , Armstrong, Gregory J.
IPC分类号： H01L21/82
CPC分类号： H01L21/823892 , H01L27/0928 , Y10S148/082 , Y10S148/14
摘要： A semiconductor device such as a dynamic read/write memory or the like is made by a twin-well CMOS process that employs a minimum number of photomasks. Field oxide isolation areas are formed in nitride-framed recesses so a relatively plane surface is provided, and a minimum of encroachment occurs. Both P-channel and N-channel transistors are constructed with silicided, ion-implanted, source/ drain regions, self-aligned to the gates, employing an implant after sidewall oxide is in place, providing lightly-doped drains. The threshold voltages of the P-channel and N-channel transistors are established by the tank implants rather than by separate ion-implant steps for threshold adjust.

7. 发明公开

EP0128385A2 Method of producing a semiconductor device having electrodes and wirings 失效
标题翻译：制造具有电极和连接的半导体器件的方法。
公开(公告)号：EP0128385A2
公开(公告)日：1984-12-19
申请号：EP84105533.8
申请日：1984-05-15
申请人： HITACHI, LTD.
发明人： Naoki, Yamamoto , Noriyuki, Sakudo
IPC分类号： H01L21/285 , H01L21/265
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/28 , H01L21/28518 , Y10S148/14
摘要： A silicide layer or silicon alloy layer (4) is formed within a surface region of an impurity-doped region (7) on the surface of a semiconductor substrate (1) by implanting and heating any of those metals which can form silicides or silicon alloys with silicon upon heating.
The peel of a metallic electrode or wiring (5) can thus be prevented, and the electrode or wiring (5) can be directly formed on the semiconductor substrate (1).

8. 发明公开

EP0092643A2 Ballistic conduction transistor 失效
标题翻译：晶闸管
公开(公告)号：EP0092643A2
公开(公告)日：1983-11-02
申请号：EP83100916.2
申请日：1983-02-01
申请人： International Business Machines Corporation
发明人： Jackson, Thomas Nelson , Woodall, Jerry Mac Pherson
IPC分类号： H01L29/10 , H01L29/72
CPC分类号： H01L29/7606 , H01L29/205 , Y10S148/084 , Y10S148/14
摘要： A majority carrier ballistic conduction transistor is fabricated with a built-in difference in barrier height (0a, 0b) between the emitter/base and collector/base interfaces by employing surface Fermi level pinning in a crystalline structure with three coplanar regions of different semiconductor materials. The central region base 3 has a thickness of the order of the mean free path of an electron- The matenals of the external regions (2. 4) are such that there is a mismatch between the crystal spacing of the external regions and the central region which causes the Fermi level of the material in the central region to be pinned in the region of the conduction band at the interfaces with the external regions and the material of the external regions is selected so that the surface Fermi level is pinned in the forbidden region. A monocrystalline structure having an emitter region (2) of GaAs. a base region (3) of InAs or W 100Ato 500Athick and a collector region (4) of GainAs provides switching in the range of 10 -12 seconds.
摘要翻译：大多数载波弹道导体晶体管通过在具有不同半导体的三个共面区域的晶体结构中采用表面费米能级钉扎而在发射极/基极和集电极/基极界面之间的势垒高度（DIAMETER a，DIAMETER b）内部无差异地制造材料。中心区域基底3具有en电子的平均自由程的顺序的厚度。外部区域（2,4）的材料使得外部区域的晶体间距与中心区域之间存在不匹配，这导致中心区域中的材料的费米能级被钉扎在选择与外部区域的界面处的导带和外部区域的材料，使得表面费米能级被固定在禁止区域中。具有GaAs的发射极区域（2），InAs或W 100A的基极区域（3A）至500A，以及GainAs的集电极区域（4）的单晶结构提供10 <1> 2的范围内的开关，秒。

9. 发明公开

EP0077814A1 RADIATION INDUCED DEPOSITION OF METAL ON SEMICONDUCTOR SURFACES 失效
标题翻译：辐射影响金属析出对半导体表面。
公开(公告)号：EP0077814A1
公开(公告)日：1983-05-04
申请号：EP82901676.0
申请日：1982-04-16
申请人： Western Electric Company, Incorporated
发明人： DONNELLY, Vincent Michael , KARLICEK, Robert Frank, Jr.
IPC分类号： H01L21 , C23C18
CPC分类号： H01L21/288 , C23C18/14 , Y10S148/094 , Y10S148/14
摘要： Une couche metallique est formee sur une surface d'un semi-conducteur compose du groupe III-V en placant la surface au contact d'une solution contenant un metal et en dirigeant des rayons laser au travers de la solution. La radiation possede une longueur d'onde qui est absorbee dans la surface, permettant ainsi d'induire thermiquement une reaction chimique entre la surface et la solution et provoquant le depot de metal de la solution sur la surface. Des exemples specifiques de depot de Pt, Au et Zn sur InP et GaAs sont decrits.

10. 发明公开

EP0463330A3 Iterative self-aligned contact metallization process 失效
标题翻译：迭代自对准接触金属化过程
公开(公告)号：EP0463330A3
公开(公告)日：1992-09-23
申请号：EP91107384.9
申请日：1991-05-07
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Coleman, Donald J., Jr.
IPC分类号： H01L21/90
CPC分类号： H01L21/76877 , H01L21/76802 , Y10S148/14 , Y10S148/164
摘要： A method is provided for forming multiple layers of interconnections adjacent a planar surface. A first insulator layer is formed adjacent the selected planar surface. A first conductor layer is formed adjacent the first insulator layer. A second insulator is formed adjacent the first conductor layer. A first cavity and a second cavity are formed, each having sidewalls extending through said second insulator layer and said first conductor layer. The first cavity is formed wider than the second cavity. A third insulator layer is conformally deposited adjacent the second insulator layer, such that sidewall insulators are deposited on sidewalls of the first cavity and such that the second cavity is substantially filled with insulator. An etch is performed through the first cavity to expose a portion of the planar surface. A second conductor layer is conformally deposited adjacent third insulator layer such that second conductor layer extends through the first cavity to contact the planar surface.

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