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1. 发明公开

EP2985615A1 SEMICONDUCTOR DEVICE AND METHOD OF TESTING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件和测试半导体器件的方法
公开(公告)号：EP2985615A1
公开(公告)日：2016-02-17
申请号：EP15179023.5
申请日：2015-07-30
申请人： FUJITSU LIMITED
发明人： SHIKIBU, Takahiro , NAKADA, Tatsumi
IPC分类号： G01R31/28 , H01L21/66 , H01L23/538
CPC分类号： G01R31/26 , G01R31/2853 , G01R31/2856 , H01L22/22 , H01L23/5382 , H01L24/16 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596
摘要： A semiconductor device includes: a plurality of semiconductor chips; and a connecting portion that connects a plurality of terminals formed on the plurality of semiconductor chips, wherein the plurality of terminals of the plurality of semiconductor chips belong to one of first group or second group, an interval between one of first terminals belonging to the first group and one of second terminals belonging to the second group is a predetermined interval, the one of the second terminals being adjacent to the one of the first terminal, the first terminals are arranged at an interval larger than the predetermined interval, and each of the plurality of semiconductor chips includes a selecting portion that selects a signal transmitting terminal among the plurality of terminals, per each of the groups.
摘要翻译：一种半导体器件包括：多个半导体芯片; 以及连接部分，其连接形成在所述多个半导体芯片上的多个端子，其中所述多个半导体芯片的多个端子属于第一组或第二组中的一个，属于第一端子的一个第一端子之间的间隔并且属于第二组的一个第二终端是预定间隔，第二终端中的一个与第一终端中的一个相邻，第一终端以大于预定间隔的间隔布置，并且每个多个半导体芯片包括选择部分，所述选择部分针对每个组选择所述多个端子中的信号发送端子。

2. 发明公开

EP2769412A1 MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOF 有权
标题翻译：具有堆叠微电子单位及其制备方法微电子封装
公开(公告)号：EP2769412A1
公开(公告)日：2014-08-27
申请号：EP12788344.5
申请日：2012-10-17
申请人： Invensas Corporation
发明人： CASKEY, Terrence , MOHAMMED, Ilyas
IPC分类号： H01L25/10 , H01L21/56 , H01L21/60
CPC分类号： H01L25/18 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L21/76877 , H01L23/13 , H01L23/3107 , H01L23/3114 , H01L23/3185 , H01L23/49816 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/43 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L25/117 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05124 , H01L2224/05147 , H01L2224/05548 , H01L2224/05554 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/06155 , H01L2224/12105 , H01L2224/13023 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/1329 , H01L2224/133 , H01L2224/14131 , H01L2224/27334 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48108 , H01L2224/48145 , H01L2224/4824 , H01L2224/73207 , H01L2224/73215 , H01L2224/73217 , H01L2224/73265 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/82047 , H01L2224/83005 , H01L2224/83192 , H01L2224/852 , H01L2224/92144 , H01L2224/92147 , H01L2225/06506 , H01L2225/0651 , H01L2225/06548 , H01L2225/06562 , H01L2225/06596 , H01L2225/1035 , H01L2225/1052 , H01L2225/1076 , H01L2225/1082 , H01L2924/00014 , H01L2924/0665 , H01L2924/12042 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/18162 , H01L2924/186 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2224/05552
摘要： A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.
摘要翻译：一种微电子封装可包括第一微电子单元包括具有第一芯片触点的半导体芯片，封装剂在所述半导体芯片的边缘接触，以及第一单元在接触所述密封剂的表面露出，并与第一芯片触点电连接。该包装可包括第二微电子单元包括具有在其表面处的第二芯片触点的半导体芯片，和密封剂的接触在所述第二单元的所述芯片的边缘，并具有一个表面延伸远离边缘。所述芯片和所述第二单元的密封剂的表面限定的面中的第二单元。在面部封装端子可以是具有通过与第一单元触点电连接的键合引线的第一部接触，并通过与第二芯片触点接触而形成金属化通孔和迹线的第二芯片触点电连接。

3. 发明公开

EP2418587A1 High performance sub-system design & assembly 审中-公开
标题翻译： Entwurf und Zusammenbau eines Hochleistungssubsystems
公开(公告)号：EP2418587A1
公开(公告)日：2012-02-15
申请号：EP11005755.1
申请日：2002-05-02
申请人： Megica Corporation
发明人： Mou-Shiung, Lin
IPC分类号： G06F13/38 , H01L23/60 , H01L25/065
CPC分类号： H01L25/0657 , G01R31/2856 , G01R31/2884 , G01R31/31905 , G01R31/31926 , G06F13/385 , H01L23/60 , H01L24/48 , H01L25/50 , H01L2224/05599 , H01L2224/16145 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2224/85399 , H01L2225/06513 , H01L2225/06527 , H01L2225/06596 , H01L2924/00014 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry.
摘要翻译：多集成电路芯片结构提供了结构的集成电路芯片之间的片上通信，没有ESD保护电路，没有输入/输出电路。芯片间通信在集成电路芯片的内部电路之间。该多集成电路芯片结构具有一个芯片间接口电路，用于选择性地将集成电路的内部电路连接到具有ESD保护电路和设计为在测试和老化过程期间与外部测试系统进行通信的输入/输出电路的测试接口电路。多个互连的集成电路芯片结构具有安装到一个或多个第二集成电路芯片的第一集成电路芯片，以将集成电路芯片彼此物理和电连接。第一集成电路芯片具有彼此连接的芯片间接口电路，以在每个集成电路芯片的内部电路连接到彼此的集成电路芯片的内部电路或测试接口电路之间选择性地通信，以在测试期间向所述内部电路提供刺激和响应程序。模式选择器接收芯片外部的信号，以确定通信是否与其他连接的集成电路芯片中的一个或单芯片模式（例如与测试接口电路）通信。 ESD保护被添加到模式选择器电路。

4. 发明公开

EP2228822A3 Flexible Packaging for Chip-on-Chip and Package-on-Package Technologies 审中-公开
标题翻译：软包装芯片上的芯片和封装上封装技术
公开(公告)号：EP2228822A3
公开(公告)日：2010-11-03
申请号：EP10155547.2
申请日：2010-03-04
申请人： Apple Inc.
发明人： von Kaenel, Vincent
IPC分类号： H01L23/498 , H01L23/50 , H01L23/528 , H01L25/065 , H01L25/18 , H01L21/98
CPC分类号： H01L25/105 , H01L22/32 , H01L23/49816 , H01L23/49838 , H01L23/50 , H01L24/05 , H01L24/16 , H01L24/24 , H01L24/48 , H01L24/82 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/13144 , H01L2224/1319 , H01L2224/16225 , H01L2224/24225 , H01L2224/32145 , H01L2224/48227 , H01L2224/82101 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06596 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/0102 , H01L2924/01079 , H01L2924/07802 , H01L2924/14 , H01L2924/1433 , H01L2924/15173 , H01L2924/15192 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In one embodiment, a packaging solution for an application integrated circuit (IC) and one or more other ICs is provided. The packaging solution may support both chip-on-chip packaging of the application IC (in flip-chip connection to a package substrate) and other ICs (in non-flip chip orientation), and package-on-package packaging of the application IC and the other ICs. The package substrate may include a first set of pads proximate to the application IC to support chip-on-chip connection to the other IGs. The pads may be connected to conductors that extend underneath the application IC, to connect to the application IC. A second set of pads may be connected to package pins for package-on-package solutions. If the chip-on-chip solution proves reliable, support for the package-on-package solution may be eliminated and the package substrate may be reduced in size.

5. 发明公开

EP1872387A4 METHOD AND SYSTEM FOR FABRICATING SEMICONDUCTOR COMPONENTS WITH THROUGH WIRE INTERCONNECTS 有权
标题翻译： VERFAHREN UND系统ZUR HERSTELLUNG VON HALBLEITERBAUELEMENTEN MIT DURCHLEITUNGSVERBINDUNGEN
公开(公告)号：EP1872387A4
公开(公告)日：2010-08-25
申请号：EP06739005
申请日：2006-03-20
申请人： MICRON TECHNOLOGY INC
发明人： HEMBREE DAVID R
IPC分类号： H01L23/49
CPC分类号： H01L25/0657 , B23K20/004 , B23K20/005 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/81 , H01L24/85 , H01L25/50 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45164 , H01L2224/45565 , H01L2224/45644 , H01L2224/4807 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/48455 , H01L2224/48471 , H01L2224/48599 , H01L2224/48699 , H01L2224/48992 , H01L2224/78301 , H01L2224/8121 , H01L2224/81224 , H01L2224/81815 , H01L2224/85043 , H01L2224/85045 , H01L2224/85201 , H01L2224/85205 , H01L2224/85951 , H01L2224/9202 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/06589 , H01L2225/06596 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/014 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/20751 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30105 , H01L2924/3025 , H05K3/4046 , H05K2201/10287 , H05K2203/049 , Y10T29/49117 , Y10T29/49147 , Y10T29/49149 , Y10T29/49162 , Y10T29/49169 , Y10T29/53213 , H01L2924/20752 , H01L2924/00 , H01L2924/2075 , H01L2224/05599 , H01L2924/00012
摘要： A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.
摘要翻译：用于通过导线互连制造半导体部件的方法包括提供具有电路侧，背面和贯通孔的基板的步骤。该方法还包括以下步骤：将导线穿过通孔，在背面的导线上形成接触，在电路侧的导线上形成接合接触，然后将线从接合接触件断开。通线互连包括通孔中的导线，背侧的触点和电路侧的接合触点。背面的触点和电路侧的接合触点允许多个部件与相邻部件之间的电连接层叠。用于执行该方法的系统包括具有通孔的基板和具有接合毛细管的引线接合器，所述接合毛细管被配置为使导线穿过通孔，并形成接触和接合接触。半导体部件可用于形成用于电接合或测试其它半导体部件的芯片尺寸部件，晶片尺寸部件，堆叠部件或互连部件。

6. 发明公开

EP1763295A2 Electronic component embedded board and its manufacturing method 审中-公开
标题翻译：。。。。。。。。。。。。。。。。。。
公开(公告)号：EP1763295A2
公开(公告)日：2007-03-14
申请号：EP06019174.9
申请日：2006-09-13
申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.
发明人： Sunohara, Masahiro
IPC分类号： H05K1/18 , H05K3/46
CPC分类号： H05K1/186 , H01L23/5385 , H01L23/5389 , H01L25/0657 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16237 , H01L2224/73204 , H01L2224/83192 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/06586 , H01L2225/06596 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K3/0023 , H05K3/4614 , H05K2201/0195 , H05K2201/10674 , H05K2203/061 , Y10T29/49126 , Y10T29/4913 , Y10T29/49139 , Y10T29/49146 , H01L2224/05599
摘要： A second substrate 12 is provided above a first substrate 11, and an electronic component 13 is arranged between the first substrate 11 and the second substrate 12 so that between the first substrate 11 and the second substrate 12, the electronic component 13 is sealed and a photosensitive resin 14 having adhesion is provided to bond the first substrate 11 and the second substrate 12 to each other.
摘要翻译：第二基板（12）设置在第一基板（11）的上方，电子元件（13）设置在第一基板（11）和第二基板（12）之间，使得第一基板（11）与第二基板第二基板（12），电子部件（13）被密封，并且提供具有粘合力的感光性树脂（14）以将第一基板（11）和第二基板（12）彼此接合。

9. 发明公开

EP1391928A3 Chipanordung mit zumindest zwei Halbleiterchips und Verfahren zur Überprüfung der Ausrichtung zweier benachbarter Halbleiterchips 有权
标题翻译： Chipanordung具有至少两个半导体芯片和方法，用于检查两个相邻的半导体芯片的对准
公开(公告)号：EP1391928A3
公开(公告)日：2006-03-15
申请号：EP03017866.9
申请日：2003-08-05
申请人： Infineon Technologies AG
发明人： Gruber, Wolfgang , Janke, Marcus
IPC分类号： H01L23/544 , H01L21/98 , H01L25/065
CPC分类号： H01L24/81 , H01L22/34 , H01L23/48 , H01L23/576 , H01L25/0657 , H01L2224/81121 , H01L2224/81801 , H01L2225/06513 , H01L2225/06593 , H01L2225/06596 , H01L2924/01005 , H01L2924/01082 , H01L2924/19043
摘要： Halbleiterchip, Chipanordnung mit zumindest zwei Halbleiterchips und Verfahren zur Überprüfung der Ausrichtung zumindest zweier übereinander liegender Halbleiterchips in einer Chipanordnung
Es ist ein Halbleiterchip mit einer aktiven Schicht (5) vorgesehen, die von einem Substrat (S) getragen wird und zumindest eine Anschlußfläche (3) aufweist. Die aktive Schicht weist eine Detektoreinrichtung (6, 7, 8) auf, mit der ein Abdeckungsgrad der zumindest einen Anschlußfläche bestimmbar ist.

10. 发明公开

EP1565939A1 SEMICONDUCTOR DEVICE HAVING A BOND PAD AND METHOD FOR ITS FABRICATION 审中-公开
标题翻译： HALBLEITERBAUELEMENT MITKONTAKTFLÄCHEUND VERFAHREN ZU SEINER HERSTELLUNG
公开(公告)号：EP1565939A1
公开(公告)日：2005-08-24
申请号：EP03768874.4
申请日：2003-11-12
申请人： Freescale Semiconductor, Inc.
发明人： DOWNEY, Susan H. , HARPER, Peter R. , HESS, Kevin , LEONI, Michael, V. , TRAN, Tu-Anh
IPC分类号： H01L23/485 , H01L25/065
CPC分类号： H01L24/05 , H01L22/32 , H01L24/03 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/02166 , H01L2224/0392 , H01L2224/04042 , H01L2224/05001 , H01L2224/05082 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05553 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/48227 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48724 , H01L2224/48744 , H01L2224/48747 , H01L2224/48824 , H01L2224/48844 , H01L2224/48847 , H01L2224/4911 , H01L2224/49112 , H01L2224/49113 , H01L2224/49431 , H01L2225/06506 , H01L2225/0651 , H01L2225/06596 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/01007 , H01L2924/00 , H01L2924/00012
摘要： A bond pad ( 200 ) has a first wire bond region ( 202 ) and a second wire bond region ( 204 ). In one embodiment, the first wire bond region ( 202 ) extends over a passivation layer ( 18 ). In an alternate embodiment, a bond pad ( 300 ) has a probe region ( 302 ), a first wire bond region ( 304 ), and a second wire bond region ( 306 ). In one embodiment, the probe region ( 302 ) and the wire bond region ( 304 ) extend over a passivation layer ( 18 ). The bond pads may have any number of wire bond and probe regions and in any configuration. The ability for the bond pads to have multiple wire bond regions allows for multiple wire connections to a single bond pad, such as in multi-chip packages. The ability for the bond pads to extend over the passivation layer also allows for reduced integrated circuit die area.
摘要翻译：接合焊盘（200）具有第一引线键合区域（202）和第二引线接合区域（204）。在一个实施例中，第一引线接合区域（202）在钝化层（18）上延伸。在替代实施例中，接合焊盘（300）具有探针区域（302），第一引线接合区域（304）和第二引线接合区域（306）。在一个实施例中，探针区域（302）和引线接合区域（304）在钝化层（18）上延伸。接合焊盘可以具有任何数量的引线键合和探针区域并且具有任何构造。接合焊盘具有多个引线接合区域的能力允许多个引线连接到单个接合焊盘，例如在多芯片封装中。接合焊盘在钝化层上延伸的能力还允许减小集成电路管芯面积。

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