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1. 发明公开

EP2835824A3 Interconnexion de plusieurs niveaux d'un empilement de supports de composants electroniques 审中-公开
标题翻译：多层互连一叠电子元件载体
公开(公告)号：EP2835824A3
公开(公告)日：2015-04-29
申请号：EP14180064.9
申请日：2014-08-06
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： Bouvier, Christophe , Pares, Gabriel
IPC分类号： H01L23/552 , H01L25/065 , H01L25/00 , H01L27/06 , H01L21/98 , H01L21/768 , H01L23/538
CPC分类号： H01L21/76838 , H01L21/76898 , H01L23/5389 , H01L23/552 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L24/92 , H01L24/96 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/04105 , H01L2224/24137 , H01L2224/24145 , H01L2224/9202 , H01L2225/06513 , H01L2225/06537 , H01L2225/06541 , H01L2225/06548 , H01L2924/12042 , H01L2924/00
摘要： Procédé de réalisation d'un dispositif microélectronique formé d'un empilement de supports (W) dotés chacun d'un ou plusieurs composants électroniques (C) et comprenant une structure conductrice (170, 470) formée d'un premier via conducteur borgne (171b, 472) et un deuxième via conducteur borgne (171a, 473) de hauteur plus importante, le premier via et le deuxième via étant connectés entre eux.
摘要翻译：用于制造由各自设置有一个或多个电子部件（C）并且包括由第一盲导体通孔（171b）形成的导电结构（170,470）的一堆支撑件（W）形成的微电子器件的方法， 472）和更高高度的第二盲孔（171a，473），第一通孔和第二通孔连接在一起。

2. 发明公开

EP2835824A2 Interconnexion de plusieurs niveaux d'un empilement de supports de composants electroniques 审中-公开
标题翻译：网络电子元器件的载体几个堆水平
公开(公告)号：EP2835824A2
公开(公告)日：2015-02-11
申请号：EP14180064.9
申请日：2014-08-06
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： Bouvier, Christophe , Pares, Gabriel
IPC分类号： H01L23/552 , H01L25/065 , H01L25/00 , H01L27/06
CPC分类号： H01L21/76838 , H01L21/76898 , H01L23/5389 , H01L23/552 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L24/92 , H01L24/96 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/04105 , H01L2224/24137 , H01L2224/24145 , H01L2224/9202 , H01L2225/06513 , H01L2225/06537 , H01L2225/06541 , H01L2225/06548 , H01L2924/12042 , H01L2924/00
摘要： Procédé de réalisation d'un dispositif microélectronique formé d'un empilement de supports (W) dotés chacun d'un ou plusieurs composants électroniques (C) et comprenant une structure conductrice (170, 470) formée d'un premier via conducteur borgne (171b, 472) et un deuxième via conducteur borgne (171a, 473) de hauteur plus importante, le premier via et le deuxième via étant connectés entre eux.

4. 发明公开

EP2764549A2 STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS 有权
标题翻译：模拟器与终端的复制集尽量减少WIRED安排无窗
公开(公告)号：EP2764549A2
公开(公告)日：2014-08-13
申请号：EP12791307.7
申请日：2012-09-26
申请人： Invensas Corporation
发明人： CRISP, Richard, Dewitt , ZOHNI, Wael , HABA, Belgacem , LAMBRECHT, Frank
IPC分类号： H01L25/065 , H01L23/49 , H01L23/13 , G11C5/02 , G11C5/06 , H01L25/10
CPC分类号： G11C5/02 , G11C5/04 , G11C5/063 , H01L23/49838 , H01L23/50 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/0557 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/16145 , H01L2224/16225 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/49113 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06551 , H01L2225/06558 , H01L2225/06562 , H01L2225/06589 , H01L2225/1023 , H01L2225/107 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/19105 , H01L2924/3011 , H05K1/181 , H05K2201/09227 , H05K2201/10159 , Y02P70/611 , H01L2924/00012 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/05599
摘要： A microelectronic element (101) having memory storage array function has a front face (105) facing away from a substrate (102) of a microelectronic package (100), and is electrically connected with the substrate (102) through conductive structure (112) extending above the front face (105). First and second sets (114, 124) of first terminals are exposed at a surface (110) of the substrate (102) on respective first and second sides of a theoretical axis (132), each set configured to carry address information usable to determine an addressable memory location of a memory storage array of the microelectronic element. Signal assignments of the first terminals in the first set are a mirror image of the signal assignments of the first terminals in the second set.
摘要翻译：具有存储器存储阵列功能的微电子元件（101）具有从微电子封装（100）的衬底（102）的面向远离前表面（105），并且电通过导电结构（112）的基板连接上述延伸前表面（105）。第一端子（104），在第一和第二组（114，124）上的理论轴线（132）的respectivement第一和第二相对侧上设置在位置被布置。各组的第一端子被配置成携带可用于微电子元件的存储器storageArray的可寻址存储器位置的确定性矿地址信息。在所述第一组（114）所述第一终端具有信号分配哪些是所述第一终端的所述第二组（124）的信号分配的镜像。

5. 发明公开

EP2399288A2 INTEGRATED CIRCUIT MICRO-MODULE 有权
标题翻译： MIKROMODUL EINER INTEGRIERTEN SCHALTUNG
公开(公告)号：EP2399288A2
公开(公告)日：2011-12-28
申请号：EP10744091.9
申请日：2010-01-08
申请人： National Semiconductor Corporation
发明人： SMEYS, Peter , JOHNSON, Peter , DEANE, Peter , RAZOUK, Reda R.
IPC分类号： H01L23/48
CPC分类号： H01L21/4853 , H01L21/486 , H01L21/6835 , H01L23/367 , H01L23/427 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L23/552 , H01L23/642 , H01L23/645 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/0652 , H01L25/112 , H01L25/16 , H01L2221/68377 , H01L2223/6677 , H01L2224/04105 , H01L2224/24137 , H01L2224/24145 , H01L2224/24226 , H01L2224/24227 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2224/82 , H01L2924/00
摘要： In one aspect, an integrated circuit package composed of a plurality of immediately adjacent stacked layers of cured, planarizing, photo-imageable dielectric is described. At least one interconnect layer is provided between a pair of adjacent dielectric layers. An integrated circuit is positioned within one or more of the dielectric layers such that at least one of the dielectric layers extends over the active surface of the integrated circuit. The integrated circuit is electrically coupled with I/O pads on a surface of the package at least in part through the interconnect layer. In particular embodiments, the package can include thermal pipes, a heat sink, multiple integrated circuits, one or more dielectric layers, sensors, optical elements, passive devices and/or a substrate with embedded components. Various methods for forming the aforementioned packages are also described.
摘要翻译：在一个方面，描述了由固化的，平坦化的可光致成像电介质的多个紧邻的堆叠层组成的集成电路封装。在一对相邻的电介质层之间提供至少一个互连层。集成电路位于一个或多个介电层内，使得介电层中的至少一个在集成电路的有源表面上延伸。集成电路至少部分地通过互连层与封装表面上的I / O焊盘电耦合。在具体实施例中，封装可以包括热管，散热器，多个集成电路，一个或多个电介质层，传感器，光学元件，无源器件和/或具有嵌入元件的衬底。还描述了用于形成上述包装的各种方法。

6. 发明公开

EP1763894A2 STACKED DIE BGA OR LGA COMPONENT ASSEMBLY 审中-公开
标题翻译：堆叠模块BGA或LGA组件组件
公开(公告)号：EP1763894A2
公开(公告)日：2007-03-21
申请号：EP05736405.1
申请日：2005-04-12
申请人： Vertical Circuits, Inc.
发明人： ROBINSON, Marc , VINDASIUS, Al , ALMEN, Don , JACOBSEN, Larry
IPC分类号： H01L23/02
CPC分类号： H01L25/00 , H01L21/563 , H01L23/3128 , H01L23/34 , H01L23/525 , H01L25/0657 , H01L2224/24145 , H01L2224/73203 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06551 , H01L2225/06582 , H01L2225/06586 , H01L2924/01046 , H01L2924/01079 , H01L2924/09701 , H01L2924/15311 , H01L2924/3011
摘要： The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack.. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.
摘要翻译：本发明提供了一种用于垂直互连半导体管芯，集成电路管芯或多个管芯段的装置。延伸到管芯或部分的一个或多个侧面的金属重新布线互连可以可选地被添加到管芯或多管芯部分，以在管芯的表面上为外部电连接点提供边缘接合焊盘。在将金属重布线互连添加到晶片上的管芯上之后，可选地将晶片减薄并且通过切割或其他合适的分割方法将每个管芯或多个管芯分段从晶片切割下来。在将晶粒或多个晶粒片段从晶片上分离或切割之后，对晶粒或多个晶粒片段的所有表面施加绝缘，在所需电连接垫片上方的绝缘体中形成开口，并且将晶粒或多个晶粒片段放置在彼此的顶部以形成堆叠。通过将短的柔性键合线或键合带附接到裸片的外围边缘处的暴露的电连接垫，将堆叠中的垂直相邻的分段电互连，所述裸露的电连接垫从裸片水平突出以及将导电聚合物或环氧树脂，细丝或线施加到叠层的一个或多个侧面。

7. 发明公开

EP1367645A3 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造
公开(公告)号：EP1367645A3
公开(公告)日：2006-12-27
申请号：EP03253279.8
申请日：2003-05-23
申请人： FUJITSU LIMITED
发明人： Fujisawa, Tetsuya, c/o Fujitsu Limited , Matsuki, Hirohisa, c/o Fujitsu Limited , Igawa, Osamu, c/o Fujitsu Limited , Aiba, Yoshitaka, c/o Fujitsu Limited , Ikumo, Masamitsu, c/o Fujitsu Limited , Sato, Mitsutaka, c/o Fujitsu Limited
IPC分类号： H01L23/538 , H01L21/60 , H01L23/498 , H01L25/065 , H01L21/98 , H01L21/58 , H01L23/31
CPC分类号： H01L24/29 , H01L23/3128 , H01L23/49822 , H01L23/5389 , H01L23/544 , H01L24/19 , H01L24/24 , H01L24/27 , H01L24/48 , H01L24/82 , H01L24/83 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2223/54426 , H01L2223/5446 , H01L2224/04042 , H01L2224/04105 , H01L2224/05599 , H01L2224/12105 , H01L2224/16145 , H01L2224/24137 , H01L2224/24145 , H01L2224/24155 , H01L2224/24195 , H01L2224/24265 , H01L2224/274 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48227 , H01L2224/4847 , H01L2224/73209 , H01L2224/73253 , H01L2224/73267 , H01L2224/83005 , H01L2224/83132 , H01L2224/83191 , H01L2224/83192 , H01L2224/83856 , H01L2224/85399 , H01L2224/92 , H01L2224/92244 , H01L2224/97 , H01L2225/0651 , H01L2225/06524 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01043 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10253 , H01L2924/12044 , H01L2924/1431 , H01L2924/1434 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19103 , H01L2924/19104 , H01L2924/19107 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： In a semiconductor device (10) circuit formation surfaces of each of a plurality of semiconductor chips (12, 13) can be easily located at even level when the semiconductor chips are arranged side by side so that a process of forming rearrangement wiring is simplified. The semiconductor chips are mounted on a substrate (11) via an adhesive layer (15) in a two-dimensional arrangement. A resin layer (14) is formed on the substrate (11) and located around the semiconductor elements. The resin layer (14) has the same thickness as a thickness of the semiconductor elements (12, 13). An organic insulating layer (16) is formed over a surface of the resin layer and circuit formation surfaces of the semiconductor elements. A
rearrangement wiring layer (17) is formed on the organic insulating layer (16) and electrodes of the semiconductor chips. External connection terminals are electrically connected to the circuit formation surfaces of the semiconductor elements through wiring in the rearrangement wiring layer.

8. 发明公开

EP1287560A1 VERTICAL ELECTRICAL INTERCONNECTIONS IN A STACK 审中-公开
标题翻译：垂直电连接在一堆
公开(公告)号：EP1287560A1
公开(公告)日：2003-03-05
申请号：EP01918005.8
申请日：2001-03-15
申请人： Thin Film Electronics ASA
发明人： NORDAL, Per-Erik , GUDESEN, Hans, Gude , LEISTAD, Geirr, I. , GUSTAFSSON, Göran
IPC分类号： H01L23/522 , H01L21/60
CPC分类号： H01L24/25 , H01L24/24 , H01L24/82 , H01L25/0657 , H01L2224/24051 , H01L2224/24145 , H01L2224/24146 , H01L2224/24225 , H01L2224/24226 , H01L2224/25175 , H01L2224/76155 , H01L2224/82102 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/01055 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/30105 , H01L2924/00
摘要： In a memory and/or data processing device having at least two stacked layers which are supported by a substrate or forming a sandwich self-supporting structure, wherein the layers comprise memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate, the layers are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack. A method for manufacturing a device of this kind comprises steps for adding said layers successively, one layer at a time such that the layers form a staggered structure and for providing one or more layers with at least one electrical contacting pad for linking to one or more interlayer edge connectors.

9. 发明授权

EP0766909B1 VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS 失效
标题翻译：过程之间的垂直连接FOR SILICON SEGMENTS
公开(公告)号：EP0766909B1
公开(公告)日：2001-12-19
申请号：EP95923676.1
申请日：1995-06-08
申请人： CUBIC MEMORY
发明人： PEDERSEN, David, V. , FINLEY, Michael, G. , SAUTTER, Kenneth, M.
IPC分类号： H05K7/06 , H01L21/00
CPC分类号： H01L24/81 , H01L23/3737 , H01L23/4824 , H01L23/5256 , H01L23/5328 , H01L23/5382 , H01L23/5385 , H01L24/10 , H01L24/13 , H01L24/75 , H01L24/83 , H01L25/0652 , H01L25/0657 , H01L25/074 , H01L25/50 , H01L29/0657 , H01L2224/13 , H01L2224/13099 , H01L2224/16145 , H01L2224/24145 , H01L2224/2919 , H01L2224/29399 , H01L2224/32145 , H01L2224/75 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2224/92244 , H01L2225/0651 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06593 , H01L2225/06596 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0665 , H01L2924/0781 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H01R4/04 , H01R29/00 , H05K3/305 , H05K3/321 , H05K7/023 , H05K2201/09472 , H05K2201/10477 , H05K2201/10674 , H05K2201/10719 , H05K2201/10727 , Y02P70/613 , H01L2924/00 , H01L2924/3512 , H01L2224/29099
摘要： A method and apparatus for vertically interconnecting stacked silicon segments (36) is disclosed. Each segment (36) includes a plurality of adjacent dies on a semiconductor wafer. The plurality of dies on a segment are interconnected using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads (42) for external electrical connection points. Each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls (102) on each of the segments (36). After the segments are cut from the wafer, the segments are placed on top of one another to form a stack (112). Vertically adjacent segments (36) in the stack (112) are electrically interconnected by applying electrically conductive epoxy traces (130) to all four sides of the stack. The inwardly sloping edge walls (102) of each of the segments (36) in the stack (112) provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked.

10. 发明公开

EP0885451A4 TRANSPARENT CONTACTS FOR ORGANIC DEVICES 失效
标题翻译：透明取得联系有机器件
公开(公告)号：EP0885451A4
公开(公告)日：1999-02-17
申请号：EP97906023
申请日：1997-02-15
申请人： UNIV PRINCETON
发明人： FORREST STEPHEN R , BURROWS PAUL E , THOMPSON MARK E , BULOVIC VLADIMIR , GU GONG
IPC分类号： H05B33/10 , C09K11/06 , C23C14/34 , G09G3/00 , H01L27/15 , H01L27/32 , H01L33/00 , H01L51/00 , H01L51/05 , H01L51/30 , H01L51/50 , H01L51/52 , H05B33/12 , H05B33/14 , H05B33/26 , H01J1/62
CPC分类号： H01L51/5234 , C09K11/06 , H01L27/156 , H01L27/3209 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0042 , H01L51/005 , H01L51/0051 , H01L51/0059 , H01L51/0077 , H01L51/008 , H01L51/0081 , H01L51/0084 , H01L51/5012 , H01L51/5036 , H01L51/5048 , H01L51/5243 , H01L51/5246 , H01L51/5253 , H01L2224/24145 , H01L2251/5323 , H01L2924/01021 , H01L2924/01068 , H01L2924/12041 , H01L2924/12044 , H01L2924/00
摘要： A multicolor organic light emitting device employs vertically stacked layers (308, 310, 312) of double heterostructure devices which are fabricated from organic compounds. The vertical stacked structure (300) is formed on a glass base (302) having a transparent coating of ITO (304) or similar metal to provide a substrate. Deposited on the substrate is the vertical stacked arrangement of three double heterostructure devices (308, 310, 312), each fabricated from a suitable organic material. Stacking is implemented such that the double heterostructure with the longest wavelength is on the top of the stack.

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