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1. 发明授权

EP2764545B1 STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS 有权
公开(公告)号：EP2764545B1
公开(公告)日：2018-07-04
申请号：EP12775582.5
申请日：2012-10-02
申请人： Invensas Corporation
发明人： CRISP, Richard, Dewitt , ZOHNI, Wael , HABA, Belgacem , LAMBRECHT, Frank
IPC分类号： H01L25/065 , H01L23/13 , G11C5/02 , G11C5/04 , G11C5/06
CPC分类号： G11C5/04 , G11C5/02 , G11C5/063 , G11C5/066 , H01L23/13 , H01L23/3128 , H01L23/36 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L2224/02375 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05569 , H01L2224/0557 , H01L2224/06155 , H01L2224/06156 , H01L2224/06165 , H01L2224/06179 , H01L2224/06181 , H01L2224/06515 , H01L2224/12105 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/48471 , H01L2224/49113 , H01L2224/49175 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06558 , H01L2225/06562 , H01L2225/06565 , H01L2225/06568 , H01L2225/06575 , H01L2225/06589 , H01L2924/00014 , H01L2924/01322 , H01L2924/10161 , H01L2924/1434 , H01L2924/1435 , H01L2924/1436 , H01L2924/1438 , H01L2924/15172 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/181 , H01L2924/18161 , H01L2924/3011 , H05K1/181 , H05K2201/09227 , H05K2201/10159 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A microelectronic package (100) can include a plurality of vertically stacked semiconductor chips 632, 637, the front face of at least one chip facing away from a first substrate surface (108), one or more columns (138, 143) of contacts (132) extending in a first direction (142) along surface (108). Columns (104A, 107B, 109A, 109B) of terminals (105 107) exposed at a second substrate surface (110) extend in the first direction. First terminals (105) disposed in a central region (112) of surface (110) which has width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the at least one semiconductor chip can intersect the central region.

3. 发明公开

EP2399288A4 INTEGRATED CIRCUIT MICRO-MODULE 有权
标题翻译：微型模块集成电路
公开(公告)号：EP2399288A4
公开(公告)日：2017-04-19
申请号：EP10744091
申请日：2010-01-08
申请人： NAT SEMICONDUCTOR CORP
发明人： SMEYS PETER , JOHNSON PETER , DEANE PETER , RAZOUK REDA R
IPC分类号： H01L23/48
CPC分类号： H01L21/4853 , H01L21/486 , H01L21/6835 , H01L23/367 , H01L23/427 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L23/552 , H01L23/642 , H01L23/645 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/0652 , H01L25/112 , H01L25/16 , H01L2221/68377 , H01L2223/6677 , H01L2224/04105 , H01L2224/24137 , H01L2224/24145 , H01L2224/24226 , H01L2224/24227 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2224/82 , H01L2924/00
摘要： In one aspect, an integrated circuit package composed of a plurality of immediately adjacent stacked layers of cured, planarizing, photo-imageable dielectric is described. At least one interconnect layer is provided between a pair of adjacent dielectric layers. An integrated circuit is positioned within one or more of the dielectric layers such that at least one of the dielectric layers extends over the active surface of the integrated circuit. The integrated circuit is electrically coupled with I/O pads on a surface of the package at least in part through the interconnect layer. In particular embodiments, the package can include thermal pipes, a heat sink, multiple integrated circuits, one or more dielectric layers, sensors, optical elements, passive devices and/or a substrate with embedded components. Various methods for forming the aforementioned packages are also described.

4. 发明公开

EP2901714A1 EMBEDDED CIRCUIT IN A MEMS DEVICE 审中-公开
标题翻译：内嵌的电路的MEMS器件，
公开(公告)号：EP2901714A1
公开(公告)日：2015-08-05
申请号：EP13842019.5
申请日：2013-09-26
申请人： Knowles Electronics, LLC
发明人： VOS, Sandra F. , GIESECKE, Daniel
IPC分类号： H04R19/04 , H01L29/84
CPC分类号： H04R19/04 , H01L2224/04105 , H01L2224/20 , H01L2224/24145 , H01L2224/2518 , H01L2224/32225 , H01L2224/73267 , H01L2924/15151 , H04R1/04 , H04R19/005 , H04R31/00
摘要： A Microelectromechanical System (MEMS) microphone includes a printed circuit board, a MEMS die, and an integrated circuit. The MEMS die disposed on a top surface of the printed circuit board. The integrated circuit is disposed at least partially within the printed circuit board and produces at least one output signal. The at least one output signal of the integrated circuit is routed directly into at least one conductor to access pads at the printed circuit board. The access pads are disposed on a bottom surface of the printed circuit board that is opposite the top surface. The integrated circuit includes conductive pads and an interface layer is disposed between the conductive pads of the integrated circuit and the printed circuit board.

5. 发明公开

EP2866258A3 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：EP2866258A3
公开(公告)日：2015-07-29
申请号：EP14193115.4
申请日：2003-05-23
申请人： Socionext Inc.
发明人： Fujisawa, Tetsuya , Matsuki, Hirohisa , Igawa, Osamu , Aiba, Yoshitaka , Ikumo, Masamitsu , Sato, Mitsutaka
IPC分类号： H01L23/538 , H01L21/60 , H01L23/544
CPC分类号： H01L24/29 , H01L23/3128 , H01L23/49822 , H01L23/5389 , H01L23/544 , H01L24/19 , H01L24/24 , H01L24/27 , H01L24/48 , H01L24/82 , H01L24/83 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2223/54426 , H01L2223/5446 , H01L2224/04042 , H01L2224/04105 , H01L2224/05599 , H01L2224/12105 , H01L2224/16145 , H01L2224/24137 , H01L2224/24145 , H01L2224/24155 , H01L2224/24195 , H01L2224/24265 , H01L2224/274 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48227 , H01L2224/4847 , H01L2224/73209 , H01L2224/73253 , H01L2224/73267 , H01L2224/83005 , H01L2224/83132 , H01L2224/83191 , H01L2224/83192 , H01L2224/83856 , H01L2224/85399 , H01L2224/92 , H01L2224/92244 , H01L2224/97 , H01L2225/0651 , H01L2225/06524 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01043 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10253 , H01L2924/12044 , H01L2924/1431 , H01L2924/1434 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19103 , H01L2924/19104 , H01L2924/19107 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A plurality of semiconductor devices formed on a silicon wafer which acts as a substrate of each semiconductor device, each semiconductor device comprising: a plurality of semiconductor elements (12,13) mounted on the substrate (11,31) via an adhesive layer (15) in a two-dimensional arrangement; a discrete resin layer (14) formed on said substrate and located around the associated semiconductor elements, the resin layer having substantially the same thickness as a thickness of the semiconductor elements; a discrete organic insulating layer (16) formed over a surface of the associated resin layer and circuit formation surfaces of the semiconductor elements so that edges of the organic insulating layer are located inward of the edges of the associated resin layer; a discrete rearrangement wiring layer (17) formed on the associated organic insulating layer and electrodes of said semiconductor chips so that edges of the rearrangement wiring layer are located inward of the edges of the associated organic insulating layer; and external connection terminals (18) electrically connected to the circuit formation surfaces of said semiconductor elements through wiring in the rearrangement wiring layer.
摘要翻译：多个半导体器件形成在充当每个半导体器件的衬底的硅晶片上，每个半导体器件包括：多个半导体元件（12,13），经由粘合层（15）安装在衬底（11,31）上，）以二维排列; 形成在所述衬底上并位于相关半导体元件周围的分立树脂层（14），所述树脂层具有与所述半导体元件的厚度基本相同的厚度; 形成在相关联的树脂层的表面和半导体元件的电路形成表面上的离散的有机绝缘层（16），使得有机绝缘层的边缘位于相关树脂层的边缘的内侧; 在相关有机绝缘层和所述半导体芯片的电极上形成的离散重排布线层（17），使得重排布线层的边缘位于相关有机绝缘层边缘的内侧; 和通过重排布线层中的布线电连接到所述半导体元件的电路形成表面的外部连接端子（18）。

6. 发明公开

EP2572375A2 ELECTRICAL CONNECTOR BETWEEN DIE PAD AND Z-INTERCONNECT FOR STACKED DIE ASSEMBLIES 审中-公开
标题翻译：之间的芯片焊盘和Z联网堆栈芯片装置的电连接器
公开(公告)号：EP2572375A2
公开(公告)日：2013-03-27
申请号：EP11784147.8
申请日：2011-05-18
申请人： Invensas Corporation
发明人： CO, Reynaldo , LEAL, Jeffrey, S. , PANGRLE, Suzette, K. , MCGRATH, Scott , MELCHER, DeAnn, Eileen , BARRIE, Keith, L. , VILLAVICENCIO, Grant , DEL ROSARIO, Elmer, M. , BRAY, John, R.
IPC分类号： H01L23/12 , H01L23/48
CPC分类号： H01L25/0657 , H01L21/6836 , H01L21/78 , H01L23/3171 , H01L23/3185 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/18 , H01L24/24 , H01L24/82 , H01L25/50 , H01L2221/68327 , H01L2221/68336 , H01L2224/0235 , H01L2224/02371 , H01L2224/03002 , H01L2224/03318 , H01L2224/0332 , H01L2224/03632 , H01L2224/03848 , H01L2224/05016 , H01L2224/05017 , H01L2224/0529 , H01L2224/05553 , H01L2224/24051 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/76155 , H01L2224/82102 , H01L2224/94 , H01L2225/06551 , H01L2225/06562 , H01L2225/06568 , H01L2924/01327 , H01L2924/14 , H01L2924/00 , H01L2224/03
摘要： Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

7. 发明公开

EP1158570A1 Vertical interconnect process for silicon segments 失效
标题翻译： Vertikales ZwischenverbindungsverfahrenfürSilikonsegmente
公开(公告)号：EP1158570A1
公开(公告)日：2001-11-28
申请号：EP01115235.2
申请日：1995-06-08
申请人： CUBIC MEMORY
发明人： Pedersen, David , Finley, Michael , Sautter, Kenneth
IPC分类号： H01L21/00 , H01L25/065
CPC分类号： H01L24/81 , H01L23/3737 , H01L23/4824 , H01L23/5256 , H01L23/5328 , H01L23/5382 , H01L23/5385 , H01L24/10 , H01L24/13 , H01L24/75 , H01L24/83 , H01L25/0652 , H01L25/0657 , H01L25/074 , H01L25/50 , H01L29/0657 , H01L2224/13 , H01L2224/13099 , H01L2224/16145 , H01L2224/24145 , H01L2224/2919 , H01L2224/29399 , H01L2224/32145 , H01L2224/75 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2224/92244 , H01L2225/0651 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06593 , H01L2225/06596 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0665 , H01L2924/0781 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H01R4/04 , H01R29/00 , H05K3/305 , H05K3/321 , H05K7/023 , H05K2201/09472 , H05K2201/10477 , H05K2201/10674 , H05K2201/10719 , H05K2201/10727 , Y02P70/613 , H01L2924/00 , H01L2924/3512 , H01L2224/29099
摘要： A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to all four sides of the stack. The inwardly sloping edge walls of each of the segments in the stack provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked. The stack of electrically interconnected segments is then mounted below the surface of a circuit board and electrically connected to circuits on the board by applying traces of electrically conductive epoxy between the bonding pads on the top segment of the stack and the circuit board.
摘要翻译：一种用于垂直互连硅片堆叠的方法和装置。每个部分在半导体晶片上包括多个相邻的裸片。使用一个或多个金属互连层在片段上互连多个管芯，该金属互连件延伸到段的全部四个侧面，以提供用于外部电连接点的边缘焊盘。在芯片互连后，使用斜切切割从晶片的背面切割每个片段，以在每个片段上提供四个向内倾斜的边缘壁。在从晶片切割片段之后，将片段放置在彼此的顶部以形成叠片。堆叠中的垂直相邻的段通过将导电环氧树脂施加到堆叠的所有四个侧面而电互连。堆叠中的每个段的向内倾斜的边缘壁提供凹部，其允许导电环氧树脂在片段被堆叠之后接近每个片段上的边缘接合焊盘和侧向电路。电互连段的堆叠然后安装在电路板的表面下方，并通过在堆叠的顶部段和电路板上的接合焊盘之间施加迹线的导电环氧树脂电连接到电路板上的电路。

8. 发明公开

EP0209173A1 Method of manufacturing semiconductor devices comprising the mechanical connection of two bodies 有权转让
标题翻译：一种用于通过这两个机构的机械连接的装置的生产半导体器件的过程。
公开(公告)号：EP0209173A1
公开(公告)日：1987-01-21
申请号：EP86201062.6
申请日：1986-06-18
申请人： Philips Electronics N.V.
发明人： Haisma, Jan , Michielsen, Theodorus Martinus , Pals, Jan Albertus
IPC分类号： H01L21/76 , H01L21/20
CPC分类号： H01L25/50 , H01L21/2007 , H01L21/76251 , H01L21/8221 , H01L24/24 , H01L24/26 , H01L24/82 , H01L24/83 , H01L25/0657 , H01L2224/24145 , H01L2224/8319 , H01L2224/8385 , H01L2225/06551 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01033 , H01L2924/01039 , H01L2924/01049 , H01L2924/0105 , H01L2924/01057 , H01L2924/01061 , H01L2924/01082 , H01L2924/07802 , H01L2924/10329 , H01L2924/12033 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , Y10S148/012 , H01L2224/80001 , H01L2924/00
摘要： A method for manufacturing a semiconductor device comprising at least a support body (1) and a monocrystalline semiconductor body (6, 7), in which both bodies are provided with at least one flat optically smooth surface obtained by means of bulkreducing polishing (mirror polishing) and at least the semiconductor body (6, 7) is then provided at the optically smooth surface with an electrically insulating layer (4), at least the electrically insulating layer on the semiconductor body being subjected to a bonding activating operation, whereupon both bodies (1;6,7), after their flat surfaces have been cleaned, are contacted with each other in a dust-free atmosphere in order to obtain a rigid mechanical connection, after which they are subjected to a heat treatment of at least 350 °C, whereupon the semi- conductor body (6, 7) is etched to a thin layer (7) having a predetermined value lying between 0.05 and 100 µm.

9. 发明公开

EP2835824A3 Interconnexion de plusieurs niveaux d'un empilement de supports de composants electroniques 审中-公开
标题翻译：多层互连一叠电子元件载体
公开(公告)号：EP2835824A3
公开(公告)日：2015-04-29
申请号：EP14180064.9
申请日：2014-08-06
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： Bouvier, Christophe , Pares, Gabriel
IPC分类号： H01L23/552 , H01L25/065 , H01L25/00 , H01L27/06 , H01L21/98 , H01L21/768 , H01L23/538
CPC分类号： H01L21/76838 , H01L21/76898 , H01L23/5389 , H01L23/552 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L24/92 , H01L24/96 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/04105 , H01L2224/24137 , H01L2224/24145 , H01L2224/9202 , H01L2225/06513 , H01L2225/06537 , H01L2225/06541 , H01L2225/06548 , H01L2924/12042 , H01L2924/00
摘要： Procédé de réalisation d'un dispositif microélectronique formé d'un empilement de supports (W) dotés chacun d'un ou plusieurs composants électroniques (C) et comprenant une structure conductrice (170, 470) formée d'un premier via conducteur borgne (171b, 472) et un deuxième via conducteur borgne (171a, 473) de hauteur plus importante, le premier via et le deuxième via étant connectés entre eux.
摘要翻译：用于制造由各自设置有一个或多个电子部件（C）并且包括由第一盲导体通孔（171b）形成的导电结构（170,470）的一堆支撑件（W）形成的微电子器件的方法， 472）和更高高度的第二盲孔（171a，473），第一通孔和第二通孔连接在一起。

10. 发明公开

EP2835824A2 Interconnexion de plusieurs niveaux d'un empilement de supports de composants electroniques 审中-公开
标题翻译：网络电子元器件的载体几个堆水平
公开(公告)号：EP2835824A2
公开(公告)日：2015-02-11
申请号：EP14180064.9
申请日：2014-08-06
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： Bouvier, Christophe , Pares, Gabriel
IPC分类号： H01L23/552 , H01L25/065 , H01L25/00 , H01L27/06
CPC分类号： H01L21/76838 , H01L21/76898 , H01L23/5389 , H01L23/552 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L24/92 , H01L24/96 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/04105 , H01L2224/24137 , H01L2224/24145 , H01L2224/9202 , H01L2225/06513 , H01L2225/06537 , H01L2225/06541 , H01L2225/06548 , H01L2924/12042 , H01L2924/00
摘要： Procédé de réalisation d'un dispositif microélectronique formé d'un empilement de supports (W) dotés chacun d'un ou plusieurs composants électroniques (C) et comprenant une structure conductrice (170, 470) formée d'un premier via conducteur borgne (171b, 472) et un deuxième via conducteur borgne (171a, 473) de hauteur plus importante, le premier via et le deuxième via étant connectés entre eux.

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