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1. 发明公开

EP1743369A4 MICROPEDE STACKED DIE COMPONENT ASSEMBLY 审中-公开
标题翻译： GESTAPELTE MICROPEDE-CHIPKOMPONENTENBAUGRUPPE
公开(公告)号：EP1743369A4
公开(公告)日：2008-07-09
申请号：EP05735136
申请日：2005-04-12
申请人： VERTICAL CIRCUITS INC
发明人： ROBINSON MARC , VINDASIUS AL , ALMEN DON , JACOBSEN LARRY
IPC分类号： H01L23/02 , H01L23/495 , H01L25/065
CPC分类号： H01L23/49575 , H01L25/0657 , H01L2224/24145 , H01L2225/0652 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06575 , H01L2225/06579 , H01L2924/09701 , H01L2924/3011
摘要： The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack.. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.
摘要翻译：本发明提供了一种用于垂直互连半导体管芯，集成电路管芯或多个管芯段的装置。延伸到管芯或部分的一个或多个侧面的金属重新布线互连可以可选地被添加到管芯或多管芯部分，以在管芯的表面上为外部电连接点提供边缘接合焊盘。在将金属重布线互连添加到晶片上的管芯上之后，可选地将晶片减薄并且通过切割或其他合适的分割方法将每个管芯或多个管芯分段从晶片切割下来。在将晶粒或多个晶粒片段从晶片上分离或切割之后，对晶粒或多个晶粒片段的所有表面施加绝缘，在所需电连接垫片上方的绝缘体中形成开口，并且将晶粒或多个晶粒片段放置在彼此的顶部以形成堆叠。通过将短的柔性键合线或键合带附接到裸片的外围边缘处的暴露的电连接垫，将堆叠中的垂直相邻的分段电互连，所述裸露的电连接垫从裸片水平突出以及将导电聚合物或环氧树脂，细丝或线施加到叠层的一个或多个侧面。

2. 发明公开

EP1029346A4 VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH THERMALLY CONDUCTIVE EPOXY PREFORM 审中-公开
标题翻译： VERTIKALES VERBINDUNGSPROZESSFÜRSILIZIUMSEGMENTE MIT THERMISCH-LEITENDEN EPOXYFORMTEILEN
公开(公告)号：EP1029346A4
公开(公告)日：2006-01-18
申请号：EP98943211
申请日：1998-08-14
申请人： VERTICAL CIRCUITS INC
发明人： VINDASIUS ALFONS , SAUTTER KENNETH M
IPC分类号： H01L25/18 , H01L21/98 , H01L23/373 , H01L23/52 , H01L25/065 , H01L25/07 , H01L29/06 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L25/50 , H01L23/3737 , H01L25/0657 , H01L29/0657 , H01L2224/24145 , H01L2224/2919 , H01L2224/29399 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06593 , H01L2924/01021 , H01L2924/01022 , H01L2924/01074 , H01L2924/01079 , H01L2924/14 , H01L2924/0665 , H01L2924/00
摘要： An apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack. The inwardly sloping edge walls of each of the segments in the stack provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked. A thermally conductive epoxy preform is provided between the stack of segments so that the stack of segments are epoxied together. In one embodiment, the thermally conductive epoxy preform includes a plurality of glass spheres randomly distributed within the preform to maintain a distance between the stack of segments.
摘要翻译：一种用于垂直互连硅片段的装置。每个部分在半导体晶片上包括多个相邻的裸片。使用一个或多个金属互连层在片段上互连多个管芯，该金属互连件延伸到段的全部四个侧面，以提供用于外部电连接点的边缘焊盘。在芯片互连后，使用斜切切割从晶片的背面切割每个片段，以在每个片段上提供四个向内倾斜的边缘壁。在从晶片切割片段之后，将片段放置在彼此的顶部以形成叠片。堆叠中的垂直相邻段通过将导电环氧树脂施加到堆叠的一个或多个侧面而电互连。堆叠中的每个段的向内倾斜的边缘壁提供凹部，其允许导电环氧树脂在片段被堆叠之后接近每个片段上的边缘接合焊盘和侧向电路。导热环氧树脂预成型件之间设置有一段片段，以便将一叠片段环氧化在一起。在一个实施例中，导热环氧树脂预制件包括随机分布在预成型件内的多个玻璃球，以保持片段之间的距离。

3. 发明公开

EP1743369A2 MICROPEDE STACKED DIE COMPONENT ASSEMBLY 审中-公开
标题翻译： MICROPEDE叠层模组件组件
公开(公告)号：EP1743369A2
公开(公告)日：2007-01-17
申请号：EP05735136.3
申请日：2005-04-12
申请人： Vertical Circuits, Inc.
发明人： The designation of the inventor has not yet been filed
IPC分类号： H01L23/02
CPC分类号： H01L23/49575 , H01L25/0657 , H01L2224/24145 , H01L2225/0652 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06575 , H01L2225/06579 , H01L2924/09701 , H01L2924/3011
摘要： The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack.. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.
摘要翻译：本发明提供了一种用于垂直互连半导体管芯，集成电路管芯或多个管芯段的装置。延伸到管芯或部分的一个或多个侧面的金属重新布线互连可以可选地被添加到管芯或多管芯部分，以在管芯的表面上为外部电连接点提供边缘接合焊盘。在将金属重布线互连添加到晶片上的管芯上之后，可选地将晶片减薄并且通过切割或其他合适的分割方法将每个管芯或多个管芯分段从晶片切割下来。在将晶粒或多个晶粒片段从晶片上分离或切割之后，对晶粒或多个晶粒片段的所有表面施加绝缘，在所需电连接垫片上方的绝缘体中形成开口，并且将晶粒或多个晶粒片段放置在彼此的顶部以形成堆叠。通过将短的柔性键合线或键合带附接到裸片的外围边缘处的暴露的电连接垫，将堆叠中的垂直相邻的分段电互连，所述裸露的电连接垫从裸片水平突出以及将导电聚合物或环氧树脂，细丝或线施加到叠层的一个或多个侧面。

4. 发明公开

EP1763894A2 STACKED DIE BGA OR LGA COMPONENT ASSEMBLY 审中-公开
标题翻译：堆叠模块BGA或LGA组件组件
公开(公告)号：EP1763894A2
公开(公告)日：2007-03-21
申请号：EP05736405.1
申请日：2005-04-12
申请人： Vertical Circuits, Inc.
发明人： ROBINSON, Marc , VINDASIUS, Al , ALMEN, Don , JACOBSEN, Larry
IPC分类号： H01L23/02
CPC分类号： H01L25/00 , H01L21/563 , H01L23/3128 , H01L23/34 , H01L23/525 , H01L25/0657 , H01L2224/24145 , H01L2224/73203 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06551 , H01L2225/06582 , H01L2225/06586 , H01L2924/01046 , H01L2924/01079 , H01L2924/09701 , H01L2924/15311 , H01L2924/3011
摘要： The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack.. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.
摘要翻译：本发明提供了一种用于垂直互连半导体管芯，集成电路管芯或多个管芯段的装置。延伸到管芯或部分的一个或多个侧面的金属重新布线互连可以可选地被添加到管芯或多管芯部分，以在管芯的表面上为外部电连接点提供边缘接合焊盘。在将金属重布线互连添加到晶片上的管芯上之后，可选地将晶片减薄并且通过切割或其他合适的分割方法将每个管芯或多个管芯分段从晶片切割下来。在将晶粒或多个晶粒片段从晶片上分离或切割之后，对晶粒或多个晶粒片段的所有表面施加绝缘，在所需电连接垫片上方的绝缘体中形成开口，并且将晶粒或多个晶粒片段放置在彼此的顶部以形成堆叠。通过将短的柔性键合线或键合带附接到裸片的外围边缘处的暴露的电连接垫，将堆叠中的垂直相邻的分段电互连，所述裸露的电连接垫从裸片水平突出以及将导电聚合物或环氧树脂，细丝或线施加到叠层的一个或多个侧面。

5. 发明公开

EP1743370A2 THREE DIMENSIONAL SIX SURFACE CONFORMAL DIE COATING 审中-公开
标题翻译：三六个柔软表面涂层CHIP
公开(公告)号：EP1743370A2
公开(公告)日：2007-01-17
申请号：EP05736129.7
申请日：2005-04-12
申请人： Vertical Circuits, Inc.
发明人： The designation of the inventor has not yet been filed
IPC分类号： H01L23/29
CPC分类号： H01L23/3185 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die (10). The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the to layer during wafer fabrication. The present invention describes a method for protecting and insulating (20) all six surfaces of the die (10) to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die (10) in an interconnected module or component.

6. 发明公开

EP1743370A4 THREE DIMENSIONAL SIX SURFACE CONFORMAL DIE COATING 审中-公开
标题翻译： DREIDIMENSIONALE KONFORME SECHSOBERFLÄCHEN-CHIPBESCHICHTUNG
公开(公告)号：EP1743370A4
公开(公告)日：2007-12-05
申请号：EP05736129
申请日：2005-04-12
申请人： VERTICAL CIRCUITS INC
发明人： ROBINSON MARC , VINDASIUS AL
IPC分类号： H01L23/29 , H01L23/053 , H01L23/31
CPC分类号： H01L23/3185 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die (10). The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the to layer during wafer fabrication. The present invention describes a method for protecting and insulating (20) all six surfaces of the die (10) to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die (10) in an interconnected module or component.
摘要翻译：通常将半导体裸片制造为通过光刻装置在由硅制成的半导体晶片或切片上成像的大量集成电路裸片。在制造之后，通常通过机械手段使硅晶片变薄，并且通常用金刚石锯切割晶片以切割单个管芯（10）。由此产生的单个集成电路具有六个暴露表面。裸片的顶部表面包括电路图像和在晶片制造期间已添加到层的任何钝化层。本发明描述了一种用于保护和绝缘（20）管芯（10）的全部六个表面以减少破损，为这些层提供电绝缘以及提供可用于将一个半导体管芯接合到另一半导体管芯的物理表面的方法将模具（10）堆叠在互连模块或组件中的目的。

8. 发明公开

EP1029360A4 VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH DIELECTRIC ISOLATION 审中-公开
标题翻译：过程之间的垂直连接与介电绝缘硅SEGMENTS
公开(公告)号：EP1029360A4
公开(公告)日：2006-04-12
申请号：EP98944438
申请日：1998-08-14
申请人： VERTICAL CIRCUITS INC
发明人： VINDASIUS ALFONS , SAUTTER KENNETH M
IPC分类号： H01L29/41 , H01L21/98 , H01L23/52 , H01L25/065 , H01L25/07 , H01L25/18 , H01L29/43 , H01L23/485
CPC分类号： H01L25/50 , H01L24/24 , H01L2224/24145 , H01L2224/2919 , H01L2225/06524 , H01L2225/06551 , H01L2225/06593 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/14 , H01L2924/0665 , H01L2924/00 , H01L2924/3512
摘要： An apparatus vertically interconnects stacks of silicon segments (36). Each segment (36) includes a plurality of adjacent die on a semiconductor wafer (30). The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads (42) for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls (102) on each of the segments (36). After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack. The inwardly sloping edge walls of each of the segments in the stack provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked. A dielectric coating is applied to the die to provide a conformal coating to protect and insulate the die and a laser is used to ablate the area over the bond pads to remove the dielectric coating in order to provide for electrical connections to bond pads.

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