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1. 发明公开

EP3036766A1 BUMPLESS DIE-PACKAGE INTERFACE FOR BUMPLESS BUILD-UP LAYER (BBUL) 审中-公开
标题翻译： HÖCKERLOSECHIPGEHÄUSESCHNITTSTELLEFÜRSTOSSFREIE AUFBAUSCHICHT（BBUL）
公开(公告)号：EP3036766A1
公开(公告)日：2016-06-29
申请号：EP13892033.5
申请日：2013-08-21
申请人： Intel Corporation
发明人： TEH, Weng Hong , GUZEK, John S. , SANKMAN, Robert L.
IPC分类号： H01L23/48 , H01L23/12
CPC分类号： H01L23/5389 , H01L21/563 , H01L21/568 , H01L23/49816 , H01L23/5386 , H01L24/19 , H01L24/97 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/8203 , H01L2224/82031 , H01L2225/1035 , H01L2225/1058 , H01L2924/10253 , H01L2924/1433 , H01L2924/18162
摘要： Embodiments of the present disclosure are directed towards bumpless interfaces to an embedded silicon die, in integrated circuit (IC) package assemblies. In one embodiment, a method includes forming a surrounding portion of dielectric material defining a cavity therein; placing at least one die in the cavity, the die including a contact; depositing a dielectric material on the die and the surrounding portion; etching the dielectric material to expose the contact; and depositing conductive material onto the contact. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例针对集成电路（IC）封装组件中的嵌入式硅管芯的无扰接口。在一个实施例中，一种方法包括形成在其中限定空腔的介电材料的周围部分; 将至少一个模具放置在所述空腔中，所述模具包括接触件; 在模具和周围部分上沉积电介质材料; 蚀刻介电材料以暴露接触; 并将导电材料沉积到触点上。可以描述和/或要求保护其他实施例。

2. 发明公开

EP2769412A1 MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOF 有权
标题翻译：具有堆叠微电子单位及其制备方法微电子封装
公开(公告)号：EP2769412A1
公开(公告)日：2014-08-27
申请号：EP12788344.5
申请日：2012-10-17
申请人： Invensas Corporation
发明人： CASKEY, Terrence , MOHAMMED, Ilyas
IPC分类号： H01L25/10 , H01L21/56 , H01L21/60
CPC分类号： H01L25/18 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L21/76877 , H01L23/13 , H01L23/3107 , H01L23/3114 , H01L23/3185 , H01L23/49816 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/43 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L25/117 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05124 , H01L2224/05147 , H01L2224/05548 , H01L2224/05554 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/06155 , H01L2224/12105 , H01L2224/13023 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/1329 , H01L2224/133 , H01L2224/14131 , H01L2224/27334 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48108 , H01L2224/48145 , H01L2224/4824 , H01L2224/73207 , H01L2224/73215 , H01L2224/73217 , H01L2224/73265 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/82047 , H01L2224/83005 , H01L2224/83192 , H01L2224/852 , H01L2224/92144 , H01L2224/92147 , H01L2225/06506 , H01L2225/0651 , H01L2225/06548 , H01L2225/06562 , H01L2225/06596 , H01L2225/1035 , H01L2225/1052 , H01L2225/1076 , H01L2225/1082 , H01L2924/00014 , H01L2924/0665 , H01L2924/12042 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/18162 , H01L2924/186 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2224/05552
摘要： A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.
摘要翻译：一种微电子封装可包括第一微电子单元包括具有第一芯片触点的半导体芯片，封装剂在所述半导体芯片的边缘接触，以及第一单元在接触所述密封剂的表面露出，并与第一芯片触点电连接。该包装可包括第二微电子单元包括具有在其表面处的第二芯片触点的半导体芯片，和密封剂的接触在所述第二单元的所述芯片的边缘，并具有一个表面延伸远离边缘。所述芯片和所述第二单元的密封剂的表面限定的面中的第二单元。在面部封装端子可以是具有通过与第一单元触点电连接的键合引线的第一部接触，并通过与第二芯片触点接触而形成金属化通孔和迹线的第二芯片触点电连接。

4. 发明公开

EP2854168A2 Embedded semiconductor device package and method of manufacturing thereof 审中-公开
标题翻译： EingebettetesHalbleitervorrichtungsgehäuseund Verfahren zur Herstellung davon
公开(公告)号：EP2854168A2
公开(公告)日：2015-04-01
申请号：EP14184831.7
申请日：2014-09-15
申请人： General Electric Company
发明人： Chauhan, Shakti Singh , McConnelee, Paul Alan , Gowda, Arun Virupaksha
IPC分类号： H01L23/00 , H01L23/538 , H05K1/18
CPC分类号： H01L23/5389 , H01L23/34 , H01L23/367 , H01L23/3677 , H01L23/3736 , H01L23/42 , H01L23/433 , H01L23/5226 , H01L23/528 , H01L23/53228 , H01L23/53295 , H01L23/5384 , H01L23/5386 , H01L24/24 , H01L24/25 , H01L24/26 , H01L24/32 , H01L24/82 , H01L2224/04105 , H01L2224/12105 , H01L2224/2402 , H01L2224/24137 , H01L2224/24195 , H01L2224/24225 , H01L2224/2518 , H01L2224/2732 , H01L2224/27416 , H01L2224/291 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/8201 , H01L2224/82031 , H01L2224/82039 , H01L2224/82047 , H01L2224/82101 , H01L2224/83005 , H01L2224/83132 , H01L2224/83192 , H01L2224/83855 , H01L2224/92144 , H01L2924/1203 , H01L2924/12042 , H01L2924/13091 , H01L2924/1433 , H01L2924/15747 , H01L2924/15787 , H01L2924/181 , H05K1/0266 , H05K1/185 , H05K3/305 , H05K3/4602 , H05K3/4605 , H05K3/4688 , H05K2201/0187 , H05K2203/0278 , H05K2203/063 , H05K2203/166 , H01L2924/014 , H01L2924/00
摘要： A package structure (10) includes a dielectric layer (14), at least one semiconductor device (12) attached to the dielectric layer (14), one or more dielectric sheets (26) applied to the dielectric layer (14) and about the semiconductor device(s) (12) to embed the semiconductor device(s) (12) therein, and a plurality of vias (30,36) formed to the semiconductor device(s) (12) that are formed in at least one of the dielectric layer (14) and the one or more dielectric sheets (26). The package structure (10) also includes metal interconnects (38) formed in the vias (30,36) and on one or more outward facing surfaces (18,20) of the package structure (10) to form electrical interconnections to the semiconductor device(s) (12). The dielectric layer (14) is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets (26) is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s) (12).
摘要翻译：封装结构（10）包括电介质层（14），附着到电介质层（14）的至少一个半导体器件（12），施加到电介质层（14）上的一个或多个电介质片（26）将半导体器件（12）嵌入其中的半导体器件（12）和形成在半导体器件（12）上的多个通孔（30,36），其形成在至少一个电介质层（14）和一个或多个电介质片（26）。封装结构（10）还包括形成在通孔（30,36）中的金属互连（38）和封装结构（10）的一个或多个向外表面（18,20）上，以形成与半导体器件（12）。电介质层（14）由在层压工艺期间不流动的材料构成，并且所述一个或多个电介质片（26）中的每一个由可在层压过程中固化时被熔化和流动的可固化材料构成，以便以填充半导体器件（12）周围的任何气隙。

5. 发明公开

EP3036766A4 BUMPLESS DIE-PACKAGE INTERFACE FOR BUMPLESS BUILD-UP LAYER (BBUL) 审中-公开
标题翻译： HÖCKERLOSECHIPGEHÄESESCHNITTSTELLEFÜRSTOSSFREIE AUFBAUSCHICHT（BBUL）
公开(公告)号：EP3036766A4
公开(公告)日：2017-09-06
申请号：EP13892033
申请日：2013-08-21
申请人： INTEL CORP
发明人： TEH WENG HONG , GUZEK JOHN S , SANKMAN ROBERT L
IPC分类号： H01L23/48 , H01L21/56 , H01L21/60 , H01L23/12 , H01L23/498 , H01L23/538 , H01L25/10
CPC分类号： H01L23/5389 , H01L21/563 , H01L21/568 , H01L23/49816 , H01L23/5386 , H01L24/19 , H01L24/97 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/8203 , H01L2224/82031 , H01L2225/1035 , H01L2225/1058 , H01L2924/10253 , H01L2924/1433 , H01L2924/18162

6. 发明公开

EP2648215A3 Method and apparatus providing integrated circuit system with interconnected stacked device wafers 审中-公开
标题翻译：用于提供集成电路系统与相关设备堆叠的晶片的方法和装置
公开(公告)号：EP2648215A3
公开(公告)日：2017-01-18
申请号：EP13161771.4
申请日：2013-03-28
申请人： OmniVision Technologies, Inc.
发明人： Qian, Yin , Tai, Hsin-Chih , Mao, Duli , Dai, Tiejun , Rhodes, Howard E. , Yang, Hongli
IPC分类号： H01L23/00 , H01L21/768 , H01L23/48 , H01L25/065 , H01L21/60 , H01L27/146
CPC分类号： H01L24/80 , H01L21/76898 , H01L23/481 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L27/14634 , H01L2224/04042 , H01L2224/05567 , H01L2224/05571 , H01L2224/08145 , H01L2224/2401 , H01L2224/24105 , H01L2224/24147 , H01L2224/48151 , H01L2224/73251 , H01L2224/80357 , H01L2224/80896 , H01L2224/80986 , H01L2224/82031 , H01L2224/82106 , H01L2224/9202 , H01L2224/94 , H01L2225/06544 , H01L2924/00014 , H01L2924/14 , H01L2924/1433 , H01L2924/3511 , H01L2224/80001 , H01L2924/00012 , H01L2224/05552
摘要： An integrated circuit system includes a first device wafer that has a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer that has a second semiconductor layer proximate to a second metal layer including a second conductor disposed within a second metal layer oxide is also included. A frontside of the first metal layer oxide is bonded to a frontside of the second metal layer oxide at an oxide bonding interface between the first metal layer oxide and the second metal layer oxide. A conductive path couples the first conductor to the second conductor with conductive material formed in a cavity etched between the first conductor and the second conductor and etched through the oxide bonding interface and through the second semiconductor layer from a backside of the second device wafer.

7. 发明公开

EP3029719A1 ELECTRONIC PACKAGES AND METHODS OF MAKING AND USING THE SAME 审中-公开
标题翻译： ELEKTRONISCHE VERPACKUNGEN UND VERFAHREN ZUR HERSTELLUNG UND VERWENDUNG DAVON
公开(公告)号：EP3029719A1
公开(公告)日：2016-06-08
申请号：EP15195705.7
申请日：2015-11-20
申请人： General Electric Company
发明人： SMITH, Scott , KAPUSTA, Christopher James , FORMAN, Glenn Alan , DAVIS, Eric Patrick
IPC分类号： H01L21/60 , H01L21/66
CPC分类号： H01L23/49827 , H01L21/2885 , H01L21/486 , H01L22/12 , H01L22/14 , H01L22/22 , H01L23/49838 , H01L24/24 , H01L24/29 , H01L24/82 , H01L24/83 , H01L24/97 , H01L25/0655 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/2919 , H01L2224/32225 , H01L2224/82031 , H01L2224/82039 , H01L2224/82047 , H01L2224/82106 , H01L2224/82138 , H01L2224/83129 , H01L2224/8314 , H01L2224/83192 , H01L2224/92144 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/14 , H01L2924/1433 , H01L2924/15724 , H01L2924/15738 , H01L2924/15747 , H01L2924/15763 , H01L2924/3025 , H01L2224/83 , H01L2224/82
摘要： An electronic package and a method of making the same in provided. The electronic package includes a dielectric layer (102) and a conformal masking layer (112) disposed on at least a portion of the dielectric layer (102). The electronic package further includes a routing layer (136) disposed on at least a portion of the combined masking layer (112) and a micro-via (122) disposed at least in part in the conformal masking layer (112) and the routing layer (136). Further, at least a portion of the routing layer (136) forms a conformal electrically conductive layer (130) in at least a portion of the micro-via (122). Also, the conformal masking layer (112) is configured to define a size of the micro-via (122). The electronic package further includes a semiconductor die (118) operatively coupled to the micro-via (122).
摘要翻译：一种电子封装及其制作方法。电子封装包括设置在电介质层（102）的至少一部分上的电介质层（102）和保形掩模层（112）。电子封装还包括设置在组合掩模层（112）的至少一部分上的布线层（136）和至少部分地设置在保形掩模层（112）中的微通孔（122）和布线层（136）。此外，路由层（136）的至少一部分在微通孔（122）的至少一部分中形成共形导电层（130）。此外，共形掩模层（112）被配置为限定微通孔（122）的尺寸。电子封装还包括可操作地耦合到微通孔（122）的半导体管芯（118）。

8. 发明公开

EP2881985A1 Embedded package structure and method for manufacturing thereof 审中-公开
标题翻译： Eingebettete Verpackungsstruktur und Verfahren zur Herstellung davon
公开(公告)号：EP2881985A1
公开(公告)日：2015-06-10
申请号：EP14197415.4
申请日：2013-09-09
申请人： Delta Electronics, Inc.
发明人： Lee, Chia-Yen , Tsai, Hsin-Chang , Lee, Peng-Hsin
IPC分类号： H01L23/492 , H01L23/538
CPC分类号： H01L24/85 , H01L23/492 , H01L23/49894 , H01L23/5389 , H01L24/06 , H01L24/16 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/82 , H01L2224/0401 , H01L2224/06181 , H01L2224/16245 , H01L2224/24137 , H01L2224/291 , H01L2224/2919 , H01L2224/32145 , H01L2224/32245 , H01L2224/73253 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/82101 , H01L2224/85 , H01L2224/92244 , H01L2924/00014 , H01L2924/12042 , H01L2924/014 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： The disclosure provides an embedded package structure comprising a metal substrate (210a), a chip module (220a), an insulation material layer (230a), and at least one patterned metal layer (240a). The metal substrate (210a) has a first surface (211a) and a second surface (212a). The chip module (220a) is disposed on the first surface of the metal substrate, and comprises at least two stacked chips (222a,221a) being electrically connected to each. A adhesive layer or a solder (260a) is positioned between the stacked chips. The insulation material layer (230a) covers the first surface of the metal substrate and the stacked chips and has an electrical interconnection (231a) formed therein. The patterned metal layer (240a) is positioned on the insulation material layer, and is electrically connected the chip module through the electrical interconnection. The method for manufacturing the embedded package structure also provides.
摘要翻译：本公开提供了一种嵌入式封装结构，其包括金属基板（210a），芯片模块（220a），绝缘材料层（230a）和至少一个图案化金属层（240a）。金属基板（210a）具有第一表面（211a）和第二表面（212a）。芯片模块（220a）设置在金属基板的第一表面上，并且包括至少两个彼此电连接的堆叠的芯片（222a，221a）。粘合剂层或焊料（260a）位于堆叠的芯片之间。绝缘材料层（230a）覆盖金属基板的第一表面和堆叠的芯片，并且其中形成有电互连（231a）。图案化的金属层（240a）位于绝缘材料层上，并且通过电互连电连接芯片模块。嵌入式封装结构的制造方法也提供了。

9. 发明公开

EP2648215A2 Method and apparatus providing integrated circuit system with interconnected stacked device wafers 审中-公开
标题翻译：用于提供集成电路系统与相关设备堆叠的晶片的方法和装置
公开(公告)号：EP2648215A2
公开(公告)日：2013-10-09
申请号：EP13161771.4
申请日：2013-03-28
申请人： OmniVision Technologies, Inc.
发明人： Qian, Yin , Tai, Hsin-Chih , Mao, Duli , Dai, Tiejun , Rhodes, Howard E. , Yang, Hongli
IPC分类号： H01L23/00 , H01L21/768 , H01L23/48 , H01L25/065
CPC分类号： H01L24/80 , H01L21/76898 , H01L23/481 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L27/14634 , H01L2224/04042 , H01L2224/05567 , H01L2224/05571 , H01L2224/08145 , H01L2224/2401 , H01L2224/24105 , H01L2224/24147 , H01L2224/48151 , H01L2224/73251 , H01L2224/80357 , H01L2224/80896 , H01L2224/80986 , H01L2224/82031 , H01L2224/82106 , H01L2224/9202 , H01L2224/94 , H01L2225/06544 , H01L2924/00014 , H01L2924/14 , H01L2924/1433 , H01L2924/3511 , H01L2224/80001 , H01L2924/00012 , H01L2224/05552
摘要： An integrated circuit system includes a first device wafer that has a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer that has a second semiconductor layer proximate to a second metal layer including a second conductor disposed within a second metal layer oxide is also included. A frontside of the first metal layer oxide is bonded to a frontside of the second metal layer oxide at an oxide bonding interface between the first metal layer oxide and the second metal layer oxide. A conductive path couples the first conductor to the second conductor with conductive material formed in a cavity etched between the first conductor and the second conductor and etched through the oxide bonding interface and through the second semiconductor layer from a backside of the second device wafer.
摘要翻译：一种集成电路系统，包括第一器件晶片做具有第一半导体层紧邻的第一金属层包括第一金属氧化物层内设置的第一导体。第二器件晶片做具有第二半导体层邻近第二金属层包括第二金属层氧化物内布置的第二导体因此包含。所述第一金属氧化物层的前侧上在所述第一金属层氧化物和第二金属氧化物层之间的氧化物键合界面接合到第二金属层的氧化物的前侧。的导电路径连接第一导体与在从所述第二设备晶片的背面的第一导体和所述第二导体和蚀刻之间蚀刻穿过氧化物键合界面，并通过所述第二半导体层的腔形成的导电材料的第二导体。

10. 发明公开

EP2903021A1 Semiconductor device, semiconductor stacked module structure, stacked module structure and method of manufacturing same 审中-公开
标题翻译：半导体器件中，半导体层叠结构模块，用于生产层状模块结构及其制程
公开(公告)号：EP2903021A1
公开(公告)日：2015-08-05
申请号：EP14153041.0
申请日：2014-01-29
申请人： J-Devices Corporation
发明人： Inoue, Hiroshi , Katsumata, Akio , Sawachi, Shigenori , Yamagata, Osamu
IPC分类号： H01L23/00 , H01L25/10
CPC分类号： H01L24/19 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L24/97 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/92244 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2924/12042 , H01L2924/15311 , H01L2224/83 , H01L2224/82 , H01L2924/014 , H01L2924/00
摘要： A semiconductor device (100), having an insulating substrate (102); a semiconductor element (101) which is mounted on one main surface of the insulating substrate via adhesive (103), with an element circuit surface of the semiconductor element facing upwards; a first insulating material layer (104a) which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto; a first metal thin film wire layer (105) which is provided on the first insulating material layer (104a) and a portion of which is exposed to an external surface; a first insulating material layer (104b) which is provided on the first metal thin film wire layer (105); a second insulating material layer (107) which is provided on a main surface of the insulating substrate (102) where the semiconductor element is not mounted; a second metal thin film wire layer (106) which is provided inside the second insulating material layer and a portion of which is exposed to an external surface; a via (108) which passes through the insulating substrate and which electrically connects the first metal thin film wire layer (105) in the first insulating material layer (104a) and the second metal thin film wire layer (106); and an external electrode (109) which is formed on the first metal thin film wire layer (105), the semiconductor device having a structure in which the second metal thin film wire layer, an electrode arranged on the element circuit surface of the semiconductor element, the first metal thin film wire layer, the via and the external electrode formed on the first metal thin film wire layer are electrically connected.
摘要翻译：一种半导体装置（100），具有对绝缘衬底（102）; 其经由粘合剂（103）安装在所述绝缘基片的一个主表面，与面向上的半导体元件的元件电路表面上的半导体元件（101）的所有; 密封该半导体元件的元件电路表面和外周在其上的绝缘基板的第一绝缘材料层（104A）; 其上设置有第一绝缘材料层（104A）和所有的暴露于外部表面上的一部分上的第1金属薄膜层金属线（105）的所有; 其设置在所述第一金属薄膜层金属线（105）的第一绝缘材料层（104B）; 其设置在其中的半导体元件没有被安装在绝缘基板（102）的主表面上的第二绝缘材料层（107）的所有; 该第二绝缘材料层和所有的暴露于外部表面上的部分的内侧设置的第二金属薄膜层金属线（106）的所有; 通孔（108），通过绝缘基板和通过其电连接在所述第一绝缘材料层中的第一金属薄膜层金属线（105）（104A）和所述第二金属薄膜层金属线（106）; 和所有其在第1金属薄膜布线层（105）上形成了外部电极（109），具有在上电极上的第2金属薄膜布线层的半导体元件的元件电路表面上排列的结构的半导体器件中，第一金属薄膜层金属线，通孔和形成在所述第1金属薄膜层导线与外部电极电连接。

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