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1. 发明授权

US06110793A Method for making a trench isolation having a conformal liner oxide and top and bottom rounded corners for integrated circuits 失效
标题翻译：用于制造具有保形衬垫氧化物的沟槽隔离和用于集成电路的顶部和底部圆角的方法
公开(公告)号：US06110793A
公开(公告)日：2000-08-29
申请号：US104033
申请日：1998-06-24
申请人： Kuei-Ying Lee , Kong-Beng Thei , Bou-Fun Chen
发明人： Kuei-Ying Lee , Kong-Beng Thei , Bou-Fun Chen
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76235
摘要： A method for forming an improved trench isolation having a conformal liner oxide and rounded top and bottom corners in the trench was achieved. The conformal liner oxide improves the CVD gap-filling capabilities for these deep submicron wide trenches, and the rounded corners improve the electrical characteristics of the devices in the adjacent device areas. After etching trenches with vertical sidewalls in the silicon substrate, a two-step oxidation process is used to form the conformal liner oxide. A first oxidation step using a low-oxygen flow rate and a low temperature (about 850 to 920.degree. C.) is used to achieve rounded bottom corners. A second oxidation step at a low-oxygen flow rate and a higher temperature (about 1000 to 1150.degree. C.) is used to achieve rounded top corners. The two-step process also results in a more conformal liner oxide. The trenches are then filled with a CVD oxide and polished or etched back to an oxidation-barrier layer/etch-stop layer over the device areas to complete the trench isolation.
摘要翻译：实现了在沟槽中形成具有共形衬垫氧化物和圆形顶部和底部角的改进的沟槽隔离的方法。保形衬垫氧化物改善了这些深亚微米宽沟槽的CVD间隙填充能力，并且圆角提高了相邻器件区域中器件的电气特性。在硅衬底中用垂直侧壁蚀刻沟槽之后，使用两步氧化工艺来形成保形衬里氧化物。使用低氧气流速度和低温（约850-920℃）的第一氧化步骤来实现圆角的底角。使用低氧流速和较高温度（约1000至1150℃）的第二氧化步骤来实现圆角顶角。两步法也导致更适形的衬里氧化物。然后用CVD氧化物填充沟槽并在器件区域上抛光或蚀刻回到氧化阻挡层/蚀刻停止层以完成沟槽隔离。

2. 发明授权

US06350662B1 Method to reduce defects in shallow trench isolations by post liner anneal 有权
标题翻译：通过后衬板退火来减少浅沟槽隔离缺陷的方法
公开(公告)号：US06350662B1
公开(公告)日：2002-02-26
申请号：US09357244
申请日：1999-07-19
申请人： Kong-Beng Thei , Kuei-Ying Lee , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： Kong-Beng Thei , Kuei-Ying Lee , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method to form shallow trench isolations with reduced substrate defects by using a nitrogen anneal is achieved. A silicon substrate is provided. The silicon substrate is etched where not protected by a photoresist mask to form shallow trenches where shallow trench isolations are planned. A liner oxide layer is grown on the interior surfaces of the shallow trenches. The silicon substrate and the liner oxide layer are annealed to reduce or eliminate defects, dislocations, interface traps, and stress in the silicon substrate. An isolation oxide layer is deposited overlying the liner oxide layer and completely filling the shallow trenches. The isolation oxide layer is etched down to the top surface of the silicon substrate and thereby forms the shallow trench isolations. The integrated circuit device is completed.
摘要翻译：实现了通过使用氮退火形成具有减少的衬底缺陷的浅沟槽隔离的方法。提供硅衬底。蚀刻硅衬底，其中未被光致抗蚀剂掩模保护以形成浅沟槽，其中规划浅沟槽隔离。在浅沟槽的内表面上生长衬里氧化物层。对硅衬底和衬里氧化物层进行退火以减少或消除硅衬底中的缺陷，位错，界面陷阱和应力。隔离氧化物层沉积在衬垫氧化物层上并且完全填充浅沟槽。隔离氧化物层被蚀刻到硅衬底的顶表面，从而形成浅沟槽隔离。集成电路装置完成。

3. 发明授权

US06214698B1 Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer 有权
标题翻译：采用间隙填充掺杂氧化硅介质层的浅沟槽隔离方法
公开(公告)号：US06214698B1
公开(公告)日：2001-04-10
申请号：US09480270
申请日：2000-01-11
申请人： Jhon-Jhy Liaw , Jin-Yuan Lee , Kuei-Ying Lee , Chu-Yun Fu , Kong-Beng Thei
发明人： Jhon-Jhy Liaw , Jin-Yuan Lee , Kuei-Ying Lee , Chu-Yun Fu , Kong-Beng Thei
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method for filling a trench within a substrate. First a substrate is provided having a trench formed therein. The trench has a bottom surface and opposing side walls. An undoped silicon glass liner is then thermally grown to coat the bottom surface and side walls of the trench. An undoped silicon oxide layer is then deposited over the undoped silicon glass liner. A boron doped silicon oxide layer is then deposited over the undoped silicon oxide layer, filling the trench. The boron doped silicon oxide layer is then heated to reflow the boron doped silicon oxide to fill any void initially formed within the boron doped silicon oxide layer within the trench, thereby eliminating any void so formed.
摘要翻译：一种填充衬底内的沟槽的方法。首先，提供具有形成在其中的沟槽的衬底。沟槽具有底面和相对的侧壁。然后将未掺杂的硅玻璃衬里热生长以涂覆沟槽的底表面和侧壁。然后将未掺杂的氧化硅层沉积在未掺杂的硅玻璃衬垫上。然后将硼掺杂的氧化硅层沉积在未掺杂的氧化硅层上，填充沟槽。然后加热硼掺杂的氧化硅层以回流硼掺杂的氧化硅以填充初始形成在沟槽内的硼掺杂的氧化硅层内的任何空隙，从而消除如此形成的任何空隙。

4. 发明授权

US09099556B2 Transistor having an active region with wing structure 有权
标题翻译：晶体管具有机翼结构的有源区域
公开(公告)号：US09099556B2
公开(公告)日：2015-08-04
申请号：US13213409
申请日：2011-08-19
申请人： Chen-Liang Chu , Fei-Yuh Chen , Yi-Sheng Chen , Shih-Kuang Hsiao , Chun Lin Tsai , Kong-Beng Thei
发明人： Chen-Liang Chu , Fei-Yuh Chen , Yi-Sheng Chen , Shih-Kuang Hsiao , Chun Lin Tsai , Kong-Beng Thei
IPC分类号： H01L29/76 , H01L29/78 , H01L29/10 , H01L29/06
CPC分类号： H01L29/41775 , H01L29/0653 , H01L29/0692 , H01L29/1033 , H01L29/1045 , H01L29/78 , H01L29/7823 , H01L29/7835
摘要： A semiconductor device includes an active region having a channel region and at least a wing region adjoining the channel region under the gate dielectric layer. The at least one wing region may be two symmetrical wing regions across the channel region.
摘要翻译：半导体器件包括具有通道区域的有源区域和与栅极介电层下方的沟道区域邻接的至少一个翼区域。所述至少一个机翼区域可以是穿过所述通道区域的两个对称翼区域。

5. 发明授权

US09054025B2 Process for controlling shallow trench isolation step height 有权
标题翻译：控制浅沟槽隔离台阶高度的工艺
公开(公告)号：US09054025B2
公开(公告)日：2015-06-09
申请号：US12478135
申请日：2009-06-04
申请人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen , Shun-Jang Liao
发明人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen , Shun-Jang Liao
IPC分类号： H01L21/66 , H01L21/762
CPC分类号： H01L22/20 , H01L21/76224 , H01L22/12
摘要： A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time.
摘要翻译：公开了一种用于制造隔离区的台阶高度之间的均匀性提高的集成电路的方法。该方法包括提供具有一个或多个沟槽的衬底; 填充一个或多个沟槽; 在所述一个或多个填充的沟槽上执行化学机械抛光，其中所述一个或多个填充的沟槽中的每一个包括厚度; 测量所述一个或多个填充沟槽中的每一个的厚度; 基于所测量的一个或多个填充的沟槽中的每一个的厚度来确定进行蚀刻处理的时间量; 并对所确定的时间量进行蚀刻处理。

6. 发明申请

US20120270379A1 METHOD OF FABRICATING A DUMMY GATE STRUCTURE IN A GATE LAST PROCESS 有权
标题翻译：在门窗最后过程中制造多孔门结构的方法
公开(公告)号：US20120270379A1
公开(公告)日：2012-10-25
申请号：US13538220
申请日：2012-06-29
申请人： Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人： Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要： A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.
摘要翻译：一种半导体器件制造方法，包括在衬底的第一部分中形成多个栅极结构，其中所述多个栅极结构具有第一高度。第一金属栅极结构形成在衬底的第二部分中，第一金属栅极结构被隔离区包围。在基板的第二部分中形成多个虚拟栅极结构。多个虚拟栅极结构被构造成围绕金属栅极结构和隔离区域的环形结构。多个虚拟结构具有与多个栅极结构基本平面的顶表面，并且覆盖基板的第二部分的图案密度的至少5％。

7. 发明申请

US20120146057A1 METHOD OF FABRICATING SPACERS IN A STRAINED SEMICONDUCTOR DEVICE 有权
标题翻译：在应变半导体器件中制作间隔物的方法
公开(公告)号：US20120146057A1
公开(公告)日：2012-06-14
申请号：US13399394
申请日：2012-02-17
申请人： Chen-Pin Hsu , Kong-Beng Thei , Harry Chuang
发明人： Chen-Pin Hsu , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L29/78 , H01L29/24
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823864 , H01L29/0847 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.
摘要翻译：本公开提供了一种制造半导体器件的方法，该方法包括在硅衬底上形成栅极叠层，在栅极叠层的侧壁上形成虚设间隔物，各向同性地蚀刻硅衬底以在栅叠层的任一侧上形成凹陷区，形成在所述凹部区域中的半导体材料，所述半导体材料与所述硅衬底不同，去除所述虚设衬垫，在所述栅极堆叠和所述半导体材料上形成具有氧化物 - 氮化物 - 氧化物构造的间隔层，并蚀刻所述间隔层以形成栅极叠层的侧壁上的栅极间隔物。

8. 发明授权

US08174091B2 Fuse structure 有权
标题翻译：保险丝结构
公开(公告)号：US08174091B2
公开(公告)日：2012-05-08
申请号：US12503641
申请日：2009-07-15
申请人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
发明人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.
摘要翻译：提出了电熔丝及其形成方法。在基材上形成第一层导电线。在第一层导电线上形成通孔。通孔优选包括阻挡层和导电材料。在通孔上形成第二层导电线。第一外部焊盘形成为耦合到第一层导电线。第二外部焊盘形成为耦合到第二层导电线。通孔，第一导线和第二导线适于作为电熔丝。电熔丝可以通过施加电流而烧坏。优选实施例的垂直结构适合于形成任何层。

9. 发明授权

US08153498B2 Downsize polysilicon height for polysilicon resistor integration of replacement gate process 有权
标题翻译：多晶硅电阻尺寸缩小，替代栅极工艺集成
公开(公告)号：US08153498B2
公开(公告)日：2012-04-10
申请号：US12401876
申请日：2009-03-11
申请人： Chen-Pin Hsu , Chung-Long Cheng , Kong-Beng Thei , Harry Chuang
发明人： Chen-Pin Hsu , Chung-Long Cheng , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/8232
CPC分类号： H01L27/0629 , H01L21/82345 , H01L27/088 , H01L29/66545 , Y10S438/926
摘要： A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure.
摘要翻译：公开了一种用于制造在栅极替换处理中保护电阻结构的半导体器件的半导体器件和方法。该方法包括提供半导体衬底; 在半导体衬底上形成包括虚拟栅极的至少一个栅极结构; 在半导体衬底上形成包括栅极的至少一个电阻结构; 暴露所述至少一个电阻结构的栅极的一部分; 在所述半导体衬底上形成蚀刻停止层，包括在所述栅极的暴露部分上方; 从所述至少一个门结构移除所述伪栅极以产生开口; 以及在所述至少一个栅极结构的开口中形成金属栅极。

10. 发明授权

US08093120B2 Integrating a first contact structure in a gate last process 有权
标题翻译：在最后一个进程中集成第一个接触结构
公开(公告)号：US08093120B2
公开(公告)日：2012-01-10
申请号：US12839994
申请日：2010-07-20
申请人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/8238
CPC分类号： H01L29/66606 , H01L21/823814 , H01L21/823871
摘要： A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.
摘要翻译：提供了一种提供基板的方法，在衬底中形成晶体管，晶体管具有虚拟栅极; 在衬底和晶体管上形成介电层; 在介电层中形成接触特征; 并且在形成接触特征之后，用金属栅极替换晶体管的虚拟栅极。示例性接触特征是双重接触。

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