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1. 发明申请

US20090273055A1 Fuse Structure 有权
标题翻译：保险丝结构
公开(公告)号：US20090273055A1
公开(公告)日：2009-11-05
申请号：US12503641
申请日：2009-07-15
申请人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
发明人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.
摘要翻译：提出了电熔丝及其形成方法。在基材上形成第一层导电线。在第一层导电线上形成通孔。通孔优选包括阻挡层和导电材料。在通孔上形成第二层导电线。第一外部焊盘形成为耦合到第一层导电线。第二外部焊盘形成为耦合到第二层导电线。通孔，第一导线和第二导线适于作为电熔丝。电熔丝可以通过施加电流而烧坏。优选实施例的垂直结构适合于形成任何层。

2. 发明授权

US08174091B2 Fuse structure 有权
标题翻译：保险丝结构
公开(公告)号：US08174091B2
公开(公告)日：2012-05-08
申请号：US12503641
申请日：2009-07-15
申请人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
发明人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.
摘要翻译：提出了电熔丝及其形成方法。在基材上形成第一层导电线。在第一层导电线上形成通孔。通孔优选包括阻挡层和导电材料。在通孔上形成第二层导电线。第一外部焊盘形成为耦合到第一层导电线。第二外部焊盘形成为耦合到第二层导电线。通孔，第一导线和第二导线适于作为电熔丝。电熔丝可以通过施加电流而烧坏。优选实施例的垂直结构适合于形成任何层。

3. 发明申请

US20120196434A1 E-fuse Structure Design in Electrical Programmable Redundancy for Embedded Memory Circuit 有权
标题翻译：嵌入式存储器电路的电可编程冗余中的电熔丝结构设计
公开(公告)号：US20120196434A1
公开(公告)日：2012-08-02
申请号：US13443550
申请日：2012-04-10
申请人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
发明人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
IPC分类号： H01L21/02
CPC分类号： H01L23/5256 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.
摘要翻译：提出了电熔丝及其形成方法。在基材上形成第一层导电线。在第一层导电线上形成通孔。通孔优选包括阻挡层和导电材料。在通孔上形成第二层导电线。第一外部焊盘形成为耦合到第一层导电线。第二外部焊盘形成为耦合到第二层导电线。通孔，第一导线和第二导线适于作为电熔丝。电熔丝可以通过施加电流而烧坏。优选实施例的垂直结构适合于形成任何层。

4. 发明授权

US08629050B2 E-fuse structure design in electrical programmable redundancy for embedded memory circuit 有权
标题翻译：用于嵌入式存储器电路的电可编程冗余中的电熔丝结构设计
公开(公告)号：US08629050B2
公开(公告)日：2014-01-14
申请号：US13443550
申请日：2012-04-10
申请人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry-Hak-Lay Chuang , Shien-Yang Wu , Shi-Bai Chen
发明人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry-Hak-Lay Chuang , Shien-Yang Wu , Shi-Bai Chen
IPC分类号： H01L21/02
CPC分类号： H01L23/5256 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.
摘要翻译：提出了电熔丝及其形成方法。在基材上形成第一层导电线。在第一层导电线上形成通孔。通孔优选包括阻挡层和导电材料。在通孔上形成第二层导电线。第一外部焊盘形成为耦合到第一层导电线。第二外部焊盘形成为耦合到第二层导电线。通孔，第一导线和第二导线适于作为电熔丝。电熔丝可以通过施加电流而烧坏。优选实施例的垂直结构适合于形成任何层。

5. 发明申请

US20050285222A1 New fuse structure 审中-公开
标题翻译：新的保险丝结构
公开(公告)号：US20050285222A1
公开(公告)日：2005-12-29
申请号：US11137075
申请日：2005-05-25
申请人： Kong-Beng Thei , Chung Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
发明人： Kong-Beng Thei , Chung Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
IPC分类号： H01L23/525 , H01L23/532 , H01L29/00
CPC分类号： H01L23/5256 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.
摘要翻译：提出了电熔丝及其形成方法。在基材上形成第一层导电线。在第一层导电线上形成通孔。通孔优选包括阻挡层和导电材料。在通孔上形成第二层导电线。第一外部焊盘形成为耦合到第一层导电线。第二外部焊盘形成为耦合到第二层导电线。通孔，第一导线和第二导线适于作为电熔丝。电熔丝可以通过施加电流而烧坏。优选实施例的垂直结构适合于形成任何层。

6. 发明申请

US20060163734A1 Fuse structure and method for making the same 审中-公开
标题翻译：保险丝结构及制作方法
公开(公告)号：US20060163734A1
公开(公告)日：2006-07-27
申请号：US11041585
申请日：2005-01-24
申请人： Kong-Beng Thei , Chung-Long Cheng , Chung-Shi Liu , Harry Chuang
发明人： Kong-Beng Thei , Chung-Long Cheng , Chung-Shi Liu , Harry Chuang
IPC分类号： H01L23/48
CPC分类号： H01L23/5258 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Provided are a fuse structure and a method for manufacturing the fuse structure. In one example, the method includes providing a multilayer interconnect structure (MLI) over a semiconductor substrate. The MLI includes multiple fuse connection and bonding connection features. A passivation layer is formed over the MLI and patterned to form openings, with each opening being aligned with one of the fuse connection or bonding connection features. A conductive layer is formed on the passivation layer and in the openings. The conductive layer is patterned to form bonding features and fuse structures. Each bonding feature is in contact with one of the bonding connection features, and each fuse structure is in contact with two of the fuse connection features. A cap dielectric layer is formed over the fuse structures and patterned to expose at least one of the bonding features while leaving the fuse structures covered.
摘要翻译：提供了一种熔丝结构和用于制造熔丝结构的方法。在一个示例中，该方法包括在半导体衬底上提供多层互连结构（MLI）。 MLI包括多个保险丝连接和接合连接功能。钝化层形成在MLI上方并被图案化以形成开口，其中每个开口与保险丝连接或接合连接特征中的一个对准。在钝化层和开口中形成导电层。将导电层图案化以形成结合特征和熔丝结构。每个接合特征与接合连接特征之一接触，并且每个熔断器结构与两个熔断器连接特征接触。在熔丝结构之上形成盖电介质层，并将其图案化以暴露粘合特征中的至少一个，同时保留熔丝结构。

7. 发明授权

US09765289B2 Cleaning methods and compositions 有权
公开(公告)号：US09765289B2
公开(公告)日：2017-09-19
申请号：US13598272
申请日：2012-08-29
申请人： Hui-Jung Tsai , Hung-Jui Kuo , Chung-Shi Liu
发明人： Hui-Jung Tsai , Hung-Jui Kuo , Chung-Shi Liu
IPC分类号： B08B3/00 , C11D11/00 , H01L21/67 , H01L21/02 , C11D7/06 , C11D7/32 , H01L23/00
CPC分类号： C11D11/0047 , C11D7/06 , C11D7/3218 , H01L21/02071 , H01L21/67051 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/03912 , H01L2224/0401 , H01L2224/05572 , H01L2224/05583 , H01L2224/05644 , H01L2224/05647 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/1147 , H01L2224/1181 , H01L2224/13005 , H01L2224/13083 , H01L2224/13111 , H01L2224/13116 , H01L2224/13118 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13169 , H01L2224/13171 , H01L2224/13172 , H01L2224/13184 , H01L2924/00014 , H01L2924/01079 , H01L2924/01082 , H01L2924/206 , H01L2924/01047 , H01L2924/01029 , H01L2224/05552
摘要： Methods and chemical solvents used for cleaning residues on metal contacts during a semiconductor device packaging process are disclosed. A chemical solvent for cleaning a residue formed on a metal contact may comprise a reactive inorganic component and a reactive organic component. The method may comprise spraying a semiconductor device with a chemical solvent at a first pressure, and spraying the semiconductor device with the chemical solvent at a second pressure less than the first pressure.

8. 发明授权

US09576830B2 Method and apparatus for adjusting wafer warpage 有权
标题翻译：调整晶片翘曲的方法和装置
公开(公告)号：US09576830B2
公开(公告)日：2017-02-21
申请号：US13475790
申请日：2012-05-18
申请人： Hui-Min Huang , Chih-Wei Lin , Wen-Hsiung Lu , Ming-Da Cheng , Chung-Shi Liu
发明人： Hui-Min Huang , Chih-Wei Lin , Wen-Hsiung Lu , Ming-Da Cheng , Chung-Shi Liu
IPC分类号： H01L21/687 , H01L21/67 , H01L21/683
CPC分类号： H01L21/67288 , H01L21/6838
摘要： A method for adjusting the warpage of a wafer, includes providing a wafer having a center portion and edge portions and providing a holding table having a holding area thereon for holding the wafer. The wafer is placed onto the holding table with the center portion higher than the edge portions and thereafter pressed onto the holding area such that the wafer is attracted to and held onto the holding table by self-suction force. The wafer is heated at a predetermined temperature and for a predetermined time in accordance with an amount of warpage of the wafer in order to achieve a substantially flat wafer or a predetermined wafer level.
摘要翻译：一种用于调整晶片翘曲的方法，包括提供具有中心部分和边缘部分的晶片，并提供其上具有用于保持晶片的保持区域的保持台。将晶片放置在保持台上，其中心部分高于边缘部分，然后按压到保持区域上，使得晶片通过自吸力被吸引并保持在保持台上。根据晶片的翘曲量将晶片在预定温度下加热预定时间，以便实现基本上平坦的晶片或预定的晶片级。

9. 发明授权

US09219030B2 Package on package structures and methods for forming the same 有权
标题翻译：包装结构及其形成方法
公开(公告)号：US09219030B2
公开(公告)日：2015-12-22
申请号：US13526073
申请日：2012-06-18
申请人： Chen-Hua Yu , Mirng-Ji Lii , Chung-Shi Liu , Meng-Tse Chen , Wei-Hung Lin , Ming-Da Cheng
发明人： Chen-Hua Yu , Mirng-Ji Lii , Chung-Shi Liu , Meng-Tse Chen , Wei-Hung Lin , Ming-Da Cheng
IPC分类号： H01L23/498 , H01L21/78 , H01L23/00 , H01L21/56 , H01L25/10 , H01L23/31 , H01L25/03 , H01L25/00
CPC分类号： H01L24/05 , B23K35/001 , B23K35/0222 , B23K35/22 , B23K35/262 , B23K35/3613 , H01L21/561 , H01L23/3135 , H01L23/3178 , H01L23/498 , H01L23/49816 , H01L24/08 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/03 , H01L25/0652 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/05572 , H01L2224/05611 , H01L2224/06181 , H01L2224/08113 , H01L2224/1184 , H01L2224/13005 , H01L2224/13014 , H01L2224/13022 , H01L2224/13023 , H01L2224/13026 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/1355 , H01L2224/13561 , H01L2224/1357 , H01L2224/13582 , H01L2224/136 , H01L2224/13666 , H01L2224/1412 , H01L2224/14181 , H01L2224/16104 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/17051 , H01L2224/48091 , H01L2224/48227 , H01L2224/81815 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/014 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/381 , H01L2924/3841 , H01L2924/00 , H01L2224/81 , H01L2924/01047 , H01L2924/01029 , H01L2924/01083 , H01L2924/013 , H01L2924/206 , H01L2224/05552 , H01L2924/00012
摘要： The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small.
摘要翻译：形成封装封装（PoP）结构的机构的所述实施例包括将具有非焊料金属球的连接器与包装衬底结合。非焊接金属球可以包括焊料涂层。具有非焊接金属球的连接器可以基本保持连接器的形状并控制上部和下部封装之间的结合结构的高度。具有非焊接金属球的连接器也不太可能导致连接器之间的桥接或接合连接器的断开（或冷接头）。结果，可以将具有非焊接金属球的连接器的间距保持较小。

10. 发明授权

US09123763B2 Package-on-package (PoP) structure having at least one package comprising one die being disposed in a core material between first and second surfaces of the core material 有权
标题翻译：封装封装（PoP）结构，其具有至少一个封装，其包括一个管芯，其设置在芯材料的芯材料的第一和第二表面之间
公开(公告)号：US09123763B2
公开(公告)日：2015-09-01
申请号：US13271952
申请日：2011-10-12
申请人： Chen-Hua Yu , Chung-Shi Liu , Mirng-Ji Lii , Ming-Da Cheng , Chih-Wei Lin
发明人： Chen-Hua Yu , Chung-Shi Liu , Mirng-Ji Lii , Ming-Da Cheng , Chih-Wei Lin
IPC分类号： H01L23/48 , H01L21/683 , H01L23/538 , H01L21/56 , H01L25/10 , H01L21/36 , H01L23/31 , H01L21/48 , H01L23/00 , H05K1/18 , H01L23/498
CPC分类号： H01L25/50 , H01L21/31051 , H01L21/4846 , H01L21/4853 , H01L21/4857 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L21/76819 , H01L21/76877 , H01L21/76898 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5383 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L2221/68345 , H01L2224/04105 , H01L2224/12105 , H01L2224/13082 , H01L2224/131 , H01L2224/16225 , H01L2224/16237 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/73204 , H01L2224/73253 , H01L2224/73267 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/83104 , H01L2225/06513 , H01L2225/06548 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H05K1/185 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2924/0665 , H01L2224/48
摘要： A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL.
摘要翻译：封装封装（PoP）结构包括第一封装和第二封装。第一包装包括第一模具，第二模具和芯材料。芯材料具有第一表面和第二表面。第一再分配层（RDL）位于第一表面上，第二RDL位于第二表面上。第一模具设置在第一表面和第二表面之间的芯材料中。第二管芯耦合到第一RDL和第二RDL之一。第二包装包括第三管芯和插入件。插入器具有第一侧和第二侧。第三裸片耦合到插入器的第二侧。第一封装通过耦合到插入件的第二侧和第一RDL的第一电连接器耦合到第二封装。

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